A HARDWARE PROTOTYPE FOR INTEGRATION, TEST AND VALIDATION OF AVIONIC NETWORKS
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1 A HARDWARE PROTOTYPE FOR INTEGRATION, TEST AND VALIDATION OF AVIONIC NETWORKS Jose-Philippe Tremblayl, Yvon Savaria1, Claude Thibeault2, Safwen Bouanen2 & Guchuan Zhu1 1 10/10/2013, 1. Ecole Poly technique de Montreal, 2. Ecole de Technologie Superieure
2 1. Introduction 2. Network architecture 3. Global approach 4. Implementation details 5. Prototype validation 6. Conclusion 2 10/10/2013
3 ) Current trends in the avionics domain -Ever increasing number of functions -Information flow increase -Stringent reliability requirements -Diversity in the transducers market -Migration to IMA architecture 3 10/10/2013
4 ) Main issues in transducer's integration -Different types of transducers -Different communication protocols -Significant design effort -Very costly and time consuming ) Solution -Systematic design approach -Normalized interfaces -Prototyping flexibility 4 10/10/2013
5 ) IEEE Standard for a Smart Transducer Interface for Sensors and Actuators ) Adoption Advantages -Increased compatibility -Reduced design effort -Reduced effort for installation, update, replacement or movement ) Considered but not yet adopted by the avionics domain 5 10/10/2013
6 TolFrom user Network Transducer Network Spe,cific Communication Transducer Interface Module Transduc,er Analog Interfac,e Service Module TEDS Module Gateway Service Module N,etwork Capable Application Proc,essor Communication Communication Module Module IEEE 1451 Reference Model 6 10/10/2013
7 ) Improvements over the basic IEEE Improved reliability j NCAP] Field Busses - I I Tllvl I Adjustable by the number of NeAP and Busses -Improved performances -Improved resources utilization -Completely generic for any class of application -Reconfigurable 7 10/10/2013 ToIFrom user Network j NCAP2 I Tllvl 2 I I I I I 1 NCAPN - Field Busses I I I I I TllvI M Generic Architecture
8 ) Main objective - Proposition of a systematic approach to validate new technological choices and their integration under important constraints ) Particular consideration for a compatibility with any certification process such as DO-254/DO Compatible with current an future design - Supports new verification constructs - Tests should be easy to create, maintain and alter Requirements Definition Architecture Optimization,,. Hardware Implementation,,. Test Cases Generation 'If Prototype Validation 8 10/10/2013
9 ) Requirements definition - Modeled on traditional avionics requirements ) Architecture optimization -Generation of a configuration matching the specified requirements Requirement Failure Rate Load Determinism Frame's Latency Bandwidth Constraint < 10e-6 < 50% Fully Deterministic <2ms 1 Mbit/s L (Frame's Lenght * Nb of Frame) Load = Transmission Interval * Bandwidth Typical ARINC 825 requirement 9 10/10/2013
10 ) Hardware Implementation -Connectivity: COTS sensor, transd ucer emulator, commercial software and PC platform ) Test Cases Generation -Valid ation of custom fault management mechanisms -Supports specific purpose such as any certification process, maintenance or integration of new components -Motivation behind a custom latency measurement system Customized tools best suited for global approach Provides a better visualization at the system level 10 10/10/2013
11 1. Introduction 2. Network architecture 3. Global approach 4. Implementation details 5. Prototype validation 6. Conclusion 11 10/10/2013
12 ) Architecture optimization -Configuration for the connection of 4 sensors to the main network for a critical system ARINC825 TIM! I 4 Sensors - NCAP! AFDX Network - NCAP2 L- TIM 2 I-- 4 Sensors ARINC /10/2013 Network architecture
13 ) Prototype platform -2 SP605 Xilinx FPGA l\lo dule Single.,L, ' :', C 825 '. " tc ontroller 8:516 LUT., 0/0... R,egis te 1101,51 4% Boards -2 ISM Networking Dnal ', ARI -C 825 Controller % 2126,8% Boards TI " I 's S,e:I'\I'j e l1 adu1e % % ) Implementation of selected protocols '." ", s ' e.n;:) ' CAP S '. )JI odu1e Vo!: 850, '. 3 % -Field bus: ARINC825 Tml - NICMl ,6 14% 2943 :5 0/ % 11% -Sensor Interface: I2C Total....uwtedOl'\f 2149,8 10% % 13 10/10/2013 Architecture's complexity
14 TIM C Tem peratu re sensor To End System 14 10/10/2013 Prototype Implementation
15 ) The VHDL custom implementation allowed the inclusion of novel fault management schemes ) Redundancy management is based on the error containment system -Bus is shut off upon the degrad ation on bus on either transmission or reception Enrm Passive Warn i n (] Limit._._._._ _._._._.- Error Active Transmitter Error Count Vs Mode of error 15 10/10/2013 Receiver Error Count Vs Mode of error
16 ) Test Cases Generation -Specific test designed for selected requirements at the required level ) Connection with commercial software ADS2 -Bandwidth valid ation of ARINC 825 -Tests generation at higher levels of abstraction ) Custom latency measurement -Integrated to the time synchronization mechanism of ARINC 825 -Compensation for extra transmission time due to bit stuffing 16 10/10/2013
17 ) Validation of the requirements -The maximum latency is inferior to 2 ms -The maximum load in normal mode is inferior to 500/0 -The slight variation of latency for each frame during each transmission cycle indicates a deterministic traffic Sensor Latency (Cycle) Latency (us) la Field Bus Condition Max Latency (us) Load 2A A Normal % 4A bus off 1.05 Network Load 53 % IB B B B /10/2013 Average Frame's Latency
18 ) Identification of an unforeseen problem in our custom fault management mechanism -Upon degrad ation of a bus, retransmissions caused frames to miss their deadline -None of our mod els pred icted this worst case situation occurring only during reconfiguration ) Final improvement -Modification over the original scheme to correct the problem and respect the requirements - A better knowledge of the standard is helpful in the id entification and correction of this problem 18 10/10/2013
19 ) New approach for design and validation of an avionic network -The prototyping platform grants an increase connectivity and flexibility -The proposed approach is compatible with any certification process ) Future work -Automatic optimization of the architecture under a specific set of constraints -Valid ation of new algorithms and novel sensor designs 19 10/10/2013
20 20 10/10/2013 ;>,.
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