CBMnet as FEE ASIC Backend

Transcription

1 CBMnet as FEE ASIC Backend 17th CBM Collaboration Meeting P2 FEE/DAQ/FLES University of Heidelberg Computer Architecture Group, Ulrich Brüning

2 Outline Motivation Front-end ASIC CBMnet implementation Structure Features Existing operational Modules Functions under Development HUB-ASIC CBMnet Structure HUB ASIC Structure Workpackages Conclusion & Outlook 2

3 Motivation CBMnet delivers a CBM specific implementation High Bandwidth for CBM requirements Including a synchronization mechanism Unified communication over one bidirectional link (possibly unbalanced ) Creation of a standardized CBMnet front-end ASIC building block Integration into different types of front-ends possible Generalized easy to use interface One DAQ frontend read-out chain used in several parts of the experiment 3

4 Front-end ASIC CBMnet Structure Data 1x, 2x or 4x Analog LVDS Blocks Analog Delay Elements Standard Cell SerDes CBMnet Protocol Modules CBMnet interface Analog HW Data LVDS DLM CLK LVDS SERDES 8b/10b CBMnet Data RF Control LVDS Control CBMnet Digital Front-end Block GPRF GPRF : General Purpose Register File SPRF SPRF : Special Purpose Register File I2C/JTAG

5 Features of CBMnet CBMnet V1.0 Features Planned additional CBMnet V2.0 extensions Communication over one optical link supporting DTM, DCM and DLM Optimized data utilization about 91 % ( about 73 % considering 8b/10b) Optimized easy to use Interface Highly modular CBM LP code structure Special adapted routing scheme Fast and efficient administration packets Retransmission for Control Packets System wide clock recovery with low jitter Deterministic link latency feature for well defined Deterministic Latency Messages Lane handling for unbalanced communication Support for large messages within hardware Planned data loss strategy in cases of overloads at the end of epochs Communication also reliable for data stream Meta data detection adaption to find Meta data within message streams in early system stages

6 Existing operational Modules CBMnet V1.0 stable working within several FPGA solutions Changes for V2.0 can thereby be tested efficiently All modules are ASIC ready implemented Only XML description for RF required Readout Controller Data Combiner Board Active Buffer Board

7 Cosy Beamtime December meter cables to ABB and ECS 50 meter cable to read-out controller DCB Jitter cleaner device 7

8 Functions under Development Digital design parts under construction Register File Control Module CBM V2.0 protocol changes SERDES Modules clk res_n link_active link_clk ctrl2send_stop ctrl2send_start ctrl2send_end ctrl2send 16 Control Message Send Analog parts required for CBMnet read-out Delay Cells LVDS Cells FEE User Module data2send_stop data2send_start data2send_end data2send crc_error_send dlm2send_va dlm2send_type dlm_rec_type dlm_rec_va crc_error_rec data_rec data_rec_start data_rec_end data_rec_stop ctrl_rec ctrl_rec_start ctrl_rec_end ctrl_rec_stop Data Message Send DLM - Send DLM - Receive Data Message Receive Control Message Receive Generic CBMnet Module Generic CBMnet control block for FEE ASICs First implementation for SPADIC together with Tim Armbruster

9 Interface - Data Send Example Interface optimzed for easy and efficient data transmission Variant of valid-stop synchronization All protocol specific features like initialization, retransmission are not visible for users

10 CBMnet Structure 1x 4x FEE FEE Hub 12x 12x 12x 48x Data flow FEE Detector Frontend Low Bandwidth FEE Hub FEE FEE 500 Mbit/s each Gbit/s each E/O DPB 5 10 Gbit/s each Control flow and Synchronization High Bandwidth Computing Cluster ECS 10

11 HUB ASIC Structure Phasealigner Registerfile DLM Linkinit SERDES LPO LPI LPI LPO CDR SERDES SERDES LPO LPI 1x - 4x connection to each die Gbit/s total per die Maximum of 48 connections 12x connection Gbit/s total Designed for fault tolerance 11

12 Workpackages Design tasks Analysis and adaption of CBM link port CBM protocol V2.0 has to be made ASIC ready Dynamic configuration for 1x, 2x, 4x Serializer and CDR at 2.5 Gb/s 5Gbit/s (CBM group in India) Clock distribution uses clock line at 500MHz Serializer at 500Mb/s interface, 8B/10B coded, phase alignment Low level initialization and hub configuration Special crossbar implementation Complete deterministic design Fault correction, redundancy for lanes etc. 12

13 Workpackages Backend tasks Process technology decision Collection of IPs and libs Integration and backend design Radiation tolerant design Test & Verification tasks Verification FPGA prototyping (in cooperation with KIP/Frankfurt) ASIC prototyping (ZITI and CBM group India) Other tasks Project planning Coordination 13

14 Conclusion & Outlook CBMnet prototyping was successful CBMnet logic will be included into SPADIC front-end ASIC Generation of reusable front-end ASIC read-out building block HUB CBM planning has to be continued Boundary conditions has to be solved 14

15 Thank you for your attention! Questions? 15