Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs

Transcription

1 pplication Note C105 esigning High-Speed TM Switch Fabrics by Using ctel FPGs The recent upsurge of interest in synchronous Transfer Mode (TM) is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant characteristic of TM is that it requires minimum cell processing in network nodes and in links such as repeaters, bridges, and routers. This means that TM allows systems to operate at rates much higher than current packet-switching systems allow. This improved performance is due to higher media quality and to TM operation in a connection-oriented mode that guarantees minimum packet loss. This low packet loss is the result of not granting entrance to the network until completion of a setup phase that allocates all necessary network resources. To reduce the size of the internal buffers in switching nodes, and thus to reduce the queuing delays in these buffers, the information field length in TM packets is kept relatively small. s a result, as packet size goes down, the speed requirement for each switching node on the network goes up. In general, to keep packet loss to a minimum, the throughput of TM switching nodes must be in the 1-gigabit-per-second range. This application note describes how to design typical high-speed switch fabrics that route TM packets on broadband networks. Switch fabric is a term used to denote a large group of basic switching building blocks connected in a specific topology. The design, analysis, and implementation of these building blocks will be described. TM Switching pplications One of the main tasks of an TM switching node is to transport TM cells at high speed from its input ports to its destination output ports. This task is performed by the switch fabric. The switch fabric establishes a connection between an arbitrary pair of input and output ports. Switch fabrics usually consist of identical basic units called switching elements. The switching elements are interconnected in a specific topology to create the switch fabric. The ctel CT 3 family of FPGs, with their high-speed multiplexer-based architectures, are, as will be seen in this application note, an excellent fit for applications, such as TM switching, that stress the heavy use of multiplexing. This application note will describe in detail the designs of two typical high-speed TM switches: pipelined 16:16 switch fabric 16:16 multipath interconnect (MIN) switch fabric Pipelined 16:16 FPG Switch Fabric One of the simpler FPG approaches to TM switch fabric design is shown by the straightforward 16:16 multiplexing scheme in Figure 1. This switch fabric design is known as a single-path network, because the same path is always used from any given input to a given output. In this example, the switch fabric has 16 input ports and 16 output ports. To achieve connectability, it employs 16 16:1 multiplexers called FFMX16 s (Figure 2). ach of the 16 FFMX16s uses five ctel FM6 basic 4:1 multiplexed flip-flops connected in two pipelined stages. 16-bit input bus Switch Select 4 16:1 mux Figure 1 16:16 asic Multiplexer Switch Fabric 1 16:1 mux 2 Switch Select 4 16 Switch Select 4 16:1 mux Output 1 Output 2 Output 16 5 pril ctel Corporation

2 0 0 Q FM Q FM6 0 Q FM6 0 Q FM Q FM6 Figure 2 Two-Stage Pipelined 16:1 Multiplexer (FFMX16) ach FM6 (Figure 3) is a 4:1 multiplexer driving a flip-flop and occupies a single ctel CT 3 sequential logic module. This multiplexed flip-flop introduces only one level of logic delay in the design. In this implementation, once each of the two stages of the 16:1 multiplexer is full, the pipeline outputs data on every subsequent clock cycle. Thus, these 16:1 multiplexers are effectively implemented in one logic level, providing improved throughput. 0 Q FM6 Figure 3 Multiplexed Flip-Flops FM6 Switch Fabric riving Circuit The driving circuit for each of the FFMX16s in the 16:16 switch fabric is shown in Figure 4. s shown in the figure, selecting data for the output of each FFMX16 requires 64 signals. This number is based on the need for four switch-select inputs (,,, and ) for each of the FFMX16s. Switch-select signals and operate with the first stage of each multiplexer, and select signals and operate with the second stages. drive signal is received as a serial bit stream (SL) that is converted to parallel form by a 64-bit serial-to-parallel shift register (SIPO64). Input data to the switch is received on the lines [15:0]. Notice that the FFMX16 shown in Figure 4 represents 16 FFMX16s, so the inputs are 16 bits wide. It takes two clock cycles to fill the FFMX16 pipeline, after which data is present on the OUTP[15:0] bus at each clock cycle. The 64-bit data selection word S[63:0] from the shift register is divided into four groups of 16 bits each, which are used to select the appropriate routing through the switch fabric. Note that there are separate clock lines for both the shift register and for the switch fabric so that data can be clocked to the output bus at a rate different from that of the shifted control bits. 5-20

3 esigning High-Speed TM Switch Fabrics by Using ctel FPGs SL INUF P SIPO64 P SHIFT UF SHIFTIN INUF CLOCK P SHIFTN INUF SHN P NL S63 Q63 S62 Q62 Q61 S61 Q60 S60 S59 Q59 S58 Q58 S57 Q57 Q56 S56 Q55 S55 S54 Q54 S53 Q53 S52 Q52 Q51 S51 Q50 S50 S49 Q49 S48 Q48 S47 Q47 Q46 S46 Q45 S45 S44 Q44 S43 Q43 S42 Q42 Q41 S41 Q40 S40 9 Q39 8 Q38 7 Q37 Q36 6 Q Q34 3 Q33 2 Q32 Q31 1 Q Q29 8 Q28 7 Q27 Q26 6 Q Q24 3 Q23 2 Q22 Q21 1 Q Q19 8 Q18 7 Q17 Q16 6 Q Q14 3 Q13 2 Q12 Q11 1 Q10 0 S9 Q9 S8 Q8 S7 Q7 Q6 S6 Q5 S5 S4 Q4 Q3 Q2 Q1 Q S63,S59,S55,S51,S47,S43,9,5,1,7,3,9,5,1,S7, S62,S58,S54,S50,S46,S42,8,4,0,6,2,8,4,0,S6, S61,S57,S53,S49,S45,S41,7,3,9,5,1,7,3,S9,S5, S60,S56,S52,S48,S44,S40,6,2,8,4,0,6,2,S8,S4, Q[15:0] 7 OUTUF OUTP[15:0] P 8 FFMX16 9 $RR= $RR=16 5 INP[15:0] INUF P [15:0] $RR=16 P HUF P UF Figure 4 Top Level View of the 16:16 Switch Fabric esign 5 Using CTgen Macro uilder The 64-bit serial-to-parallel shift register (SIPO64) is generated by the ctel macro generator, CTgen included with esigner Series software packages. With CTgen s graphical user interface, you can build structured macros (counters, adders, etc.) by simply clicking on a few menu choices. The CTgen Macro uilder then creates functions that effectively use the ctel architecture. ach macro is developed with the goal of limiting module count, maximizing performance, and restricting loading to acceptable levels. In this design, the SIPO64 is generated by simply choosing the desired parameters from CTgen s graphical user interface (64-bits, serial-to-parallel, active-low clear, active-high shift enable, and positive-edge triggered clock). The created shift register is then instantiated in the design with no need for simulation. The CTgen macros are already tested to guarantee correct functionality. Note: In the N:N multiplexed structure shown here, any given input may be broadcast to all outputs simultaneously. lso, an advantage of this approach is that after only two clock cycles, the pipeline is full and ready to output data. disadvantage of this scheme is that it allows only one possible path, and no alternative paths, between each input and output. To implement a multiple-path capability, multiples of this switch fabric can be cascaded together. However, a better solution is the MIN switch fabric. 16:16 Multipath Interconnect (MIN) Switch Fabric The primary advantage of a multipath interconnect network (MIN) is that it permits the creation of alternative paths between a given input and a given output in order to avoid possible packet collisions. One implementation of a MIN switch is the two-section anyan network shown in Figure 5. This network consists of four stages that drive a second group of four. The second group is made up of the first four stages with a reversed topology it is the mirror image of the first. dding this second half produces a complete MIN switch fabric in a minimum number of stages. The first four stages (see Figure 5) enable any output to be reached from any input via one specific path. This is the standard anyan configuration. The second four stages use a reversed anyan topology. Together, the two sections provide the multiplicity of paths required for a MIN switch fabric. That is, in an N:N MIN switch fabric, N internal paths are available to reach any output from an arbitrary input. ach basic switching element used in this switch fabric is a 2:2 switch. (See Figure 6.) epending on the value of switch line, the data will be either passed or crossed between the input and output lines. Figure 7 shows the implementation of the basic switching element using ctel FM1 CT 3 multiplexed flip-flops. s shown in the figure, two multiplexed flip-flops are required to implement the switching element. The truth table for the basic switching element shown is given in Table

4 16:16 anyan network 16:16 Reversed anyan network Legend = 2:2 basic switching element Figure 5 16 X 16 Mulltipath Interconnect Network (MIN) Switch Fabric 2:2 Mux Figure 6 Possible Signal Paths in a 2:2 asic Switching lement 5-22

5 esigning High-Speed TM Switch Fabrics by Using ctel FPGs S Q FM1 Q FM1 S Figure 7 2:2 asic Switching lement CLL Table 1 Truth Table for 2:2 asic Switching lement CLL Clock nable ssuming an N:N MIN switch fabric, the number of stages in the network is 2log 2 N. If N = 16 (as in the present case), the MIN switch fabric is implemented in eight stages. Thus, a 16:16 MIN can be constructed of eight stages, with each stage consisting of eight 2:2 basic switching elements. Switch Fabric riving Circuit The driving circuit for the MIN network is similar to the one used for the multiplexer-based switch fabric described in the previous section. s shown in Figure 8, the switching elements (CLL) are connected to each other to implement the topology shown in Figure 5. The lines of the switching elements are driven by the outputs (S[63:0]) of a 64-bit shift register. The S[63:0] signals are received as a serial bit stream (SL) and are converted to parallel form by a 64-bit serial-to-parallel shift register (SIPO64). Input data to the switch is received on the lines IN[15:0] and is clocked to the outputs once the CLLs are enabled. It takes eight clock cycles to fill the switch fabric pipeline, after which data is present on the OUTP[15:0] bus at each clock cycle. The 64 bits of the data selection word (S63:) from the shift register are used to select the appropriate routing through the switch fabric. Note that there are separate clock lines for the shift register and for the switch fabric so that data can be clocked to the output bus at a rate different from that of the shifted control bits S[63:0]. Switch X 1 X s in previous state s in previous state Notes: = Triggered on positive edge of clock X = on t care Note: The complete multipath interconnect switch fabric is implemented by using 128 (8 x 8 x 2) multiplexed flip-flops of the type FM1. The straight multiplexed switch structure discussed in the previous section requires 80 (5 x 16) FM6 multiplexed flip-flops. However, this size differential does not translate for larger values of N (where N is the number of input and output ports). s N gets larger, the number of modules required to implement the MIN network does not increase as rapidly as it does for the simple mux-structured network. lso, notice that the multiplexed flip-flop used in the MIN network is a 2:1 type, whereas the straight mux switch fabric requires a 4:1 type. The 2:1 multiplexed flip-flop offers the advantage that, because of its lower fanin, it is easier to route on the ctel software

6 SL INUF P P INUF INUF P SHN SIPO64 SHIFTIN CLOCK SHIFTN Q63 Q62 Q61 Q60 Q59 Q58 Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S S9 S8 S7 S6 S5 S4 IN0 IN1 N IN2 IN3 N IN4 IN5 N IN6 IN7 N IN8 IN9 S4 N IN10 IN11 S5 N CLL CLL CLL CLL CLL CLL L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L110 L111 N N N N N N L10 L12 S8 L14 L16 S9 L18 L110 0 L112 L114 1 L11 L13 2 L15 L17 3 CLL CLL CLL CLL CLL CLL L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L210 L211 N N N N N N L20 L22 6 L24 L26 7 L21 L23 8 L25 L27 9 L28 L210 0 L212 L214 1 CLL CLL CLL CLL CLL CLL L30 L31 L32 L33 L34 L35 L36 L37 L38 L39 L310 L311 N P UF N IN12 IN13 S6 N CLL L112 L113 N L19 L111 4 CLL L212 L213 N L29 L211 2 CLL L312 L313 UF IN14 IN15 S7 N CLL L114 L115 N L113 L115 5 CLL L214 L215 N L213 L215 3 CLL L314 L315 P SHIFT INP0 P INUF IN0 INP4 P INUF IN4 INP8P INUF INP1 P INUF IN1 INP5 P INUF IN5 INP9 P INUF INUF INUF INUF INP2 P IN2 INP6 P IN6 INP10P INUF INUF INUF INP3 P IN3 INP7 P IN7 INP11P IN8 INP12 P INUF IN9 INP13 P INUF INUF IN10 INP14 P INUF IN11 INP15 P IN12 IN13 IN14 IN15 P HUF Figure 8 Top-Level View of the MIN Switch Fabric esign Timing nalysis The MIN switch fabric discussed here can be implemented in most ctel CT 3 devices, such as the 1425, the 1440, 1460, and the The timing analysis given in this section was obtained from the The MIN switch fabric can be operated as fast as the slowest switching element can switch its data from input to output. The basic switching element has a 5.7 ns clock-to-q (input-to-output) delay, along with 0.7 ns of setup time. Hence, the maximum frequency of the switch fabric clock is 156 MHz. In a 16:16 switch, this provides a maximum throughput of 2.5 gigabits per second. Note that it takes eight clock cycles for data to move from the switch fabric input to its output (about 51.2 ns). However, as in all such pipelines, once all stages of the network are filled up, data is output at every subsequent clock cycle. Conclusion The basic concept behind switch fabrics is multiplexing data from input ports to output ports. The multiplexer-based architecture of ctel FPGs fits this requirement. High-speed switching networks of almost any topology can be implemented efficiently using the multiplexed flip-flops in the ctel library. ach of these flip-flops is mapped to only one sequential module within the FPG to take maximum advantage of the die area within the chip. 5-24

7 5-25 esigning High-Speed TM Switch Fabrics by Using ctel FPGs 5 Figure 8 Top-Level View of the MIN Switch Fabric esign (continued) L815 L814 L813 L812 L811 L810 L89 L88 L87 L86 L85 L84 L83 L82 L81 L80 L715 S56 S48 S40 L76 L75 L74 L73 L72 L71 L70 S47 L513 N L515 L64 S49 S50 S51 L67 S54 L611 L610 L69 L63 L62 L61 L60 L512 L58 L55 L54 L51 L52 L610 S41 9 L414 N L415 L512 L513 L514 L515 L511 L510 L59 L58 L57 L56 L55 L54 L52 L51 L50 L412 L410 L49 6 L46 5 L45 L44 4 L43 3 L42 L41 L40 2 L42 L43 L41 L40 P OUTUF P OUTUF OUTUF P P OUTUF OUTUF P P OUTUF OUTUF P OUTUF P L514 L510 L56 L50 L413 CLL CLL N N N N N N N N N N N N N N N N N N N N N N N N N N N N L77 L714 L713 L712 CLL L711 L710 L79 L78 L615 L614 L613 L68 L66 L65 L57 L53 L511 L59 L411 L48 L47 CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL CLL 7 8 S42 S43 S44 S45 S46 L612 S52 S53 S55 S57 S58 S59 S60 S61 S62 S63 N OUTUF P OUTUF P P OUTUF OUTUF P P OUTUF OUTUF P P OUTUF P OUTUF L81 L82 L83 L84 L85 L86 L87 L88 L89 L810 L811 L812 L813 L814 L815 OUTP0 OUTP1 OUTP2 OUTP3 OUTP4 OUTP5 OUTP6 OUTP7 OUTP8 OUTP9 OUTP10 OUTP11 OUTP12 OUTP13 OUTP14 OUTP15 CLL CLL CLL CLL CLL CLL CLL L30 L31 L34 L35 L37 L38 L310 L39 L311 L312 L314 L313 L36 CLL L32 4 L N N N N 8 N 9 N 0 N L315 1 N L45 L44 L46 L47 L49 L48 CLL CLL L410 L411 L412 L413 L414 L415 N L53 L615 L614 L613 L612 L611 L69 L68 L67 L66 L65 L64 L60 L61 L63 L62 L715 L713 L712 L711 L710 L79 L78 L77 L76 L74 L73 L72 L71 L70 L75 L714 L80

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