EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) FPGA Overview

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1 EECS150 - igital esign Lecture 3 - Field Programmable Gate rrays (FPGs) January 27, 2009 John Wawrzynek Spring 2009 EECS150 - Lec03-FPG Page 1 FPG Overview asic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block. Simplified version of FPG internal architecture: Spring 2009 EECS150 - Lec03-FPG Page 2

2009 EECS150 - Lec03-FPG Page 3 Xilinx Technology rives Performance in MW Williams Formula One Race Car at 2003 Grand Prix Sep 2, 2003 18:08 ET Xilinx-Enabled WilliamsF1 MW FW25 Challenges Ferrari

Far more designs are implemented in FPG than in custom chips. SN JOSE, Calif., Sept. 2 /PRNewswire/ -- t the Indianapolis 2003 Grand Prix today, Xilinx, Inc.

2 ie Photos: Virtex FPG vs. Pentium IV FGP Vertex chip looks remarkably structured Very dense, very regular structure Full-Custom Pentium chip somewhat more random in structure Large on-chip memories (caches) are visible Spring 2009 EECS150 - Lec03-FPG Page 3 Xilinx Technology rives Performance in MW Williams Formula One Race Car at 2003 Grand Prix Sep 2, :08 ET Xilinx-Enabled WilliamsF1 MW FW25 Challenges Ferrari for the Win Xilinx-Enabled WilliamsF1 (PRNewsFoto) FPG also get used in many (not as interesting) products: network routers, set-top boxes, printers, etc. Far more designs are implemented in FPG than in custom chips. SN JOSE, Calif., Sept. 2 /PRNewswire/ -- t the Indianapolis 2003 Grand Prix today, Xilinx, Inc. (NS:XLNX) programmable chips will play a mission-critical role in the performance of the MW WilliamsF1 Team. The MW WilliamsF1 Team is the leading contender in the 2003 Formula One Series, currently heading the FI Formula One Constructors' Championship. fter a closely fought race in Monza, Italy, between Ferrari, MW Williams and McLaren, the outcome of today's U.S. Grand Prix race could hold the key to the entire 2003 FI Formula One Championship. The season concludes with a final race in Suzuka, Japan on October 12. The teams and drivers who remain in contention are acutely conscious that wins and losses will come at the margins of performance, and no one can afford anything less than a faultless race. The MW WilliamsF1 Team selected high performance programmable chips from Xilinx as the leading technology in the Vehicle Control Module (VCM) of the team's 2003 Challenger -- the WilliamsF1 MW FW25. The Xilinx-enabled VCM is used to control essential vehicle components such as the gearbox, differential, traction control, launch control and telemetry. With leading edge technology -- greater on-chip functionality and lower power consumption, Xilinx FPGs have ensured that the VCM unit is reduced in size and weight, ultimately enhancing the performance of the car. Spring 2009 EECS150 - Lec03-FPG Page 4

FPG Variations Families of FPG s differ in: physical means of implementing user programmability, arrangement of interconnection wires, and the basic functionality of the logic blocks.

Lec03-FPG Page 5 User Programmability Latch-based (Xilinx, ltera, ) + reconfigurable volatile relatively large. Latches are used to: 1. make or break cross-point connections in the interconnect 2.

3 FPG Variations Families of FPG s differ in: physical means of implementing user programmability, arrangement of interconnection wires, and the basic functionality of the logic blocks. Most significant difference is in the method for providing flexible blocks and connections: nti-fuse based (ex: ctel) + Non-volatile, relatively small fixed (non-reprogrammable) Spring 2009 EECS150 - Lec03-FPG Page 5 User Programmability Latch-based (Xilinx, ltera, ) + reconfigurable volatile relatively large. Latches are used to: 1. make or break cross-point connections in the interconnect 2. define the function of the logic blocks 3. set user options: within the logic blocks in the input/output blocks global reset/clock Configuration bit stream can be loaded under user control Spring 2009 EECS150 - Lec03-FPG Page

4 Idealized FPG Logic lock 4-input look up table () implements combinational logic functions Register optionally stores output of Spring 2009 EECS150 - Lec03-FPG Page 7 ackground for Next Slide MUX or multiplexor is a combinational logic circuit that chooses between 2 N inputs under the control of N control signals. latch is a 1-bit memory (similar to a flip-flop). Spring 2009 EECS150 - Lec03-FPG Page 8

5 4- Implementation n-bit is implemented as a 2 n x 1 memory: inputs choose one of 2 n memory locations. memory locations (latches) are normally loaded with values from user s configuration bit stream. Inputs to mux control are the CL inputs. Result is a general purpose logic gate. n- can implement any function of n inputs! Spring 2009 EECS150 - Lec03-FPG Page 9 as general logic gate n n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination. Example: 4-lut Example: 2-lut Implements any function of 2 inputs. How many of these are there? How many functions of n inputs? Spring 2009 EECS150 - Lec03-FPG Page 10

FPG Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis, in case of using HL

6 FPG Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis, in case of using HL entry followed by, Partition, place, and route to create configuration bitstream file esign verification: Optionally use simulator to check function, Load design onto FPG device (cable connects PC to development board) Spring 2009 EECS150 - Lec03-FPG Page 11 Example Partition, Placement, and Route Idealized FPG structure: Example Circuit: collection of gates and flip-flops Circuit combinational logic must be covered by 4-input 1-output s. Flip-flops from circuit must map to FPG flip-flops. (est to preserve closeness to CL to minimize wiring.) est placement in general attempts to minimize wiring. Vdd, GN, clock, and global resets are all prewired. Spring 2009 EECS150 - Lec03-FPG Page 12

7 Example Partition, Placement, and Route OUT IN Example Circuit: collection of gates and flip-flops Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop. Spring 2009 EECS150 - Lec03-FPG Page 13 Xilinx FPGs (interconnect detail) Spring 2009 EECS150 - Lec03-FPG Page 14

Project platform: Xilinx ML505-110 Spring 2009

8 Project platform: Xilinx ML Spring 2009 EECS150 - Lec03-FPG Page 15 FPG: Xilinx Virtex-5 XC5VLX110T Virtex-5 die photo Spring 2009 EECS150 - Lec03-FPG Page 1 die is an unpackaged part!"#$%&'()

9 all Grid rray (G) Flip-Chip Package From die to PC board... Copper Heatspreader Thermal Interface Material Underfill Epoxy dhesive Epoxy* Flip Chip Solder ump Silicon ie Solder all Organic uild-up Substrate Spring 2009 EECS150 - Lec03-FPG Page 17!"#$%&'() NK 40 I/O NK 40 I/O NK 40 I/O NK 40 I/O Figure -3: anks of I/O placed on chip floor NK 20 I/O NK 20 I/O CONFIG NK 20 I/O NK 20 I/O NK 40 I/O NK 40 I/O NK 40 I/O NK 40 I/O ug190 03_02130 Virtex-5 XC5VLX30 I/O anks Colors on this package pinout map to banks. C E F G H J K L M N P R T U V W Y C E F C E F G H J K L M N P R T U V W Y C E F Spring 2009 EECS150 - Lec03-FPG Page 18!"#$%&'()

10 Colors represent different types of resources: Logic lock RM SP (LUs) Clocking I/O Serial I/O + PCI routing fabric runs throughout the chip to wire everything together.!"#$%&'() Routing fabric requires many interconnect layers.!"#$%&'()

11 Configurable Logic locks (CLs) Slices define regular connections to the switching fabric, and to slices in CLs above and below it on the die. CL Slice(1) Switch Matrix Slice(0) CIN CIN UG190_5_01_12205 The LX110T has 17,280 slices. Spring 2009 EECS150 - Lec03-FPG Page 21 X-Y naming convention for slices X0, X2,... are lower CL slices. X1, X3,... are upper CL slices. Y0, Y1,... are CL column positions. CL Slice X1Y1 CL Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CL Slice X1Y0 CL Slice X3Y0 Slice X0Y0 Slice X2Y0 Lower-left corner of the die. UG190_5_02_12205 Spring 2009 EECS150 - Lec03-FPG Page 22

12 toms: 5-input Look Up Tables (s) 5 [:2] (1) (0) (1). (0). [:2] Computes any 5- input logic function. Timing is independent of function (0) (1) Latches set during configuration. 23 Spring 2009 EECS150 - Lec03-FPG Page Virtex-5 -s: Composition of 5-s May be used as one -input ( out) or as two 5-input S ( and 5) Figure 3: lock iagram of a Virtex-5 -Input WP245_03_05100 The LX110T has 9,120 -s - delay is 0.9 ns Combinational logic (post configuration) Spring 2009 EECS150 - Lec03-FPG Page 24

13 ([:1]) (C[:1]) ([:1]) [:1] [:1] [:1] The simplest view of a slice SLI () () (C) (C) () () Four -s Four Flip-Flops Switching fabric may see combinational and registered outputs. ([:1]) () [:1] () () n actual Virtex-5 slice adds many small features to this simplified diagram. We show them one by one... Spring 2009 EECS150 - Lec03-FPG Page 25 SLI Two 7-s per slice... ([:1]) [:1] F7MUX (C[:1]) (CX) [:1] (CMUX) (C) Extra multiplexers(f7mux, F7MUX) () ([:1]) [:1] F7MUX Extra inputs (X and CX) (MUX) ([:1]) [:1] () (X) Spring 2009 EECS150 - Lec03-FPG Page 2

14 Or one 8-s per slice... SLI ([:1]) [:1] F7MUX (C[:1]) [:1] F8MUX Third multiplexer(f8mux) (CX) (MUX) ([:1]) [:1] F7MUX () Third input (X) ([:1]) (X) (X) () [:1] Configuring the n of an n-... Spring 2009 EECS150 - Lec03-FPG UG Page 27 Extra muxes to chose option... Inputs X FE/LT MUX From eight 5-s... to one 8-. C Inputs CX F7MUX F8MUX FE/LT C CMUX C Combinational or registered outs. Inputs X FE/LT MUX Flip-flops unused by s can be used standalone. Inputs X (X) F7MUX MUX FE/LT Spring 2009 EECS150 - Lec03-FPG Page 28 UG190_5_25_05050 Flip-flops...

15 Slice flip-flop properties... Output HIGH LOW Each state element may be edge-triggered or latch. X CX X X C Output Output Output C HIGH LOW HIGH LOW HIGH LOW C Reset Type Sync sync Clock enable, clock polarity, and set/reset lines in a slice are shared. Each state element may respond differently to set/reset signal. Next: The vertical dimension... Spring 2009 EECS150 - Lec03-FPG Page 29 Reminder: arithmetic addition... One-bit full adder Simplest multi-bit adder [Co,S] = + + Ci,, Ci: 1-bit number inputs. [Co,S]: 2-bit number output. + : rithmetic addition. Ripple-carry adder Spring 2009 EECS150 - Lec03-FPG Page 30

16 UG190_5_24_05050 From From X S3 (To Next Slice) I3 MUXCY Virtex 5 Verical Logic Carry Chain lock (CRRY4) CO3 O3 MUX/* MUX We can map ripple-carry addition onto carry-chain block. From C S2 MUXCY CO2 CMUX/C* From C CX I2 O2 CMUX C From S1 MUXCY CO1 MUX/* From X I1 O1 MUX From From X CO0 S0 MUXCY O0 I0 CYINIT CIN 0 1 CIN (From Previous Slice) MUX/* MUX * Can be used if unregistered/registered outputs are free. The carry-chain block also useful for speeding up other adder structures and counters. Putting it all together... a SLIL X X Reset Type Sync sync HIGH LOW MUX The previous slides explain all SLIL features. CMUX C C5 C4 C3 C2 C1 CX X X 0/1 C CX X X Spring 2009 EECS150 - Lec03-FPG Page HIGH LOW HIGH LOW HIGH LOW C C MUX MUX bout 50% of the 17,280 slices in an LX110T are SLILs. The other slices are SLIMs, and have extra features. 32 CIN UG190_5_04_0320

17 5 [:2] Recall: 5- architecture... (1) (0) (1). (0) (0) (1). [:2] 32 Latches. Configured to 1 or 0. Some parts of a logic design need many state elements. SLIMs replace normal 5-s with circuits that can act like 5-s, but can alternatively use the 32 latches as RM,, shift registers. Spring 2009 EECS150 - Lec03-FPG Page 33 Normal - inputs. Memory write address SLIM -... Memory data input I2 PRM4/32 SPRM4/32 L32 L1 RM I1 MC31 W-W W7 W8 Normal 5/- outputs. Memory data input. Control output for chaining s to make larger memories. 1.1 Mb distributed RM can be made if all SLIMs of an LX110T are used as RM. Spring 2009 EECS150 - Lec03-FPG Page 34

18 [7:0] W WE Many RM configurations possible... 8 () (WE/) RM25X1S I1 [:1] W[8:1] WE I1 [:1] W[8:1] WE I1 [:1] W[8:1] WE I1 [:1] W[8:1] WE SPRM4 SPRM4 SPRM4 SPRM4 F7MUX (X) F7MUX (CX) 7 (X) F8MUX O Output Registered Output UG190_5_14_05050 Example configuration: Single-port 25b x 1, registered output. complete list:! Single-Port 32 x 1-bit RM! ual-port 32 x 1-bit RM! uad-port 32 x 2-bit RM! Simple ual-port 32 x -bit RM! Single-Port 4 x 1-bit RM! ual-port 4 x 1-bit RM! uad-port 4 x 1-bit RM! Simple ual-port 4 x 3-bit RM! Single-Port 128 x 1-bit RM! ual-port 128 x 1-bit RM! Single-Port 25 x 1-bit RM 128 x 32b RM has a 1.1ns access time. Figure 5-14: istributed RM (RM25X1S) Spring 2009 EECS150 - Lec03-FPG Page 35 SLIM shift register (one of many). SHIFTIN () 32-bit Shift Register WE SHIFTOUT(31) ddress ([4:0]) 5 MUX UG190_5_1_05050 See Virtex-5 User Guide for an complete list of shift-register types. Spring 2009 EECS150 - Lec03-FPG Page 3

19 Spring 2009 EECS150 - Lec03-FPG Page SLIL vs SLIM... I2 X C CX X X I1 MC31 UG190_5_03_04100 I MUX C C CMUX MUX MUX Reset Type X W-W W7 W8 PRM4/32 SPRM4/32 L32 L1 RM PRM4/32 SPRM4/32 L32 L1 RM PRM4/32 SPRM4/32 L32 L1 RM PRM4/32 SPRM4/32 L32 L1 RM HIGH LOW HIGH LOW HIGH LOW HIGH LOW WSGEN CIN 0/1 WE Sync sync I2 I1 MC31 C CI CX C5 C4 C3 C2 C1 I2 I1 MC31 I X I2 I1 MC31 I X WE W-W W7 W8 W-W W7 W8 W-W W7 W8 X C CX X X UG190_5_04_0320 MUX C C CMUX MUX MUX X HIGH LOW HIGH LOW HIGH LOW HIGH LOW CIN 0/1 C CX C5 C4 C3 C2 C1 X X Reset Type Sync sync SLIM SLIL SLIM adds memory features to s, + muxes. 37 Spring 2009 EECS150 - Lec03-FPG Page Virtex-5 SP48E Slice 38 Efficient implementation of multiply, add, bit-wise logical. LX110T has 4 in a single column.

20 Spring 2009 EECS150 - Lec03-FPG Page 39 To be continued... Throughout the semester, we will look at different Virtex-5 features in-depth. Switch fabric lock RM SP48 (LUs) Clocking I/O Serial I/O + PCI!"#$%&'()

EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) Project platform: Xilinx ML

EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) Project platform: Xilinx ML EECS150 - igital esign Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 25, 2010 John Wawrzynek Spring 2011 EECS150 - Lec03-FPGA Page 1 Project platform: Xilinx ML505-110 Spring 2011 EECS150