The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register

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Bruce Gervase Sanders
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1 The Need of Datapath or Register Transfer Logic Number 1 Number 2 Number 3 Number 4 Numbers from 1 to million Register (a) (b) Circuits to add several numbers: (a) combinational circuit to add four numbers; (b) datapath to add many numbers. Designing Dedicated Datapaths Datapath is responsible for performing all of the data operations. it must be able to perform all of the data manipulation statements and conditional tests specified by the algorithm. For Example the datapath can perform an assignment like A = A 3 The Datapath required for performing this operation consists of Adder, Register to store the A variable and buses to enter the constant value 3 and connect the register to the adder and the adder to the register. This is shown in (a) of the following figure. If the assignment is A = B C, then the required datapath is as shown in (b) of the figure shown. ALoad Load D 7-0 -bit Register A Load D 7-0 -bit Register B Load D 7-0 -bit Register C '3' ALoad Load D 7-0 -bit Register A (a) (b)

2 If single datapath is required for performing both assignments, the previous two datapaths will be combined together to form the datapath shown. Load D 7-0 -bit Register B Load -bit Register C D 7-0 Amux 1 0 ALoad Load -bit Register A D 7-0 '3' This datapath uses 2 adders. Another possible implementation for these assignments is by using one adder only as shown in the following figure. ALoad D 7-0 Load -bit Register A Load D 7-0 -bit Register B D 7-0 Load -bit Register C 1 0 '3' Mux 1 0 A Register may store more than one variable in different times. Therefore it may be a destination for more than one source. These sources may be a bus (buses), register or function unit (like adder, shifter...etc). a destination register for two different sources is shown in the following figure.

3 Input 1 0 The destination of the datapath may be one or more registers depending on the assignments under concern. A register file may also be used to simplify the datapath implementation. Special registers like shift registers or counters may also be used for implementing special functions. Selecting the circuit implementing the requested function is another factor affecting the design of the datapath. For example, if addition is required one can use an adder, an adder-subtractor or an ALU. Using one function unit or more depending on the assignment may also affect the datapath complexity. For example the assignments a = b c d = e f Reg can be implemented as shown. These implementations show the different complexities of using one adder or 2 adders for implementing both assignments. Data Transfer Methods A register or function unit can be a destination for multiple sources. The sources may be registers, dedicated buses or output from other functional unit. In this case a multiplexer is used to select one of these sources to be transferred to the destination. If the register or functional unit is a source no extra circuit is required.

4 Tri-State Bus The sources and destinations in datapath can be connected together using tri-state buffers assuming that only one source can output at any one time. If more than one source output at the same time, data conflict will occur and tri-state bus is not suitable. To avoid data conflict tri-state buffers are used to enable or disable the output of each source. In this case one source must be enabled at any one time and all the other sources are disabled. The tri-state bus is simple and bidirectional. An example of tri-state bus is shown in the following figure. This bus contains 3 registers, one ALU and one adder. Control Unit Each datapath should have a control unit to generate the control signals required for operations executed in the datapath. The datapath, however, must supply the results of the conditional tests for the control unit so that the control unit can determine what statement to execute next. Status signals are the results of the conditional tests that the datapath supplies to the control unit. Every conditional test that the algorithm has requires a corresponding status signal. These status signals are usually generated by comparators. For example, to execute the statement IF (A = 0) THEN A status signal is required to give the control unit test result of register A (i.e. the content of A equal 0 or not). To test if register A is equal to zero, one of the circuit shown may be used. Different status signal can be generated from the datapath according to the required test conditions. Any given datapath will have a number of control signals. By asserting or de-asserting these control signals at different times, the datapath can perform different register-transfer operations. All of the control signals for a datapath, when grouped together, are referred to as a control word. Hence, a control word will have one bit for each control signal in the datapath. One register-transfer operation of a datapath, therefore, is determined by the values set in one control word. The datapath operation can be determined simply by specifying the bit string for the control word. Each control word operation will take one clock cycle to perform. By combining multiple control words together in a certain sequence, the datapath will perform the specified operations in the order given. Example: Drive the control word required for executing the statements A = A 3 and A = B C. The datapaths required by these statements were shown previously in different forms. These figures have two control signals named ALoad and the Mux. Two control words is required for each datapath in this case, one for each statement. The required control words are given in the following table. The sequence of these control words is arbitrary and can be changed.

5 Control Word Instruction ALoad Mux 1 A = A A = B C 1 0 Examples of Designing datapaths Three steps are required for designing a datapath. The first is to design the select the components required by the datapath it self like registers, function units and the buses between them. The second is to drive the control word required for performing the datapath operations. The third is to design a control unit to generate the required control words. The following examples demonstrate these steps. Counting 1 to 10 Example 1: Derive the datapath and the control unit for the following counting problem 1 i = 0 2 WHILE (i 10){ 3 i = i 1 4 OUTPUT i 5 } Solution: 1. Design of the requested datapath: The datapath can be deigned using one of the two configurations shown 2. The Control words required for each datapath are given in the following tables respectively: Control Word Instruction iload Clear Out 1 i = i = i OUTPUT i Control Word Instruction Count Clear Out 1 i = i = i OUTPUT i Design of the control unit required drawing the state diagram for the control Unit. Each control word is considered as a state. Additional state may be added if required by the design. The state diagrams for both datapath configurations are similar. It is as shown next.

6 Writing the state table is a part of the design of the control unit. The state table and the corresponding transition table are shown next. Current State Next State Q 1 Q 0 Q 1 Q 0 (i ' (i s0 00 s3 11 s1 01 s1 01 s2 10 s2 10 s2 10 s3 11 s1 01 s3 11 s3 11 s3 11 Current State Next State Q 1 Q 0 Q 1 Q 0 (i ' (i Assuming D-flip flops the D-input of each flip flop can be obtained using K-map as follows: The inputs of the datapath iload, Clear and Out can be obtained by replacing control words by the corresponding states according to the following table and the equations of these inputs are: Q1Q0 iload Clear Out iload = Q1'Q0 Clear = Q1'Q0' Out = Q1Q0' The implementation of the control unit is as shown below:

7 Simple IF-THEN-ELSE Example 2: Construct a 4-bit-wide dedicated datapath for solving the simple IF-THEN-ELSE algorithm shown 1 INPUT A 2 IF (A = 5) THEN 3 B = 4 ELSE 5 B = 13 6 END IF 7 OUTPUT B Solution: 1. Design of the requested datapath: The datapath can be deigned as shown:

8 2. The Control words required for the datapath is given in the following table: Control Word Instruction ALoad Muxsel BLoad Out 1 INPUT A Test A B = B = OUTPUT B The state diagram for the control Unit is as shown below. Each control word is considered as a state. Additional state is required in this design to test the content of register A. The state table and transition table are also given next. The D-inputs of the flip-flops can be obtained from the transition table (excitation table in this case). The control words are replaced by the corresponding state to get the datapaths inputs ALoad, Muxsel, BLoad and Out Current State Next State Q2Q1Q0 Q2 Q1 Q0 (A = 5)' (A = 5) s_input 000 s_extra 001 s_extra 001 s_extra 001 s_notequal 010 s_equal 011 s_notequal 010 s_output 100 s_output 100 s_equal 011 s_output 100 s_output 100 s_output 100 s_output 100 s_output 100 Unused Unused Unused Current State Q2Q1Q0 Next State D2 D1 D0 (A = 5)' (A = 5) D2 = Q2'Q1 Q2Q1'Q0' D1 = Q2'Q1'Q0 D0 = Q2'Q1'Q0' Q2'Q1' (A = 5) Q2Q1Q0 Instruction ALoad Muxsel BLoad Out 000 INPUT A No operation B = B = OUTPUT B No operation No operation No operation ALoad = Q2'Q1'Q0' Muxsel = Q2'Q1Q0' BLoad = Q2'Q1 Out = Q2Q1'Q0' Implementation of the control unit for this example is as shown:

9 This example can be solved easier if the test signal A = 5 is drived from the input bus directly as shown. In this case the state diagram will be as shown next.

10 Complete the design of this datapath in this case. Register Files: If more than one register are required in the datapath, register file is easier to be used. The register file is a group of registers (e.g. 4 registers) sharing the input and output buses. In addition there are address lines to select one register only as input and a write enable (WE) signal to load the input in the selected register during Write Operation. The Register files may have two output ports to be suitable for connection with the ALUs which have 2 inputs. Each output port is selected using an address and enable signal. The address signals for each port select one of the registers to be an output and the enable signal is used to output the content of this register. The block diagram of 4 * register file is shown. This circuit contains 4 registers. These registers can be used as input by selecting one of them using WA1 and WA0 address signal and WE as write enable signal to write inside the selected register. One of these registers can also be used as an output on each port by selecting the address signal corresponding to this port and the enable signal of this port. The circuit has RAA1 and RAA0 address lines to select the register that will output its content on port A and RAE signal to enable the contents of this register on the port. The signals RBA1, RBA0 and RBE are the corresponding signals of port B. To enable 2 output ports to one register the output of this register is controlled as shown next:

11 The logic diagram of the 4 * bits registers file with 1 input port and 2 output ports is shown next Summation of n down to 1 Example 3: Construct an -bit dedicated datapath to generate and add the numbers from n down to 1, where n is an -bit user-input number. 1 sum = 0 2 INPUT n 3 WHILE (n 0){ 4 sum = sum n 5 n = n } 7 OUTPUT sum Solution: 1. Design of the requested datapath: In this example a generalized datapath can be used. This datapath consists of an ALU, shifter and an 4 * register file. The functions performed by the ALU and the shifter are shown in the following tables. ALU2 ALU1 ALU0 Operation Pass through A A AND B A OR B NOT A A B A B A A 1

12 SH1 SH0 Operation 0 0 Pass through 0 1 Shift left and fill with Shift right and fill with Rotate right The generalized datapath is as shown. A comparison circuit is added to detect the condition n 0. the condition is detected asynchronously from the multiplexer output to avoid using additional state. The Control words required for implementing this algorithm are given in the following table. The first word is used to perform the instruction sum = 0 by subtracting register 00 of the register file from itself and storing the result in the same register. This is done in one clock time by selecting the control variables simultaneously as follows: 1. Selecting input 0 of the multiplexer to store the ALU output (IE = 0). 2. Activating WE=1, WA 1,0 = 00 to select register 00 as input and activating RAE = 1, RBE = 1, RAA 1,0 = 00 and RAB 1,0 = 00 to select the same register as ALU inputs. 3. Selecting the ALU function (subtract) by activating ALU 2,1,0 = 101 and no shift by activating SH 1,0 = Disabling the data output by selecting OE = 0. Control IE WE WA1,0 RAE RAA1,0 RBE RBA1,0 ALU2,1,0 SH1,0 OE Instruction Word sum = (subtract) INPUT n sum = sum n (add) n = n (decrement) OUTPUT sum (pass) 00 1 The other Control words required are executed in similar manners using different values of the control variable according to the operations as shown in the previous table. The control words can also be written in RTL notation as shown in the following table to demonstrate what happen internally during execution inside the datapath.

unit of this problem is shown next The state table and the state assignment for this state diagram are as

13 Control Instruction Word RTL Instruction 1 sum = 0 Reg00 Reg00 - Reg00 2 INPUT n Reg01 Data Input 3 sum = sum n Reg00 Reg00 Reg01 4 n = n 1 Reg01 Reg OUTPUT sum Data Output ALU Output The state diagram of the control unit of this problem is shown next The state table and the state assignment for this state diagram are as follows: This circuit needs 3 D-Type flip-flops and the Karnauph map of the D inputs of these flip flops are as shown:

The values of the datapath inputs corresponding to state assignment (which are the outputs of the finite state machines) are given in the following

14 The values of the datapath inputs corresponding to state assignment (which are the outputs of the finite state machines) are given in the following table. The Boolean functions of the datapath inputs are as follows: The implementation of the control circuit required for this problem is as follows:

15 Problems: 1. Derive the truth table for the circuit shown. The truth table should only have columns for the control signal inputs and outputs. The data inputs, D0 to D3, are written in the table entries. 2. Derive the control words using the generalized datapath shown for the following problems. Design the control unit for each case: a. Inputting three -bit unsigned numbers, and then output the largest number, followed by the second largest. b. Inputting ten -bit unsigned numbers, and then output the sum of the numbers. c. Inputting multiple -bit unsigned numbers until a zero is entered, and then output the number of numbers entered. d. Inputting an -bit unsigned number, and then output the number of 1 bits in the number. For example, the number has five 1 bits. e. Solving the Greatest Common Divisor (GCD) algorithm shown WHILE (X Y){ IF (X < Y) THEN Y = Y - X; ELSE

16 X = X - Y; END IF } 3. Design an -bit dedicated datapath for the following algorithm, and write the control words for it. Draw the state diagram for the control unit of this datapath. Use only one adder-subtractor unit for all the addition and subtraction operations. Label clearly all of the control and status signals. w = 0 x = 0 y = 0 INPUT z WHILE (z 0) { w = w 2 IF (z is an odd number) THEN x = x 2 ELSE y = y 1 END IF z = z 1 } 4. Repeat problem 2 for each case using dedicated datapath. 5. Design a dedicated datapath for solving the following algorithm. Use only one adder (i.e., no adder-subtractor and no ALU) for all the arithmetic operations. Include the circuits for generating all of the status signals. The datapath is 4-bits wide. s1 = 0; s2 = 0; FOR(i=0; i 10; i){ INPUT j; IF (j is even) THEN s1; ELSE s2; END IF } OUTPUT s1; OUTPUT s2;

Contents. Chapter 9 Datapaths Page 1 of 28

Contents. Chapter 9 Datapaths Page 1 of 28 Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for