Design, Verification and Emulation of an Island-Based Network Flow Processor

Transcription

1 Design, Verification and Emulation of an Island-Based Network Flow Processor Ron Swartzentruber CDN Live April 5, NETRONOME SYSTEMS, INC.

2 Problem Statements 1) Design a large-scale 200Gbps Network Processor containing over 200 processors with multiple high speed I/O and large amounts of internal memory using APR blocks that can be replaced and interchanged across the floorplan Allow for changes in topology later Common building block floorplan saves on design time 2) Verify this very large design using a full-chip environment that can instantiate a few blocks, several blocks, or all of the blocks Speed of the simulation can be determined by how many blocks are instantiated in the testbench 3) Emulate this SoC design to find potential bottlenecks and guarantee system performance Enable Software applications to run pre-silicon and prove out design 2016 NETRONOME SYSTEMS, INC. 2

3 Building an NFP Island APR Blocks with a Common Footprint External Signal Interconnect with Fixed Pin Locations Fabric Ports Register Interface Interrupts and Events JTAG, Clocks, DFT Re-use I/O Timing constraints 50/50 budget Common Test Logic, complete for DFM Identical Overlay Mesh for Internal Signals and Busses for all Islands NFP Island Interconnect Mesh 2016 NETRONOME SYSTEMS, INC. 3

4 Island Block Topology A P C B A Innovative Heterogeneous Island Architecture Identical Overlay Mesh M C C M APR Blocks Connected by Abutment M C C C M Latency Tolerant Processing Architecture with 8 threads A E C C C B C P A F Blocks can be Easily Interchanged; Replaced and Repeated 2016 NETRONOME SYSTEMS, INC. 4

5 Full Chip Test Environment Verify the SoC using a full-chip test environment that can instantiate a few blocks, several blocks, or all of them Common Verify this very large design using a full-chip environment that can instantiate a few blocks, several blocks, or all of the blocks Speed of the simulation can be determined by how many blocks are instantiated in the test bench Test bench created by combining the I/O s of interest with multiple internal islands Python scripts create Verilog top-level module and test bench comprised of multiple blocks and common interfaces UVCs instantiated based on the I/Os of interest 2016 NETRONOME SYSTEMS, INC. 5

6 Full Chip Verification I/O A P Small, Fast 10/25GbE test bench M C E C C C Larger, 100GbE test bench I/O A B C P A I/O 2016 NETRONOME SYSTEMS, INC. 6

7 Emulation Environment Goal: Run full chip System Verilog simulations at 20x speed Run real Software applications to validate performance and find potential bottlenecks Test many thousands of packets in a fraction of the time as compared to simulation. Goal: 9,000x w/ speed-bridge(s) Create make/run environment that allows any SW engineer to test NFP application code pre-silicon Incorporate Cadence Palladium supported I/Os, Speedbridge, BFMs and Packet Generator Treat DUT as a NIC and connect to a VM via PCIe Speedbridge Software load to NIC via external PCIe interface 2016 NETRONOME SYSTEMS, INC. 7

8 Emulation Overview BFM PCIe I/O Network External Memory Ethernet D D R A M P C M C C C C Host PCIe to Network with External Memory Testing 2016 NETRONOME SYSTEMS, INC. 8

9 NFP x PCIe Gen3 x8 For use on Intelligent Server Adapters Six ports 40GbE (or 24x10GbE) 2x100GbE support Four PCIe Gen3 x8 PCIe Gen3 x 8 PCIe Gen3 x 8 PCIe Gen3 x 8 PCIe Gen3 x 8 Comprehensive features with LNOD 2.1 RX/TX with SR-IOV and stateless offloads Extensive, flexible tunneling support (e.g. VXLAN, GRE) Transparent offload of OVS datapath Stateful flow tracking Stateful Load Balancing Firmware Data Plane (blue) RX & TX Processing RX/TX DMA VXLAN/GRE OVS Flow Tracker Load Balancing Network Interface MAC SerDes Adaptive Memory Controller (DDR3-2133) Internal Memory Unit External Memory Unit Function Accelerators Hash TM Bulk Crypto Queue Atomic 6x32bit DDR3 External DDR3 for deeper flow tables 2x100GbE, 6x 40GbE or 24x10GE 2016 NETRONOME SYSTEMS, INC. 9

10 Reference Patents US Patent Application No. 13/399,433: Staggered Island Structure in an Islandbased Network Flow Processor US Patent Application No. 13/399,888: Island-based Network Flow Processor Integrated Circuit US Patent Application No. 13/399,958: Processing Resource Management in an Island-based Network Flow Processor 2016 NETRONOME SYSTEMS, INC. 10

11 2016 NETRONOME SYSTEMS, INC. Thank You