REVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND.

Transcription

1 December 3-6, 2018 Santa Clara Convention Center CA, USA REVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND NETRONOME SYSTEMS, INC.

2 MASSIVELY PARALLEL RISC-V PROCESSING WITH TRANSACTIONAL MEMORY Steven Zagorianakos VP Silicon Development Netronome NETRONOME SYSTEMS, INC.

3 Introduction Discuss Transaction Memories Walk Through an Example Implementation, Utilizing Transactional Memories and RISC-V Harts Full Chip,, Cluster and Groups of RISC-V Harts RISC-V Feature Set for Summary 2018 NETRONOME SYSTEMS, INC. 3

4 Transactional Many, Many CPU Cores Require Many Cores Efficient Command Dispatch / Fetch / Result / Synchronization (Not interrupt based for example )! WFE Currently Planned as Custom-1 But still running in arbitrary C code of any size... Instruction-Driven Switch Fabric Transactional Hierarchy Closely coupled Threaded processing engines And hardwired transaction types Atomics CRC Crypto 2018 NETRONOME SYSTEMS, INC. 4

5 A Practical Implementation Config SRAM SRAM DRAM Cache DRAM-Backed Network Interface SRAM SRAM Host Interface Expansion Host Host The chip or chiplet is made up of islands, which are connected through the instruction-driven switch fabric Which allows for implementtation from small to large hierarchy provides equal access to all types of memories The config, host interface, and network interface islands allow for feeding data into the system Basic flow of data in a SmartNIC 2018 NETRONOME SYSTEMS, INC. 5

6 Global Bus Config/ Bridge Datapath: Posted Coprocessor and Transactions Bus Remote-Cache Coherency Ops Caching Data/ Instructions, C Structures, etc. Tile Link to Bus Agent Bus Cluster (Many Cores) Tile Link Slice Cache Local Scratch Transactional Ops Cluster (Many Cores) Tile Link Slice Cache Cluster (Many Cores) Tile Link Slice Cache 2018 NETRONOME SYSTEMS, INC. 6

7 Cluster Transactional Ops Caching Data/ Instructions, C Structures, etc. Remote-Cache Coherency Ops Tile Link Datapath: Posted Coprocessor and Transactions Group (~10 Cores) Tile Link Interface Group (~10 Cores) Datapath: Posted Coprocessor and Transactions Bus Bus interface Load Store Manages Binding Load Store Bus interface Bus Group (~10 Cores) Local Prefetch/Write Buffer Group (~10 Cores) 2018 NETRONOME SYSTEMS, INC. 7

8 Group RISC-V Pipeline Group Core Coproc (Multiply +) Signals / Timers Several Cores Per Group Instruction Fetch Data Prefetch/Write Buffer Internal Cmd/ Atomic/ Prefetch/ Write Buffer Local Shared Code, High-Speed Thread-Local Data Structures Transactional Ops Remote-Cache Coherency Ops 2018 NETRONOME SYSTEMS, INC. 8

9 RISC-V Feature Set for Cores are RV32IMC cores with custom-0/1 instructions RV32IMC keeps the performance high with low silicon gate count; support for User, Machine and Debug modes only, but provides some memory protection and both user-level and machine-level interrupts. Custom-0 instructions permit dynamic binding of 48+-bit host address and bulk DDR addresses to 32-bit RISC-V addresses Custom-1 instructions permit transaction memory and signaling operations Cores collected into groups Sharing local memory, which is directly accessed (not cache) Simple address translation permits core-local data and stack without changing code and register initialization values Groups collected into Clusters Transaction initiation and signal handling (for transaction acceptance/completion) are handled also in the island bus interfaces. bus access through a shared memory, and local transactional (atomic pipeline) memory shared within the cluster only. Non-transactional access to the cache slices Clusters collected together RISC-V Debug module shared amongst 40 cores - permits JTAG-based debugging of every core The slices of cache combine as L2 cache Provides windowing to 48-bit PCIe and 40-bit MU address spaces is size and performance optimized 2018 NETRONOME SYSTEMS, INC. 9

10 Summary RISC-V harts are well suited for the processor required for implementing a thousand CPU Smart-NIC. The RISC-V solutions can be tailored to meet the needs for embedded applications with suitable choice of instruction set features, privileged modes and debug methodology. We covered at a high level the organization of memories and RISC-V harts that provides efficient processing with high latency memory transactions We looked at the instruction set customizations that allow this to handle RISC-V hart interaction with the memory systems and other harts 2018 NETRONOME SYSTEMS, INC. 10

11 ODSA Workgroup Implementing open specifications contributed by participating companies, any vendor s silicon die can become a building block that can be utilized in a chiplet-based SoC design Working together to standardize processors, accelerators, and memory and I/O peripherals using optimal process nodes Companies wishing to learn more, participate and become an integral part of the ODSA Workgroup can inquire further at odsa@netronome.com or visit us in booth #407! 2018 NETRONOME SYSTEMS, INC. 11

12 THANK YOU NETRONOME SYSTEMS, INC.