Description. PACKAGE TEMPERATURE RANGE 220ns 300ns PKG. NO. CERDIP -55 o C to +125 o C HM1-6561B/883 HM1-6561/883 F18.

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1 March x 4 CMOS RM Features This Circuit is Processed in ccordance to MI-STD- 883 and is Fully Conformant Under the Provisions of Paragraph ow Power Standby µ Max ow Power Operation m/MHz Max Fast ccess ns Max Data Retention at 2.0V Min TT Compatible Input/Output High Output Drive - 1 TT oad On-Chip ddress Registers Common Data In/Out Description The HM-6561/883 is a 256 x 4 static CMOS RM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility. The HM-6561/883 is a fully static RM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Three-State Output asy Microprocessor Interfacing Ordering Information PCKG TMPRTUR RNG 220ns 300ns PKG. NO. CRDIP -55 o C to +125 o C HM1-6561B/883 HM1-6561/883 F18.3 Pinout HM-6561/883 (CRDIP) TOP VI VCC S DQ DQ DQ1 GND 8 11 DQ S2 PIN S DQ DSCRIPTION ddress Input Chip nable rite nable Chip Select Data In/Out CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or Copyright Intersil Corporation File Number

2 Functional Diagram TCHD DDRSS RGISTR 5 5 GTD RO DCODR G 32 G 8 32 x 32 MTRIX DQ0 Q TCH D GTD COUMN DQ1 Q TCH D DCODR ND DT I / O DQ2 Q TCH D DQ3 Q TCH D 3 3 TCHD DDRSS RGISTR S1 S NOTS: 1. ll lines positive logic-active high. 2. Three-state Buffers: high output active. 3. Data atches: high Q = D and Q latches on falling edge of. 4. ddress atches and Gated Decoders: atch on falling edge of and gate on falling edge of

3 bsolute Maximum Ratings Supply Voltage V Input or Output Voltage GND -0.3V to VCC +0.3V SD Classification Class 1 Thermal Information Thermal Resistance θ J θ JC CRDIP Package o C/ 18 o C/ Maximum Storage Temperature Range o C to +150 o C Maximum Junction Temperature o C Maximum ead Temperature (Soldering 10s) o C Die Characteristics Gate Count Gates CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range V to + Operating Temperature Range o C to +125 o C Input ow Voltage V to +0.8V Input High Voltage VCC - 2.0V to VCC Input Rise and Fall ns Max TB 1. HM-6561/883 DC CTRIC PRFORMNC SPCIFICTIONS Device Guaranteed and 100% Tested PRMTR SYMBO (NOT 1) CONDITIONS GROUP SUBGROUPS TMPRTUR MIN IMITS MX UNITS Output ow Voltage VO VCC = 4.5V, IO = 1.6m Output High Voltage VOH VCC = 4.5V, IOH = -0.4m Input eakage Current II VCC =, VI = GND or VCC Input/Output eakage Current IIOZ VCC =, VIO = GND or VCC Data Retention Supply Current ICCDR VCC = 2.0V, = VCC, IO = 0m, Operating Supply Current ICCOP VCC =, (Note 2), = 1MHz, = GND, VI = VCC or GND Standby Supply Current ICCSB VCC =, IO = 0m, VI = VCC or GND 1, 2, 3-55 o C T +125 o C V 1, 2, 3-55 o C T +125 o C V 1, 2, 3-55 o C T +125 o C µ 1, 2, 3-55 o C T +125 o C µ 1, 2, 3-55 o C T +125 o C - 10 µ 1, 2, 3-55 o C T +125 o C - 4 m 1, 2, 3-55 o C T +125 o C - 10 µ NOTS: 1. ll voltages referenced to device GND. 2. Typical derating 1.5m/MHz increase in ICCOP

4 TB 2. HM-6561/883.C. CTRIC PRFORMNC SPCIFICTIONS Device Guaranteed and 100% Tested IMITS PRMTR SYMBO (NOTS 1, 2) CONDITIONS GROUP SUB- GROUPS TMPRTUR HM-6561B/883 HM-6561/883 MIN MX MIN MX UNITS Chip nable ccess ddress ccess Chip Select Output nable Chip Select Output Disable Chip nable Pulse Negative idth Chip nable Pulse Positive idth ddress Setup (1) TQV VCC = 4.5 and (2) TVQV VCC = 4.5 and, (Note 3) (3) TSQX VCC = 4.5 and (4) TSHQZ VCC = 4.5 and (5) TH VCC = 4.5 and (6) TH VCC = 4.5 and (7) TV VCC = 4.5 and 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns ddress Hold (8) TX VCC = 4.5 and Data Setup (9) TDVH VCC = 4.5 and Data Hold (10) THDX VCC = 4.5 and 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns rite Data Delay Chip Select rite Pulse Setup Chip nable rite Pulse Setup Chip Select rite Pulse Hold Chip nable rite Pulse Hold rite nable Pulse idth Read or rite Cycle (11) TDV VCC = 4.5 and (12) TSH VCC = 4.5 and (13) TH VCC = 4.5 and (14) TSH VCC = 4.5 and (15) TH VCC = 4.5 and (16) TH VCC = 4.5 and (17) T VCC = 4.5 and 9, 10, o C T +125 o C , 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns 9, 10, o C T +125 o C ns NOTS: 1. ll voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IO = 1.6m, IOH = -0.4m, C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pf. 3. TVQV = TQV + TV

5 TB 3. HM-6561/883 CTRIC PRFORMNC SPCIFICTIONS IMITS SYMBO PRMTR CONDITIONS NOT TMPRTUR MIN MX UNITS CI Input Capacitance VCC = Open, f = 1MHz, ll Measurements Referenced to Device Ground CO Output Capacitance VCC = Open, f = 1MHz, ll Measurements Referenced to Device Ground 1 T = +25 o C - 8 pf 1 T = +25 o C - 10 pf NOT: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. TB 4. PPICB SUBGROUPS CONFORMNC GROUPS MTHOD SUBGROUPS Initial Test 100%/ Interim Test 100%/5004 1, 7, 9 PD 100%/ Final Test 100%/5004 2, 3, 8, 8B, 10, 11 Group Samples/5005 1, 2, 3, 7, 8, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 Test oad Circuit DUT (NOT 1) C IOH V IO QUIVNT CIRCUIT NOT: 1. Test head capacitance includes stray and jig capacitance

6 Timing aveforms (7) TV (8) TX (7) TV VID (6) TH (5) TH (17) T (6) TH DQ HIGH PRVIOUS DT HIGH Z (1) TQV (2) TVQV VID DT TCHD HIGH Z S1, S2 (4) TSHQZ (4) TSQX (4) TSHQZ TIM RFRNC FIGUR 1. RD CYC TRUTH TB TIM RFRNC INPUTS OUTPUT S1 DQ FUNCTION -1 H H X X Z Memory Disabled 0 X H V Z Cycle Begins, ddresses are atched 1 H X X Output nabled 2 H X V Output Valid 3 H X V Output atched 4 H H X X Z Device Disabled, Prepare for Next Cycle (Same as -1) 5 X H V Z Cycle nds, Next Cycle Begins (Same as 0) NOT: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. The HM-6561/883 Read Cycle is initiated on the falling edge of. This signal latches the input address word into on-chip registers. Minimum address setup and hold times must be met. fter the required hold time, the address lines may change state without affecting device operation. In order to read the output data, S1 and S2 must be low and must be high. The output data will be valid at access time (TQV). The HM-6561/883 has output data latches that are controlled by. On the rising edge of the present data is latched and remains latched until falls. ither or both S1 or S2 may be used to force the output buffers into a high impedance state

7 Timing aveforms (Continued) (7) TV (8) TX (7) TV VID NXT (6) TH (17) T (5) TH (6) TH (13) TH (15) TH (16) TH (11) TDV (9) TDVH (10) THDX DQ S1, S2 (14) TSH (12) TSH VID DT TIM RFRNC FIGUR 2. RIT CYC TRUTH TB TIM RFRNC INPUTS S1 DQ FUNCTION -1 H H X X X Memory Disabled 0 X X V X Cycle Begins, ddresses are atched 1 X X rite Period Begins 2 X V Data In is ritten 3 X H X X rite is Completed 4 H H X X X Prepare for Next Cycle (Same as -1) 5 X X V X Cycle nds, Next Cycle Begins (Same as 0) NOT: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. The write cycle begins with the falling edge latching the address. The write portion of the cycle is defined by, S1, S2 and all being low simultaneously. The write portion of the cycle is terminated by the first rising edge of any control line,, S1, S2 or. The data setup and data hold times (TDVH and THDX) must be referenced to the terminating signal. For example, if S2 rises first, data setup and hold times become TDVS2H and TS2HDX; and are numerically equal to TDVH and THDX. Data input/output multiplexing is controlled by. Care must be taken to avoid data bus conflicts, where the RM outputs become enabled when another device is driving the data inputs. The following two examples illustrate the timing required to avoid bus conflicts. Case 1: Both S1 and S2 Fall Before Falls. If both selects fall before falls, the RM outputs will become enabled. is used to disable the outputs, so a disable time (TQZ = TDV) must pass before any other device can begin to drive the data inputs. This method of operation requires a wider write pulse, because TDV + TDVH is greater than TH. In this case TS + TSHH are meaningless and can be ignored. Case 2: Falls Before Both S1 and S2 Fall. If one or both selects are high until falls, the outputs are guaranteed not to enable at the beginning of the cycle. This eliminates the concern for data bus conflicts and simplifies data input timing. Data input may be applied as early as convenient, and TDV is ignored. Since is not used to disable the outputs it can be shorter than in Case 1; TH 6-123

8 is the minimum write pulse. t the end of the write period, if rises before either select the outputs will enable reading data just written. They will not disable until either select goes high (TSHQZ). CS 1 Both S1 and S2 = ow Before = ow IF OBSRV IGNOR TQZ TDV TDVH TH If a series of consecutive write cycles are to be performed, may remain low until all desired locations are written. This is an extension of Case 2. Read-Modify-rite cycles and Read-rite-Read cycles can be performed (extension of Case 1). In fact data may be modified as many times as desired with remaining low. CS 2 = ow Before Both S1 and S2 = ow TH TDVH TQZ TDV Burn-In Circuit HM-6561/883 CRDIP VCC C1 F6 1 3 VCC 18 F F7 F F1 F3 4 0 S1 15 F0 F8 5 5 DQ3 14 F2 F9 6 6 DQ2 13 F2 F DQ1 12 F2 8 GND DQ0 11 F2 F0 9 S2 10 F0 NOTS: ll resistors 47kΩ ±5%. F0 = 100kHz ±10%. F1 = F0 2, F2 = F1 2, F3 = F F12 = F11 2. VCC = ±0.5V. VIH = 4.5V ±10%. VI = -0.2V to +0.4V. C1 = 0.01µF Min

Die Characteristics DI DIMNSIONS: 132 x 160 x 19 ±1mils MTIZTION: Type: Si - l Thickness: 11kÅ ±2kÅ GSSIVTION: Type: SiO 2 Thickness: 8kÅ ±1kÅ ORST CS CURRNT DNSITY: 1.

9 Die Characteristics DI DIMNSIONS: 132 x 160 x 19 ±1mils MTIZTION: Type: Si - l Thickness: 11kÅ ±2kÅ GSSIVTION: Type: SiO 2 Thickness: 8kÅ ±1kÅ ORST CS CURRNT DNSITY: x 10 5 /cm 2 D TMPRTUR (10s soldering): 300 o C Metallization Mask ayout HM-6561/883 S1 DQ3 DQ2 DQ1 DQ0 S2 4 VCC GND ll Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site

DATASHEET HM-6617/883. Features. Description. Ordering Information. Pinout. 2K x 8 CMOS PROM. FN3016 Rev.3.00 Page 1 of 7. June FN3016 Rev.3.

DATASHEET HM-6617/883. Features. Description. Ordering Information. Pinout. 2K x 8 CMOS PROM. FN3016 Rev.3.00 Page 1 of 7. June FN3016 Rev.3. DTSHT 2K x 8 CMOS PROM Features This Circuit is Processed in ccordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Low Power Standby and Operating Power - ICCSB.................................