DATASHEET HM-6617/883. Features. Description. Ordering Information. Pinout. 2K x 8 CMOS PROM. FN3016 Rev.3.00 Page 1 of 7. June FN3016 Rev.3.
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1 DTSHT 2K x 8 CMOS PROM Features This Circuit is Processed in ccordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph Low Power Standby and Operating Power - ICCSB ICCOP m at 1MHz Fast ccess Time ns Industry Standard Pinout Single 5.0V Supply CMOS/TTL Compatible Inputs High Output Drive LSTTL Loads Synchronous Operation On-Chip ddress Latches Separate Output nable Operating Temperature Range o C to +125 o C Ordering Information Description FN3016 Rev.3.00 The is a 16,384-bit fuse link CMOS PROM in a 2K word by 8-bit/word format with Three-State outputs. The utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS PROMs. ll bits are manufactured storing a logical 0 and can be PCK TMPRTUR RN 120ns PCK NO. SBDIP -55 o C to +125 o C HM1-6617/883 D24.6 Pinout (SBDIP) TOP VIW PIN DSCRIPTION Q0 9 Q1 10 Q2 11 ND V CC 8 9 P 10 Q6 Q5 Q4 Q3 NC PIN 0-10 Q V CC P (Note) DSCRIPTION No Connect ddress Inputs Chip nable Data Output Power (+5V) Output nable Program nable NOT: P should be hardwired to V CC except during programming. FN3016 Rev.3.00 Page 1 of 7
2 Functional Diagram MSB LSB LTCHD DDRSS RISTR L 7 7 TD ROW DCODR x 128 MTRIX Q0 Q1 Q2 Q3 TD COLUMN DCODR ND DT OUTPUT CONTROL 8 Q4 4 4 Q5 LL LINS POSITIV LOIC: THR-STT BUFFRS: HIH CTIV HIH OUTPUT CTIV L MSB LTCHD DDRSS RISTR LSB Q6 DDRSS LTCHS ND TD DCODRS: LTCH ON FLLIN D OF T ON FLLIN D OF FN3016 Rev.3.00 Page 2 of 7
3 bsolute Maximum Ratings Supply Voltage V Input, Output or I/O Voltage ND -0.3V to VCC +0.3V Typical Derating Factor m/MHz Increase in ICCOP SD Classification Class 1 Operating Conditions Operating Voltage Range V to +5.5V Operating Temperature Range o C to +125 o C Input Low Voltage V to +0.8V Input High Voltage V to VCC +0.3V Thermal Information Thermal Resistance J JC SBDIP Package o C/W 9 o C/W Maximum Storage Temperature Range o C to +150 o C Maximum Junction Temperature o C Maximum Lead Temperature (Soldering 10s) o C Die Characteristics ate Count ates CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TBL 1. DC LCTRICL PRFORMNC SPCIFICTIONS Device uaranteed and 100% Tested PRMTR (NOTS 1, 4) CONDITIONS ROUP SUBROUPS TMPRTUR MX High Level Output Voltage VOH1 VCC = 4.5V, IO = -2.0m 1, 2, 3-55 o C T +125 o C V Low Level Output Voltage VOL VCC = 4.5V, IO = +4.8m 1, 2, 3-55 o C T +125 o C V High Impedance Output Leakage Current IIOZ VCC = 5.5V, = 5.5V, VI/O = ND or VCC 1, 2, 3-55 o C T +125 o C Input Leakage Current II VCC = 5.5V, VI = ND or VCC, P Not Tested Standby Supply Current ICCSB VI = VCC or ND, VCC = 5.5V, IO = 0m Operating Supply Current ICCOP VCC = 5.5V, = ND, (Note 3), f = 1MHz, IO = 0m, VI = VCC or ND 1, 2, 3-55 o C T +125 o C , 2, 3-55 o C T +125 o C , 2, 3-55 o C T +125 o C - 20 m Functional Test FT VCC = 4.5V (Note 6) 7, 8, 8B -55 o C T +125 o C - - TBL 2. C LCTRICL PRFORMNC SPCIFICTIONS Device uaranteed and 100% Tested PRMTR (NOTS 1, 2, 4) CONDITIONS ROUP SUBROUPS TMPRTUR MX ddress ccess Time TVQV VCC = 4.5V and 5.5V (Note 5) 9, 10, o C T +125 o C ns Output nable ccess Time Chip nable ccess Time TLQV VCC = 4.5V and 5.5V 9, 10, o C T +125 o C - 50 ns TLQV VCC = 4.5V and 5.5V 9, 10, o C T +125 o C ns ddress Setup Time TVL VCC = 4.5V and 5.5V 9, 10, o C T +125 o C 20 - ns ddress Hold Time TLX VCC = 4.5V and 5.5V 9, 10, o C T +125 o C 25 - ns Chip nable Low Width TLH VCC = 4.5V and 5.5V 9, 10, o C T +125 o C ns Chip nable High Width THL VCC = 4.5V and 5.5V 9, 10, o C T +125 o C 40 - ns FN3016 Rev.3.00 Page 3 of 7
4 TBL 2. C LCTRICL PRFORMNC SPCIFICTIONS (Continued) Device uaranteed and 100% Tested PRMTR (NOTS 1, 2, 4) CONDITIONS ROUP SUBROUPS TMPRTUR MX Read Cycle Time TLL VCC = 4.5V and 5.5V 9, 10, o C T +125 o C ns NOTS: 1. ll voltages referenced to Device ND. 2. C measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = ; output load = 1TTL equivalent load and CL 50pF. 3. Typical derating = 5m/MHz increase in ICCOP. 4. ll tests performed with P hardwired to VCC. 5. TVQV = TLQV + TVL. 6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1m, IOL = +1m, VOH, VOL. TBL 3. C ND DC LCTRICL PRFORMNC SPCIFICTIONS PRMTR (NOTS 1, 2) CONDITIONS NOTS TMPRTUR MX Input Capacitance CIN VCC = Open, f = 1MHz, ll Measurements Referenced to Device ND I/O Capacitance CI/O VCC = Open, f = 1MHz, ll Measurements Referenced to Device ND o C - 10 pf o C - 12 pf Chip nable Time TLQX VCC = 4.5V and 5.5V 2-55 o C T +125 o C 5 - ns Output nable Time TLQX VCC = 4.5V and 5.5V 2-55 o C T +125 o C 5 - ns Chip Disable Time THQZ VCC = 4.5V and 5.5V 2-55 o C T +125 o C - 50 ns Output Disable Time THQZ VCC = 4.5V and 5.5V 2-55 o C T +125 o C - 50 ns Output High Voltage VOH2 VCC = 4.5V, IO = o C T +125 o C VCC- 1V - V NOTS: 1. ll tests performed with P hardwired to VCC. 2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design changes which would affect these characteristics. TBL 4. PPLICBL SUBROUPS CONFORMNC ROUPS MTHOD SUBROUPS Initial Test 100%/ Interim Test 100%/5004 1, 7, 9 PD 100%/ Final Test 100%/5004 2, 3, 8, 8B, 10, 11 roup Samples/5005 1, 2, 3, 7, 8, 8B, 9, 10, 11 roups C & D Samples/5005 1, 7, 9 FN3016 Rev.3.00 Page 4 of 7
5 Switching Waveforms TVQV DDRSSS THL VLID DDRSS TVL TLX TLQV TLH TLL VLID DDRSSS THQZ 3.0V 0V 3.0V 0V DT OUTPUT Q0- TLQX TLQX TLQV VLID DT THQZ 3.0V 0V T S FIUR 1. RD CYCL Test Circuit DUT C L (NOT) I OH I OL NOT: TST HD CPCITNC QUIVLNT CIRCUIT FIUR 2. TST CIRCUIT FN3016 Rev.3.00 Page 5 of 7
6 Burn-In Circuit NOTS: (.600 INCH) SBDIP VCC C f8 1 7 VCC 24 f f11 f f12 f5 4 4 P 21 VCC f f1 f f13 f2 f f0 9 Q0 Q6 16 VCC/2 10 Q1 Q5 15 VCC/2 11 Q2 Q ND Q3 13 ND f0 = 100KHz 10%. ll resistors = 47k Unless Otherwise Noted. VCC = 5.5V 0.05V. C = 0.01 F min. Copyright Intersil mericas LLC ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3016 Rev.3.00 Page 6 of 7
7 Die Characteristics DI DIMNSIONS: 140 x 232 x 19 1mils MTLLIZTION: Type: Si - l Thickness: 11kÅ 15kÅ LSSIVTION: Type: SiO 2 Thickness: 7kÅ 9kÅ WORST CS CURRNT DNSITY: 1.7 x 10 5 /cm 2 Metallization Mask Layout VCC 8 9 P Q0 Q1 Q2 ND Q3 Q4 Q5 Q6 FN3016 Rev.3.00 Page 7 of 7
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ISSI IS25C02 IS25C04 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM FEATURES DESCRIPTION. Advanced Information January 2005
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2005 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low power CMOS Active current less than 3.0
AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb
REVISION HISTORY Revision Description Issue Date 1.0 Initial issue Feb 2007 2.0 Add-in industrial temperature option for 28-pin 600 July 2017 mil PDIP. Standby current(isb1) reduced to be 20uA for I-grade
SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input
1-Mbit (64K x 16) Static RAM
1-Mbit (64K x 16) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C High speed t AA = 12 ns (Commercial & Industrial) t AA = 15 ns (Automotive)
2.5 V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch ADG3247
V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps V/3.3 V Supply Operation Selectable Level
EDI8G322048C DESCRIPTION FEATURES PIN CONFIGURATION PIN NAMES
2048K x 32 Static RM CMOS, High Speed Module FETURES n 2048K x 32 bit CMOS Static n Random ccess Memory ccess Times: 20, 25, and 35ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O
IDT54/74FCT244/A/C FAST CMOS OCTAL BUFFER/LINE DRIVER DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM FEATURES: OEA OEB DA1 OA1 DB1 OB1 DA2 OA2 OB2 DB2 DA3 OA3
FAST CMOS OCTAL BUFFER/LINE DRIVER IDT/7FCT/A/C FEATURES: IDT/7FCTA equivalent to FAST speed and drive IDT/7FCTA % faster than FAST IDT/7FCTC up to % faster than FAST IOL = ma (commercial) and 8mA (military)
TM124MBK36C, TM124MBK36S BY 36-BIT TM248NBK36C, TM248NBK36S BY 36-BIT DYNAMIC RAM MODULE
Organization TM124MBK36C...48576 36 TM248NBK36C...2097152 36 Single 5-V Power Supply (±% Tolerance) 72-pin Leadless Single In-Line Memory Module (SIMM) TM124MBK36C Utilizes Eight 4-Megabit DRAMs in Plastic
ISSI Preliminary Information January 2006
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2006 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low-voltage Operation Vcc = 1.8V to 5.5V Low
SED1180F CMOS LCD 64-COMMON DRIVERS LCD CONTR 256SEG 64 COM DUTY: 1/64
CMOS LCD -COMMON DRIVERS DESCRIPTION The SED119 is a dot matrix LCD common (row) driver for driving high-capacity LCD panel at duty cycles higher than 1/. The LSI uses two serially connected, 32-bit shift
CS SK DI TEST DO 4 5 GND. Figure 1. Table 1
Rev.1.1 CMOS SERIAL E 2 PROM Features ø Low power consumption Standby : µa Max. Operating : 1.2 ma Max. (VCC=5.5 V) : ma Max. (VCC=2.5 V) ø Wide operating voltage range Write : 1.8 to 5.5 V Read : 1.8
CAT22C Bit Nonvolatile CMOS Static RAM
256-Bit Nonvolatile CMOS Static RAM FEATURES Single 5V Supply Fast RAM Access Times: 200ns 300ns Infinite E 2 PROM to RAM Recall CMOS and TTL Compatible I/O Power Up/Down Protection 100,000 Program/Erase
93C76/86. 8K/16K 5.0V Microwire Serial EEPROM FEATURES DESCRIPTION PACKAGE TYPES BLOCK DIAGRAM
8K/16K 5.0V Microwire Serial EEPROM FEATURES PACKAGE TYPES Single 5.0V supply Low power CMOS technology - 1 ma active current typical ORG pin selectable memory configuration 1024 x 8- or 512 x 16-bit organization
SN54ALS20A, SN54AS20, SN74ALS20A, SN74AS20 DUAL 4-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These devices contain two independent -input positive-nand
16Mbit, 512KX32 CMOS S-RAM MODULE
16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 25, 35 and 45ns Package Options: 66-Pin Ceramic PGA 1.385" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFP
Craft Port Tiny RS-232 Transceiver for Portable Applications ADM101E. Data Sheet FUNCTIONAL BLOCK DIAGRAM
Data Sheet FEATURES 460 kbit/s Transmission Rate Single 5 V Power Supply Compatible with RS-232 Input/Output Levels 0.1 μf Charge Pump Capacitors One Driver and One Receiver On-Board DC-DC Converter ±4.2
M28C16. 16K (2K x 8) PARALLEL EEPROM with SOFTWARE DATA PROTECTION
16K (2K x 8) PARALLL PROM with SOFTAR DATA PROTCTION FAST ACCSS TIM: 90ns SINL 5V ± 10% SUPPLY VOLTA LO POR CONSUMPTION FAST RIT CYCL: 64 Bytes Page rite Operation Byte or Page rite Cycle: 3ms Max NHANCD
SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout True Logic Outputs Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N)
MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION
![MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION](/thumbs/78/78720826.jpg "MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION")
FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM
OPTIONS. Low Power Data Retention Mode. PIN ASSIGNMENT (Top View) I/O 16 I/O 17 I/O 18 I/O 19 I/O17 I/O18 I/O19. Vss I/O20 I/O21 I/O22 I/O23
512K x 32 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-94611 & 5962-95624 (Military Pinout) MIL-STD-883 FEATURES Operation with single 5V supply Vastly improved Icc Specs High speed:
3.3 Volt CMOS Bus Interface 8-Bit Latches
Q 3.3 Volt CMOS Bus Interface 8-Bit Latches QS74FCT3373 QS74FCT32373 FEATURES/BENEFITS Pin and function compatible to the 74F373 JEDEC spec compatible 74LVT373 and 74FCT373T IOL = 24 ma Com. Available
AS6C K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access
3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVER
. CMOS OCTAL IDIRECTIONAL TRANSCEIVER. CMOS OCTAL IDIRECTIONAL TRANSCEIVER IDT7FCT/A FEATURES: 0. MICRON CMOS Technology ESD > 00 per MIL-STD-, Method 0; > 0 using machine model (C = 00pF, R = 0) VCC =.
LY68L M Bits Serial Pseudo-SRAM with SPI and QPI
REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0 FEATURES GENERAL
2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
512KX8 CMOS S-RAM (Monolithic)
512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic
MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS05-13103-5E Memory FRAM CMOS 1 M Bit (128 K 8) MB85R1001 DESCRIPTIONS The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072 words x
IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit)
CMOS Static RAM 1 Meg (4K x 1-Bit) IDT711S/NS Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial and Industrial: //2 One Chip Select plus one Output Enable pin
IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD
3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 T TOLERANT I/O AND BUS-HOLD FEATURES: Typical tsk(0) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs
16Mbit, 512KX32 CMOS S-RAM MODULE
16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 17 and 20ns Package Options: 66-Pin Ceramic PGA 1.080" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFJ
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242 FEATURES 225 ps propagation delay through the switch 4.5 Ω switch connection between ports Data rate 1.5 Gbps 2.5 V/3.3 V supply operation
2.5 V/3.3 V, 8-Bit, 2-Port Level Translating, Bus Switch ADG3245
V/3.3 V, 8-Bit, 2-Port Level Translating, Bus Switch ADG3245 FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps V/3.3 V Supply Operation Selectable
S-2900A. Rev.1.1. CMOS 512-bit SERIAL E 2 PROM
Rev.1.1 CMOS 512-bit SERIAL E 2 PROM S-29A The S-29A is a wide operating voltage range, low power consumption 512-bit E 2 PROM. The organization is 64-word 8-bit, and can be read or written serially. It
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CAT28C17A 16K-Bit CMOS PARALLEL EEPROM
16K-Bit CMOS PARALLEL EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast Read Access Times: 200 ns Low Power CMOS Dissipation: Active: 25 ma Max. Standby: 100 µa Max. Simple Write Operation: On-Chip Address
CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout
CMOS Static RAM 1 Meg (K x -Bit) Revolutionary Pinout IDT714 Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access and cycle times
8M x 64 Bit PC-100 SDRAM DIMM
PC-100 SYNCHRONOUS DRAM DIMM 64814ESEM4G09TWF 168 Pin 8Mx64 (Formerly 64814ESEM4G09T) Unbuffered, 4k Refresh, 3.3V with SPD Pin Assignment General Description The module is a 8Mx64 bit, 9 chip, 168 Pin
VCC NC PROTECT DI DO. Table 1
Rev.1.11 CMOS SERIAL E 2 PROM Features Low power consumption Standby :0.8 µa Max. (V CC =5.5 V) Operating :0.8 ma Max. (V CC =5.5 V) 0.4 ma Max. (V CC =2.7 V) Low operating voltage range Write : 1.8 to