Fixed-Length Switching vs. Variable-Length Switching in Input-Queued IP Switches

Transcription

1 Fixed-Length Switching vs. Variable-Length Switching in Input-Queued IP Switches Chengchen Hu, Xuefei Chen, Wenjie Li, Bin Liu Department of Computer Science and Technology Tsinghua University Beijing, P. R. China {hucc03, chenxf03, Abstract Many large-scale, high speed routers adopt inputqueued switches with virtual output queuing (VOQ) for preventing head of line (HOL) blocking. Switching based on cellby-cell scheduling algorithms () have been widely studied for years, while a new idea of transferring IP packet based on a packet-by-packet scheduling algorithm () has been proposed recently. These two switching modes differ largely in performance and implementation complexity. This paper establishes experiments at the aim of evaluating one design issue: whether it should be or. We investigate various performance measures of interest: bandwidth utilization, packet loss, segmentation and reassembling overhead, as well as average packet latency. The focus of the paper is on identifying key parameters that influence the outcome of this comparison, and on quantifying the potential benefits of each switching mode. Keywords- input queued switch,, I. INTRODUCTION Rapid deployment of the Internet technology in recent years was primarily driven by the need for higher speed and better quality of service. This brings many challenges and opportunities to the research on switches and routers in backbones. Since exiting the output conflicts that many inputs may compete for the same output, switches internally need buffer packets. Output Queuing (OQ) need speedup of N for an N N switch, while naive Input Queuing (IQ) suffers from Head of Line (HOL) blocking which limits the throughput to 2-2= , when N [1]. However, IQ achieves 100% throughput without any speedup by the means of Virtual Output Queue (VOQ). Consequently, Input queued switch combined with VOQ is widely adopted as the structure of high speed switches and routers [2, 3]. This paper will focus on input-queued switches. Assume an N N switch with each input and output interface operating at the same rate. Further, assume that the time is slotted, and at most one cell can arrive at each input port at each time slot. Figure 1 illustrates the structure of an input-queued switch. The switch fabric operates on fixedlength data units that we call a cell. After being segmented into cells, packets at input i and to output j are buffered in the corresponding VOQ denoted by VOQ ij. Cross points are configured according to results of the scheduling algorithm at the end of each time slot. A major issue on the design of input-queued switch is that the access to the switch fabric must be controlled by some form of scheduling algorithm to avoid contention at inputs and outputs [4-6]. The time interval between two consecutive scheduling decisions is called a slot, and the slot is the granularity in the allocation of switch resources. Output contention can be described as: at any time slot, there may be more than one input that has cell/packet destined for the same output, but the output can send grant information to only one input. On the other hand, one input may receive several grant information but only one VOQ can send data to switch fabric. It is called input competition. According to traditional implementation methodology, an incoming IP packet is segmented into fixed length units when it enters a switch, whereas it is transmitted in Internet with variable length. Then the segmented cells pass through the switch fabric based on a cell-by-cell scheduling algorithm. Throughout this paper, we use or cell switching to denote this switching mode. Intuitively, has two main disadvantages: (1) It requires complex SAR operation in a variable-length IP router, which not only increases the complexity of hardware implementation, but also limits the line rate of router interfaces. (2) Packets may generate an incomplete cells because a cell should be fixed length and should not contain data belonging to two different packets. Some control data is also added to each cell. These will result in significant bandwidth loss. Vitesse Corp. provided a switch solution which does not require SAR operation and the scheduling decision based on the granularity of variable-length IP packets [8, 9]. Since each packet has a different arrival time and a different packet length, the scheduler has to monitor the packet arrival and departure time and updata cross-point configuration at each packet arrival and departure time in continuous time domain. Therefore, it cause high complexity and is especially hard for high speed Giga- or Tera-bit switches to make scheduling decisions as fast as the speed of incoming packets. An alternative idea of segmenting packet and transferring cells of the same packet like a train without being interleaved with cells of other packets was first proposed in [10]. This type of switching refers to or packet switching in this paper. Specifically, a segment module segments the IP packet into logical cells adopting for the updating interval. A variable-

2 length packet scheduler periodically updates the cross-point configuration at every predetermined time interval (slot) as the cell scheduling system. The cells of an IP packet pass through the switch fabric by maintaining the cross-point connection. Note that the transmission of the whole packet should not be interrupted. Let s refer to figure 1. When is adopted, the scheduler checks all HOL cells in VOQ at the beginning of the slot and finds optimal input-output matching pairs. All inputs have some possibility to change their matched outputs at next time slot. Cells belonging to different packets may be interleaved at the same output, therefore, reassemble module is needed. When is adopted, there are many inputs which are dedicated to packet connections and these inputs certainly maintain their matched outputs as long as their current states continue. Note that, cells belonging to the same packet are kept contiguous in the input queue and output queue. Thus, reassemble module can be removed in this case. Fixed-length and can be significantly different in performance and implementation complexity. The subject of vs. variablelength switching has become an important design and architecture issue. Some prior works analyzed the stability and throughput of [6] and variable-length switching [11, 12] respectively. A comprehensive comparison of two approaches is necessary and significative to guide both the academic research and industrial implementation. There are three variables that the user is concerned about most: user effective bandwidth, packet loss rate and average packet latency. In this paper, we take account of several elements of both and variable-length switching to give a comparison, such as bandwidth, loss rate, SAR overhead and packet latency. The work is carried out by means of simulation experiments, which allow us to make a comprehensive comparison. The objective of this study is to provide some insight into the factors that influence the outcome of the comparison. The structure of this paper is as follows. Some related work on the stability of both and variablelength switching is shown in section 2. A comparison of bandwidth utilization is made in section 3. Section 4 presents the loss performance comparison. Section 5 discusses the overhead of SAR operation. Further, some experiments are carried out by the means of simulations in section 6. Finally, section 7 concludes the paper. II. RELATED WORK Some previous works analyzed the stability of cell-by-cell scheduling algorithm and packet-by-packet scheduling algorithm respectively. Let A ij (n) and D ij (n) be the cumulative number of cells that arrive at and departure from VOQ ij respectively. We adopt the convention that A ij ( n) = 0 and say that the arrival process A( n) = { Aij ( n)} satisfies the strong law of large numbers (SLLN), if equation (1) is always true. Input 1 Segment Input N Aij ( n) lim n n = λ i, j = 1,2, L, N (1) ij Stability of cell-by-cell scheduling algorithm adopted by is discussed in [4, 6]. It was shown in [4] that under any admissible 1 Bernoulli i.i.d. traffic, MWM (Maximum Weight Matching) algorithm is stable and delivers 100% throughput. In [6] using the fluid model analysis it was proved that any Maximum Weight Match algorithm under a speedup of one and any Maximal Weight Match algorithm under a speedup of two are stable for any admissible traffic that satisfies SLLN. The notion of stability in [6] (rate stability, ( ij) n D with probability one, lim n = λij ) is weaker than the n notion of stability used in [4], but in [6] the stability is proved for a larger class of arrival traffic. Stability of packet-by-packet scheduling algorithm adopted by is discussed in [10-12]. In [10, 11], it was shown that canonical modification of the cell by cell MWM scheduling algorithm for packet-by-packet scheduling, achieves 100% throughput for any admissible Bernoulli i.i.d. traffic with packet lengths being bounded. Paper [12] established the fluid model to extend the result of [10] to general regenerative 2 traffic pattern instead of just admissible arrival traffic pattern. Further, a new class of waiting algorithm was proposed in [12], which is stable for any admissible traffic using fluid limit technique. III. UTILIZATION OF AVAILABLE BANDWIDTH In order to buffer packets being blocked by switch fabric, large amount memory DRAMs should be used in high speed switches or routers. The gap of speed between DRAMs speed (improving 7%-9% per year), even RLDRAM (Reduce latency DRAM) and internet link speed (improving 100% per year) is only increasing [18]. The switch fabric speed is facing the similar problem. In other words, external memory and switch fabric are two major bottlenecks existing in the data path of 1 Let λ ij be the arrival rate at VOQ ij. The arrival process is admissible if no input and output is overloaded, i.e., λ 1, λ 1. j ij Segment λ11 u11 λ1n λ N1 λ NN u 1 N u N1 u NN V V V Switch Fabric Figure 1. Input-queued switch architecture Reassemble Output 1 Reassemble Output N 2 Let t be the time between two successive occurrences of the event that all ports are free. If E(t) is finite we say that the traffic pattern is regenerative. In other words, it has property that on average it requires a finite amount of time to reach the state where all the input and output ports are free. V i ij

3 switches and routers. On the other hand, the available bandwidth refers to the number and bandwidth of connections which can be made in the network. The higher the available bandwidth is, the more money the ISPs can make, and in an indirect way, this is of interesting to the end user because it may affect his ability to make a connection. Therefore, how to utilize bandwidth more efficiently becomes an important design issue. Two principle sources result in bandwidth loss. First, scheduler making its decision depends on the certain information of packet or cell, such as destination port, sequence number and etc.. So it brings bandwidth loss due to inserting some control data into cells when segmenting. Control data needs to be added to each cell of the packet when adopting, while it only needs to be added to the first cell of the packet when adopting. On the other hand, it also brings bandwidth loss due to the need of segmentation. Packets may generate incomplete cells (last cell), because a cell should be fixed length and should not contain data belonging to two different packets. To give a numerical analysis, we assume that the cell size is 64 bytes and additional control data is 8 bytes. Thus the bandwidth losses of a packet with length of x adopting fixedlength switching and are as follows 3 : x BL packet ( x) = (1 ) 100% (2) x x BL packet ( x) = (1 ) 100% (3) x Figure 2 illustrates the curves comparing the bandwidth loss of versus as a function of length of the packet being switched. It is found that wastes more bandwidth than. The minimum bandwidth loss for is 56/64=12.5%. The bandwidth loss for at its stationary point is 8/(x+8) ( x 56 ), so the longer the packet is, the more superior the is. Assume the packet length x < 1024, then the minimum loss is 0.78%. Certainly, the overall bandwidth loss should be the expected value and depends upon the probability density function for the length of packets. Variable-length switching has a better performance from the viewpoint of bandwidth loss. IV. PACKET LOSS Packet loss is relevant to three major sources [13]: Losses due to transmission errors. The white noise of the transmission lines or switch fabric may introduce packet loss. Bandwith loss rate / slot Packet length Figure 2. Bandwidth loss vs. packet length Losses due to buffer overflows. Packet is dropped depends on some queue management strategy such as RED and Tail Drop, because the queue length is not long enough to buffer all incoming packets, especially the burst packets. Losses due to excessive delay. Some real-time application such as multimedia traffic requires strict delay, and the packet with excessive delay is considered as being lost. Losses due to transmission errors are well controlled by modern technologies, e.g., optical fiber network. Adopting or has no effect on such losses. To the second source, losses can be controlled by selecting an appropriate queue length. Note that, longer queues will reduce such losses. Figure 3 illustrates the effect of traffic load on the queue overflow probability as a function of the queue length. The packet lengths are uniformly distributed between 40 Bytes and 1500 Bytes and the simulation environment will be presented in detail in section 6. We assume that entire packet is discarded if the input queue does not have enough free space to buffer the incoming packet. The figure demonstrates that may suffer more loss if the queue length is the same as the fixedlength switching. On the other hand, long packet will block the output port when it is being transferred. It increases the delay of short packet when adopting which is proved by the experiment in section 6. Unfortunately, some delay-sensitive traffic has short packets, such as VoIP (Voice over IP) traffic 4. So may increase more loss due to the third source. V. SAR OVERHEAD As mentioned above, packets arriving at input side need to be segmented into cells, requiring a special input segmentation module. Switch fabric transfers cells from input to output and these cells are delivered to the reassembling module where packets are reassembled when is 3 denotes a Ceiling operator. 4 The packet size of VoIP is 50-bytes for real-time transport protocol (RTP) and much less bytes for compressed RTP (crtp).

4 probability of overview 10 0 load = probability of overview 10 0 load = probability of overview 10 0 load = probability of overview 10 0 load = Figure 3. Packet loss vs. queue length adopted. There are no differences between two switching modes on segmentation. However, introduces significant implementation overhead and additional delay at reassembling module. In the case of, cells belonging to different packets can be interleaved at the same output. Therefore, more than one reassembling queues can be active at each output. At most N reassembling queues per output are used if the packets have only one priority. Further, if the switch or router is designed to support multi-priorities traffic (suppose M priorities), then the number of reassembling queues at each output should be M N. With the increase of M and N, it significantly increases the implementation overhead and queue management complexity. It is infeasible to support per-flow queuing with naive. On the contrary, when is adopted, it is possible to further simplify the switch structure. Indeed, cells belonging to the same packet are contiguous in the input queue of the switch, and cells belonging to the same packet are kept contiguous also in the output queue. As a matter of fact, the reassembling modules are no longer necessary. It makes per-flow queuing possible. Further, reassembling module has effect on packet latency. In the case of, cells should wait in the reassembling module for its subsequent cells to reassemble a complete packet and then sent the whole packet to the next node, while cells can be sent to next node without waiting when is adopted. If the packet latency is defined as the time difference between an instant when the head of an IP packet enters the switch module and an instant when the tail of the IP packet passes through the switch module. Therefore, at the viewpoint of packet latency, each packet obtains an additional delay of a packet transferring time out of the reassembling queue when is adopted. Experiments in section 6 will show the effect. VI. SIMULATION RESULT To evaluated the effect of the factors described in the previous section and the packet latency measures, it need to be complemented with simulations or experiments to validate the hypothesis made during the analysis and to explore phenomena not amenable to tractable analysis. Figure 4 shows a high level overview of the components of the simulator. Packet generator creates variable length packets. We consider three packet length distributions: uniform distribution, bimodal distribution and trimodal distribution, which will be explained later in this section. Segmentation component segments packet into cells, and then send to queuing and scheduling component which Packet Generator Segmentati on Figure 4. Queuing&scheduling (Variable- length) Queuing&scheduling (fixed- length) reassembling Components of the simulator statistics

5 without Reassembling with Reassembling without Reassembling with Reassembling load load Figure 5. Latency vs. load (same valid cell size) Figure 6. Latency vs. load (different valid cell size) without Reassembling with Reassembling load proportion of short packet Figure 7. Latency with uniform distributed packet length Figure 8. Short packet delay vs. packet length simulate an 8 8 switch. Two components have the same source packets (cells) representation as raw traces. The fixedlength component adopts islip algorithm as the scheduling algorithm, while adopts modified islip algorithm [17] by updating switch fabric configuration in EOP (end of packet) cells and excluding preoccupied input/output ports from arbitration. A reassembling component is used to reassemble packets under. Eventually, a statistic component computes the performance parameters by the tag information that is added by former components. We exam the average packet latency: the time difference between an instant when the head of an IP packet enters the switch module and an instant when the tail of the IP packet passes through the switch module. Suppose that, the cells of two switching modes deliver the same valid data (56 Bytes). Figure 5 compares the packet latency of and with packet length being trimodal distributed. Packet lengths are chosen equal to either 40 Bytes with probability 0.559, or 572 Bytes with probability 0.2, or 1500 Bytes with probability The latency increases as the load increases. The performance of the exhibits larger latency than under low to media load. However, taken the reassembling effect that is discussed in section 5 into account, obtains much larger latency. As mentioned in section 3, the valid cell size of variablelength switching is 64 Bytes, while the valid cell size of fixedlength switching is 56 Bytes. The simulation result in figure 6 considers the different valid cell size. It reveals that fixedlength switching suffers large latency even disregarding reassembling delay. The reason is that it creates more cells than. Figure 7 shows the packet latency with uniform distributed packet length. The packet length is uniformly distributed between 40 Bytes and 1500 Bytes. The performance of the exhibits better than fixed-length switching. The increase of the load increases the contention probability that lead to larger latency. When load is low, the queuing latency is small, so the reassemble delay (time to transfer the packet) affects the latency performance badly. Queuing delay increases as the load increases. Therefore the reassemble effect becomes slighter. Intuitively, short packets may be blocked due to the transfer of long packets under that increase the short packet delay. Figure 8 highlights the starvation effect. Simulation is carried out under traffic load of 0.75 and the packet length is bimodal distributed. Packet lengths are chosen

6 equal to either 40 Bytes or 1500 Bytes with the probability of p and 1 -p, where p represent the proportion of short packet in the traffic. The curve of indicates that long packets have little effect on short packet, while the curve of reveals the opposite. The smaller the proportion of short packet is, the larger the probability of being blocked by long packets is, and therefore the larger latency obtains. With the proportion of short packets increases, short packets may obtain smaller latency than fixed-length switching. VII. CONCLUSION This paper studies the comparison of and. Analysis and simulations are establishes to investigate various performance measures including bandwidth loss, packet loss, segmentation and reassembly overhead, as well as average packet delay. The focus of the paper is on identifying key parameters that influence the outcome of this comparison, and on quantifying the potential benefits of each switching mode. We recommend that in high speed networks it is more reasonable that incoming IP packets pass through a switch fabric based on. The main advantages of using this packet scheduling algorithm are as follows: First, this scheme can reduce switching complexity because it is not necessary to perform scheduling at each single cell time. Second, this packet scheduling algorithm can avoid additional delays in reassembly buffers. Additionally, the packet delay can be a better measure than the cell latency for user QoS requirements because each packet itself represents more information. From the viewpoint of packet delay, packet scheduling schemes may perform better than cell scheduling schemes. Third, suffers less bandwidth loss. Admittedly, long packets may block short packets and larger buffer is required to avoid packet loss when variablelength switching is adopted. Our future work will be located on the methodologies that can be proposed to reduce average short packet delay and buffer space of. [5] N. McKeown, islip: a scheduling algorithm for input-queued switches, IEEE Trans. on Networking, vol. 7, no.2, pp , April [6] J.G. Dai and B. Prabhakar, The throughput of data switches with and without speedup, INFOCOM 2000, pp [7] K. Kar, D. Stiliadis, T. V. Lakshman and L. Tassiulas, "Scheduling algorithms for optical packet fabrics," IEEE J. Sel. Areas Commun., vol. 21, no. 7, pp , Sept [8] Vitesse. VSC 870 Data Sheet Rev4.2: High Performance Serial Backplane Transceiver [9] Vitesse. VSC 880 Data Sheet Rev4.2: High Performance 16x16 Serial Crosspoint Switch [10] MA. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, Packet Scheduling in Input-Queued Cell-Based Swithces, INFOCOM 2001, pp [11] MA. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, Packetmode Scheduling in Input-Queued Cell-Based Swithces, IEEE Trans. on Networking, vol. 10, no. 5,October 2002, pp [12] Y. Ganjali, A. Keshavarzian, and D. Shah, Input Queued Switches Cell Switching vs Packet Switching, INFOCOM [13] A. Shaw, Fixed-length packets versus variable-length packets in fast packet switching networks, Massachusetts Inst. Technol., Cambridge, Tech. Rep., Mar [14] S. Parekh and K. Sohraby, Some performance trade-offs associated with ATM fixed-length variable-length cell formats, ICC 88. [15] I. Cidon, J. Derby, I. Gopal, and B. Kadaba, A critique of ATM from a data communications perspective, Journal of High Speed Networks, vol. 1, no.4, pp , [16] M. Naghshineh and R. Cuerin, Fixed versus variable packet sizes in fast packet-switched networks, Infocom 93, vol.1: March-1 April [17] Sung-Ho Moon and Dan Keun Sung, High-Performance Variable- Length Packet Scheduling Algorithm for IP Traffic, GLOBECOM 01, vol.4: , Nov [18] Cristian Estan George Varghese, New Directions in Traffic Measurement and Accounting, SIGCOMM 02, August 19-23, 2002, Pittsburgh, Pennsylvania, USA. ACKNOWLEDGMENT This work was supported NSFC (No and No ), China 863 High-tech Plan (No. 2003AA and No. 2002AA ), and China/Ireland Science and Technology Collaboration Research Fund (CI ). REFERENCES [1] M.Karol, M. Hiluchyj,and S.Morgan, Input Versus Output Queueing on a Space Division Switch, IEEE Trans. on Comm., vol. 35, no.12, pp , [2] N. McKeown, "A fast switched backplane for a gigabit switched router," Business Communications Review, vol. 27, no. 12, Dec [3] N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, and M. Horowitz, "Tiny Tera: a packet switch core," IEEE Micro, vol. 17, no. 1, pp , Jan.-Feb [4] N. McKeown, V. Anantharam, and J. Walrand, Achieving 100% Throughput in an Input-Queued Switch, IEEE Trans. on Comm., vol. 47, no. 8, pp , Aug