Lecture 18: Communication Models and Architectures: Interconnection Networks

Transcription

1 Design & Co-design of Embedded Systems Lecture 18: Communication Models and Architectures: Interconnection Networks Sharif University of Technology Computer Engineering g Dept. Winter-Spring 2008 Mehdi Modarressi

2 Fully Connected Network The shortest delay But: Not scalable ½ (N (N-1)) links Impossible for large networks

3 Crossbar Reducing the complexity of fullyconnected networks while all the modules are connected Low latency Number of switching elements (cost): O(P 2 ) Not scalable (cost) Non-blocking: No connections block any connections between other processors and memory units;

4 Interconnection Networks Today buses are the dominating technology for small systems We saw that buses have severe limitations that become evident, if the number of components in a system is large The bus is a communication bottleneck, bandwidth is limited Buses are only scalable to a certain extent Interconnection networks Overcome the limitation of buses Provide a much larger amount of communication resources and are scalable

5 Interconnection Networks Information in the form of packets is routed via channels and switches from one terminal node to another A terminal node can be any kind of component like Processor Memory Hardware component Bus-based system with several components, e.g. Processor and Memory

6 Interconnection Networks OSI Provides a 7-layer network protocol standard way to classify network components and operations Interconnection networks use a similar protocol stack corresponding to the 4 lowest layers of the OSI protocol

7 Interconnection Networks Message: is a continuous group of bits that is delivered from source terminal to destination terminal. A message consists of packets. A packet is the basic unit for routing and sequencing. Packets maybe divided into flits. A flit (flow control digit) often is the unit that is transferred across a channel in a single clock cycle. Flits do not have any routing or sequence information and have to follow the route for the whole packet.

8 Interconnection Networks Interconnection characteristics Topology Routing switching

9 Topology The network topology refers to the static arrangement of channels and nodes in the network Some well-known network topologies: Mesh Torus Tree

10 Routing Choose which paths a message takes through network Example X-Y routing algorithm in mesh and torus First direct the message in x dimension until reaches the column of the destination Then direct the message in y dimension

11 Routing Deterministic: a unique path is determined based on a predefined algorithm, e.g. X-Y Adaptive: Current state of the network is also used to determine the route Deterministic (X-Y) Adaptive

12 Switching The way data traverse the route Two well-known methods: Store-and-Forward and Wormhole Store-and-forward Packets passes from node to node Each node stores the entire packet After examining the packet header, the node forwards it on the appropriate link Wormhole Packets are passed as a train of flits through a series of nodes less buffer space Pipelining the transmission

13 Switching

14 Router Components Input ports FIFO buffer Control logic Perform the route computation Determine output port for each incoming packet Arbitrate among inputs directed at same output Crossbar Connects each input to any output Output ports

15 Router Architecture

16 Router Crossbar Each buffer can connect an input to an output An input is connected to an output t based on the routing and arbitration

17 Router Architecture The buffers are implemented as FIFOs The routing logic reads the flit at the head of the fifo The flit in the head cab be 1. The header flit of a packet which contains routing information i.e. the packet destination 2. A body flit 3 A tail flit which is the last flit 3. A tail flit which is the last flit of a packet

18 Router Architecture- Control Function At each cycle, router checks the lit in the head of the fifio buffer of every input port If the head of the buffer contains a header flit: Read the destination address from the flit and pass it to the routing logic Routing logic determines the output port based on the destination address and the routing algorithm More than one output ports may be determined in case of adaptive routing Each port may have a separate routing logic

19 Router Architecture- Control Function If the head of the buffer contains a header flit (continued ): The arbiter does not send grant to the requesting ports if the requested port is busy If the requested port is free, selects one of the requesters according to the arbitration policy and send it grant Set the output port status as busy In the requesting input port Upon receiving grant, the header flit is directed to the selected output port Each output port has a separate arbiter

20 Router Architecture- Control Function

21 Router Architecture- Control Function If the head of the buffer contains a body flit A path is already set by the header flit Routing is carried out Abi Arbitration i is accomplished and grant is received The crossbar is set appropriately Simply pydirect it toward the destination output port

22 Router Architecture- Control Function This connection is set until the entire packet is transmitted

23 Router Architecture- Control Function If the head of the buffer contains a body flit Direct it to output port as other flits Free the output port used by this port, i.e. set its status as free

24 Flow Control Link-level flow-control To prevent overflow in a buffer