OpenSMART: An Opensource Singlecycle Multi-hop NoC Generator
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1 OpenSMART: An Opensource Singlecycle Multi-hop NoC Generator Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab ( OpenSMART ( Nov 12, 2017
2 OpenSMART NoC NoC generated by OpenSMART NIC NIC NIC NIC Router Router Router Router Router Router Router Router NIC NIC NIC NIC Interface AMBA Wishbone Custom 2
3 Challenges for NoCs Scalability - Supporting many-ip heterogeneous system - Lower latency - Lower area & energy Flexibility - Support diverse connectivity for custom heterogeneous system - Support diverse latency/throughput requirements Design-cost - Automating the design of high-performance, low-energy NoCs - Lowering design/verification costs of SoCs with NoCs 3
4 OpenSMART Low Cost Flexibility Scalability User-configurable Automatic NoC Generation High-level HW Lanugage SMART NoC Krishna et al, HPCA 2013 Chen et al, DATE 2013 Krishna et al, IEEE Micro Top Picks 2014 Highly-modular Pre-verified Building Blocks Arbitrary Topology Support OpenSMART Area/power-efficient RTL Building Blocks 4
5 SMART NoC Single-cycle Multi-hop Asynchronous Repeated Traversal SSR (SMART Setup Request) SSR (SMART Setup Request)SSR (SMART Setup Request) S SMART: HPCmax achieve the performance Krishna et al, HPCA of dedicated 2013 Chen al, DATE 2013 connections over a network Krishna al, of IEEE shared Micro links Top Picks 2014, D 1-cycle (no other traffic) 5
6 Features of SMART Low latency network - Dynamic bypass of intermediate routers between any two routers - Limit: HPCmax (hops per cycle max), maximum number of hops that the underlying wire allows the flit to traverse within a clock cycle Separate control path - HPCmax bits from every router along each direction - Arbitration of multiple bypass requests on the same link - No ACK required 6
7 How to Get the Source Code Go to Synergy lab homepage (synergy.ece.gatech.edu) 7
8 How to Get the Source Code In the released tools tap, click OPENSMART 8
9 How to Get the Source Code You will be forwarded to access request form page. Please fill and submit the form, then you will get a link to OpenSMART repository 9
10 How to Get the Source Code Using the link, you can access to the repository 10
11 Source Tree (Under Backend/BSV) Frontend: Configuration Parser (under development) Backend/BSV: BSV implementation (Main files) - src: Building blocks - Network.bsv : Connectivity configuration (default: Mesh) - Types/Types.bsv : Topology (Number of routers), VC, Routing algorithm, SMART (HPCmax) configuration - lib: Fundamental BSV libraries (FIFOs and CReg) - testbenches: Include synthetic traffic-based simulation Backend/Chisel: Chisel implementation (Router only) 11
12 OpenSMART Design Flow Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input SMART Output Building Block Library (RTL) HPCmax Analyzer Switch OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files 12
13 How to Specify a topology In Backend/BSV/src/Network.bsv for(integer i=0; i < meshheight; i++) begin 65 for(integer j=0; j < meshwidth -1; j++) begin 66 mkconnection(routers[i][j].datalinks[east].getflit, routers[i][j+1].datalinks[west].putflit) 67 mkconnection(routers[i][j].controllinks[east].putcredit, routers[i][j+1].controllinks[west].getcredit) 68 end 69 end Interconnecting all the data/credit West -> East links in a mesh network Can change connectivity using mkconnection with different routers/links Automation of this process is under development 13
14 OpenSMART Design Flow Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input SMART Output Building Block Library (RTL) HPCmax Analyzer Switch OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files 14
15 How to Configure OpenSMART In Backend/BSV/Types/types.bsv 1 typedef Benchmark Cycle 2 typedef 32 DataSz Flit data size 3 typedef 4 NumFlitsPerDataMessage Determine number of flits in a packet 4 5 typedef 6 UserHPCMax Determine HPCmax (SMART feature) 6 typedef 8 MeshWidth Mesh dimension (determines number 7 typedef 8 MeshHeight of routers) 8 9 typedef 4 NumUserVCs Determinenumber of VCs currentroutingalgorithm = XY_; Determine routing algorithm 15
16 OpenSMART Design Flow Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input SMART Output Building Block Library (RTL) HPCmax Analyzer Switch OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files 16
17 OpenSMART Building Blocks Buffer Arbiter Input VC Selector Arbiter Output Input buffer + Input VC arbitration Output VC selection + Output port arbitration + Credit management >> Switching (via crossbar) + Routing calculation Crossbar Switch Routing Calculator SSR SSR Controller Bypass Flag SMART SSR communication & Arbitration + Bypass flag 17
18 OpenSMART Router Incoming Flits Input Arbiter OpenSMART Router Arbiter (Baseline) Outgoing Flits Flit Input s Flit Header Flit Size Flit Data Output s Input Buffers Number of VCs/VC Depth >> Flit Header Switch Flit Data 18
19 OpenSMART Router Incoming Flits Output Port Request Output Arbiter OpenSMART Router (Baseline) Outgoing Flits Output Port Grant Input s Output Arbiter s VC Selector >> nextvc Switch VC nextvc VC queue hascredit Credit Manager Credit 19
20 OpenSMART Router Incoming Flits From Input s OpenSMART Router (Baseline) Input s Switching Output s >> >> >> >> >> Routing Switch Algorithm Outgoing Flits Outgoing Flits Crossbar Routing 20
21 OpenSMART Router (SMART) Incoming SSRs Incoming Flits Incoming SSRs Input s SMART OpenSMART Router (SMART) SSR From Local Router SSR Controller SMART Arbiter Output s Priority >> Switch Outgoing SSRs >> Priority SMART HPCmax Bypass Flag Prioritization by distance -> SSR from a nearer SSR Prioritization router gets the higher priority (Local (distance = 0) has the highest prirority) Bypass MUX Selection Outgoing SSRs Outgoing Flits 21
22 Walk-through Example Router Incoming r4 sends a flit to router r7 Router SSRs r5 sends a flit to router r7 Dist = 0 SSR From Local Router SMART Arbiter HPCmax = 3 Dist = 3 Bypass Cycle Cycle 1: Multi-hop 0: SSR Bypass Flag Dist = 2 Priority Send Dist = SSR (SMART 110Setup Request) 110 From: r4 From: r Winner r5 r6 r7 SMART in r5 22
23 OpenSMART Design Flow Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input SMART Output Building Block Library (RTL) HPCmax Analyzer Switch OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files 23
24 How to Run OpenSMART In Backend/BSV/ >./OpenSMART c Compile synthetic trafficbased Simulation >./OpenSMART r Run compiled simulation >./OpenSMART v Generate Verilog code >./OpenSMART clean Clean up build files 24
25 How to Run OpenSMART Simulation Compilation Print-out Messages 25
26 How to Run OpenSMART Simulation Print-out Messages Simulation Ticks: every 10,000 cycles Indicates if the simulation is alive or not 26
27 How to Run OpenSMART Simulation Print-out Messages Send/Receive counts for every router Summary of the total statistics 27
28 How to Run OpenSMART Generating Verilog files Similar print-out messages as simulation compilation 28
29 How to Run OpenSMART Generating Verilog files Verilog files are generated in./verilog 29
30 OpenSMART Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input SMART Output Switch Building Block Library (RTL) Thank you! HPCmax Analyzer OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files OpenSMART( 30
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