Applica'on Aware Deadlock Free Oblivious Rou'ng

Transcription

1 Applica'on Aware Deadlock Free Oblivious Rou'ng Michel Kinsy, Myong Hyo Cho, Tina Wen, Edward Suh (Cornell University), Marten van Dijk and Srinivas Devadas Massachuse(s Ins,tute of Technology

2 Outline Rou,ng algorithms and Mo,va,on Applica,on Aware Oblivious Rou,ng Bandwidth Sensi,ve Rou,ng Approach Router Architecture and Performance Analysis Plans for the Future

3 Oblivious Rou'ng Sta,cally determined given the source and des,na,on addresses XY Rou'ng Dc DB DA SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand

4 Oblivious Rou'ng Sta,cally determined given the source and des,na,on addresses XY Rou'ng (+) Simple and fast router designs Dc DB DA SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand

5 Oblivious Rou'ng Sta,cally determined given the source and des,na,on addresses XY Rou'ng (+) Simple and fast router designs ( ) Lead to network under u,liza,on ( ) Lack proper load balancing SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand Dc DB DA

6 Adap've Rou'ng Routes dynamically adjusted based on network status Dc DB DA SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand

7 Adap've Rou'ng Routes dynamically adjusted based on network status (+) Be(er load balancing and path diversity (+) Poten,ally be(er throughput and latency Dc DB DA SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand

8 Adap've Rou'ng Routes dynamically adjusted based on network status (+) Be(er load balancing and path diversity (+) Poten,ally be(er throughput and latency Dc DB ( ) Need for global or local knowledge of network condi,ons ( ) Router complexity SA SB SC Link Capacity 50 Mbytes/sec Each flow has 25 Mbytes/sec bandwidth demand DA

9 Mo'va'on Can we get the best of both worlds? (+) Simple and fast router designs (+) Be(er load balancing (+) Poten,ally be(er throughput and latency

10 Mo'va'on Given an applica,on, with knowledge of data communica,on pa(erns, can we determine a set of sta,c routes that performs be(er than conven,onal oblivious rou,ng? Exploit knowledge of bandwidth demands (or latency requirements) Ensure deadlock freedom

11 PlaMorms and Suitable applica'ons Suitable for applica,ons with predictable communica,on pa(erns video compression processor simula,on rendering Reconfigurable hardware: processing elements and their interconnec,on network can be configured

12 Outline Rou,ng algorithms and Mo,va,on Applica,on Aware Oblivious Rou,ng Bandwidth Sensi,ve Rou,ng Approach Router Architecture and Performance Analysis Plans for the Future

13 Applica'on Aware Rou'ng Framework Step 1: Use the targeted network topology and resources (e.g., buffer space) to create a conven;onal channel dependency graph (CDG) D of the network. F E D A B the mesh is transformed into a CDG C FE ED DC CB BE EF FA AB BC CD DE EB BA AF

14 Applica'on Aware Rou'ng Framework Step 1: Use the targeted network topology and resources (e.g., buffer space) to create a conven;onal channel dependency graph (CDG) D of the network. Ver,ces in the CDG represent network links F A E B D C the mesh is transformed into a CDG FE ED DC CB BE EF FA AB BC CD DE EB BA AF

15 Applica'on Aware Rou'ng Framework Step 2: Create (new) acyclic CDG D A by dele;ng some edges from D. Because the channel dependency graph D derived from the network topology may contain many cycles FE ED DC CB BE EF FA AB BC CD DE EB BA AF Well known result: Having cycle free dependency graph ensures deadlock freedom

16 Turn Model (Glass and Ni, 1994) A systema,c way of genera,ng deadlock free routes with small number of prohibited turns Deadlock free if routes conform to at least ONE of the turn models (acyclic channel dependence graph) West First Turn Model North Last Turn Model

17 Acyclic CDG Deadlock free routes Per the North-Last prohibited turns, all the edges in red are deleted F A E B D C FE ED DC CB BE EF FA AB BC CD DE EB BA AF North Last Acyclic CDG AB FE ED DC CB BE EF FA BC CD DE EB BA AF

18 Acyclic CDG Deadlock free routes Turns could be prohibited at ad-hoc, all the edges in red are deleted F A E B D C FE ED DC CB BE EF FA AB BC CD DE EB BA AF Ad hoc Acyclic CDG FE EB AB BE BC ED CD DC DE CB EF BA FA AF

19 Acyclic CDG Deadlock free routes Turns could be prohibited at ad-hoc, all the edges in red are deleted. F A E B D C FE ED DC CB BE EF FA AB BC 5 edges are CD deleted here vs. DE EB BA 4 edges in the North last AF Ad hoc Acyclic CDG FE EB AB BE BC ED CD DC DE CB EF BA FA AF

20 Applica'on Aware Rou'ng Framework Step 3: Transform D A into a flow network G A, given a set of k flows denoted K. Flows K = {K 1, K 2,, K k }. K i = (s i, t i, d i ), where s i and t i are the source and sink, for connec,on i, and d i is the demand

21 Applica'on Aware Rou'ng Framework Step 3: Transform D A into a flow network G A, given a set of k flows denoted K. Part of the modular decomposi,on of the H.264 decoder, with the following es,mated bandwidths and placement: K 1 : 39.7 MB/s Inverse transform/ Quan,za,on Module K 2 : 39.7 MB/s Video bitstream Entropy Decoder Module Other modules Intra Predic,on/ Deblocking Reconstruc,on Module Flow ID Source Des,na,on Demands K 1 F B 39.7 MB/s K 2 B D 39.7 MB/s

22 Applica'on Aware Rou'ng Framework Step 3: Transform D A into a flow network G A, given a set of k flows denoted K. Flows are routed on CDG not on network To rou,ng K 1 = ( F, B, 39.7 MB/s) on the ad hoc acyclic CDG "$ $% %! (!!" "# #& &$ ' $ %$ $" $& &# #" "!!% Dummy nodes s F and d B are created to drive flow K 1 from its source F and to sink it into B

23 Applica'on Aware Rou'ng Framework Step 3: Transform D A into a flow network G A, given a set of k flows denoted K. Flows are routed on CDG not on network To rou,ng K 2 = ( B, D, 39.7 MB/s) on the ad hoc acyclic CDG %$ $& &# #" "!!% $" ( ' # $ "#!" "$ #& &$ $% %! Dummy nodes s B and d D are created to drive flow K 2 from its source B and to sink it into D

24 Applica'on Aware Rou'ng Framework Step 3: Transform D A into a flow network G A, given a set of k flows denoted K. Flows are routed on CDG not on network To rou,ng K 2 = ( B, D, 39.7 MB/s) on the ad hoc acyclic CDG (' ') )# #" "!!( '" + * "# # '!" "' #) )' '( (! Edges into BE are assigned the capacity of link BE in the mesh No capacity or weight is assigned to the edges incident on sink nodes

25 Applica'on Aware Rou'ng Framework Step 4: Perform applica;on aware rou;ng of the flows in G A. Step 5: If desired, go to Step 2 and repeat using a different acyclic CDG. Step 6: Select the best set of routes found, per the rou;ng func;on used in Step 4. In Step 4, bandwidth sensi,ve rou,ng can be used as a type of applica,on aware rou,ng scheme

26 Outline Rou,ng algorithms and Mo,va,on Applica,on Aware Oblivious Rou,ng Bandwidth Sensi,ve Rou,ng Approach Router Architecture and Performance Analysis Plans for the Future

27 Bandwidth Sensi've Oblivious Rou'ng (BSOR) Goal: Route flows while minimizing the maximum channel load (MCL) U in the network: %$ $& minimize &# U = max #" $" ( ' # $ "#!" "$ #& v E k i=1 "! (u,v) E f i (u,v) v is a link/vertex in the CDG (e.g., ED)!% f i (u, v) is the edge s bandwidth used by flow i (e.g., f 1 (BE, ED) = 0 where &$ f 2 (BE, ED) = 39.7) $% %!

28 Bandwidth Sensi've Oblivious Rou'ng (BSOR) Goal: Route flows while minimizing the maximum channel load (MCL) U in the network: %$ $& minimize &# U = max #" $" ( ' # $ "#!" "$ #& v E k i=1 v is a link/vertex in the CDG (e.g., ED) "! (u,v) E f i (u,v)!% f i (u, v) is the edge s bandwidth used by flow i (e.g., f 1 (BE, ED) = 0 where &$ f 2 (BE, ED) = 39.7) $% U denotes the channel with the highest load which is the bo(leneck channel in the en,re network and determines the satura,on throughput of the system %!

29 BSOR Algorithms Unspli(able flow problem is NP hard Mixed Integer Linear Programming (MILP) can provide an op,mal solu,on in worst case exponen,al,me Works for small problems with ~100 flows Dijkstra s weighted shortest path algorithm provides a polynomial,me heuris,c that produces good results

30 Mixed Integer Linear Programming Capacity: Flow conserva,on: k v s i,t i h(v) = f i (u,v) c(u,v) i=1 (u,v) E i, u s i,t i f i (w,u) = f i (u,w) (w,u) E (u,w) E Unspli(able flow: i, f i (s i,w) = f i (w,t i ) = g i (s i,w) E (w,t i ) E Hop count: helps control i b i (u,v) hop i (u,v ) E path lengths i, (u,v) E, f i (u,v) b i (u,v) d i i, u (u,v ) E b i (u,v) 1

31 Mixed Integer Linear Programming Capacity: Flow conserva,on: i, u s i,t i f i (w,u) = f i (u,w) (w,u) E k v s i,t i h(v) = f i (u,v) c(u,v) i=1 (u,v) E (u,w) E Unspli(able flow: i, f i (s i,w) = f i (w,t i ) = g i (s i,w) E (w,t i ) E Hop count: helps control i b i (u,v) hop i (u,v ) E path lengths i, (u,v) E, f i (u,v) b i (u,v) d i i, u (u,v ) E b i (u,v) 1

32 Dijkstra s weighted shortest path BSOR Polynomial,me (suitable for large size problems) Greedily route one flow at the,me The weigh,ng func,on: Residual capacity:

33 Dijkstra based Flows rou'ng Illustra'on For flow K 1 (F, B, 39.7 MB/s) "' '( (! F E D +!!" "# #) )' * ' A B C (' '" ') )# #" "!!( We consider all possible routes for flow K 1 conforming to the acyclic graph Here the ad hoc acyclic CDG is used

34 Dijkstra based Flows rou'ng Illustra'on For flow K 1 (F, B, 39.7 MB/s) "' '( (! F E D +!!" "# #) )' * ' A B C (' '" ') )# #" "!!( We consider all possible routes for flow K 1 conforming to the acyclic graph Final route corresponds to the best path in CDG determined by the weigh,ng func,on

35 Dijkstra based Flows rou'ng Illustra'on For flow K 2 (B, D) 39.7 MB/s F E D (' ') )# #" "!!( A B C '" + * "# # '!" "' #) )' '( (! Arer the edge weights are adjusted from the rou,ng of K 1, we consider all possible routes for K 2 conforming to the acyclic graph

36 Dijkstra based Flows rou'ng Illustra'on For flow K 2 (B, D) 39.7 MB/s F E D (' ') )# #" "!!( A B C '" + * "# # '!" "' #) )' '( (! Final route corresponds to the best path in CDG determined by the weigh,ng func,on Here both routes permi(ed under the acyclic CDG have the same weight

37 Dijkstra based Flows rou'ng Illustra'on F E D A B C Final routes for the two flows are as shown Rou,ng order of flows in Dijkstra based algorithms does affect route selec,on MILP produces the minimal MCL through exhaus,ve search

38 Comparison of Maximum Channel Load Transpose: Bit Complement: Shuffle: H.264 decoder: bandwidths and flows derived through profiling Traffic XY YX ROMM Valiant Dijkstra MILP Transpose Bit comp Shuffle H

39 Outline Rou,ng algorithms and Mo,va,on Applica,on Aware Oblivious Rou,ng Bandwidth Sensi,ve Rou,ng Approach Router Architecture and Performance Analysis Plans for the Future

40 Baseline architecture Router architecture VC Allocator VC state crossbar switch Rou,ng Module Switch Allocator VC state Output Port Output Port Router: rou,ng phases Rou,ng Computa,on (RC) Virtual Channel Alloca,on (VA) Switch Alloca,on (SA) Switch Traversal (ST) PE L R PE H R PE G R PE E R PE F R PE D R PE B R PE A R PE C R 3x3 Mesh network Typical virtual channel router

41 Router for Applica'on Aware Rou'ng Rou,ng Module VC Allocator Switch Allocator Rou,ng Computa,on (RC) VC state Output Port Virtual Channel Alloca,on (VA) Switch Alloca,on (SA) VC state crossbar switch Output Port Switch Traversal (ST) Router architecture Router: rou,ng phases We need modifica,ons to the standard router architecture for applica,on aware rou,ng The main change required is in the rou,ng module The rou,ng module needs table based rou;ng

42 Two ways of Table Based Rou'ng C packet A B N N E N N RC RC RC N packet C A B 1 out index 2 0 N 3 1 E 2 2 W 5 out index 0 N 3 1 E 5 2 W 1 0 out index 0 E 1 1 S 6 2 N 0 Source rou,ng Node table rou,ng Source rou,ng eliminates the rou,ng step, but results in longer packets Node table rou,ng Each module contains a rou,ng table, which is looked up at every hop but this does not change the per hop latency

43 Performance Analysis Benchmarks : Synthe,c: Transpose, Bit Complement, and Shuffle Applica,on: H.264 Decoder Simulator : a cycle accurate network simulator 8 X 8 2 D mesh network with 1, 2, 4 or 8 VCs per port Fixed packet length : 8 flits Per hop latency : 1 cycle Flit buffer size per VC : 16 flits Simula,on for 100,000 cycles arer 20,000 cycles of warm up

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46 In H.264 head of blocking is the limi,ng factor for BSOR More VCs to mi,gate the effects We also propose a different heuris,c BSORM (Bandwidth Sensi,ve Oblivious Rou,ng with Minimal Routes) which requires two virtual channels [NOCS 09]

47 "'% "'$ "'# "'" " &'% &'$ &'# &'" &!"#$!"#$'()*"+&"'&,# DC- EF(5- CD- DC- EF(5-!'%! " # $ % &! &" ())*+*,-./0*1234/-562*-78619*2:;1<1=*>!'%! " # $ % &! &" Bandwidth of each Individual flow is changed by 10% and 50% in a random fashion?426=-?@+4ab@8a *2:;1<1=*> ROMM and Valiant do not do as well as DOR algorithms Complete summary of our experimental results in the paper "'% "'$ "'# "'" " &'% &'$ &'# &'" &!"#$!"#$'()*"+&"'&,# CD- ())*+*,-./0*1234/-562*-78619*2:;1<1=*>

48 Conclusion Our applica,on aware framework has same router speed and complexity as required by other oblivious algorithms It does be(er load balancing, (therefore shows be(er performance) than other oblivious algorithms It can handle even substan,al run,me bandwidth varia,on with no significant performance degrada,on

49 Conclusion Its limitation: need some knowledge of the application To handle bursty flows, we have proposed bandwidth-adaptive networks that contain adaptive bidirectional links [PACT 09] Ongoing work: - How does bandwidth-sensitive routing do on the bandwidth-adaptive network?

50 Q & A Sec'on Thank You! More Informa,on at h(p://csg.csail.mit.edu Also thanks to Keun Sup Shim and Mieszko Lis for their contribu,on, comments and valuable feedback