A Survey on various Reconfigurable Architectures for Wireless communication Systems

Transcription

1 Volume 119 No , ISSN: (on-line version) url: ijpam.eu A Survey on various Reconfigurable Architectures for Wireless communication Systems Karthi S P 1, Kavitha K 2 1 Assistant Professor Electronics and Communication Engineering Sri Krishna College of Engineering and Technology Coimbatore , India. karthisp@skcet.ac.in 2 Professor Electronics and Communication Engineering Kumaraguru College of Technology Coimbatore , India kavitha.k.ece@kct.ac.in Abstract Reconfigurable architecture plays a vital role in the development of communication system. In a recent study, it is estimated that 20 billion devices will be connected to the internet in the near future due to the development in IoT. The demand for higher data rates, computational complexity are also changing dynamically.one hardware for multiple functions is the only solution to the rapid development in wireless communication system. In this paper various reconfigurable methods are discussed. Keywords : Reconfigurable architecture, IoT, computational complexity. 1. INTRODUCTION The goal of future wireless communication systems will be to integrate different wireless technologies and architectures into an efficient seamless wireless infrastructure [1]. A new architecture in which researchers are focusing in the 1427

2 recent time is the reconfigurable architecture which combines the benefits of FPGA and ASIC. It provides hardware flexibility for any architecture and design. Reconfigurable architecture increases the performance of hardware and it is made possible by FPGAs [11]. In future wireless communication system, adaptivity of the system becomes more important and all the communication devices will become multi-mode and multifunctional devices. Heterogeneous reconfigurable hardware offers more flexibility for performing multiple wireless standards. The main aim of introducing reconfigurable hardware is in any wireless terminal is to support various wireless standards [2]. First level of adaptivity introduces the support of multiple wireless communication standards in a single wireless terminal. The terminal can switch between various wireless communication standards.for example when packet data transport is performed over UMTS and a WLAN hotspot becomes available the terminal can switch from UMTS to a WLAN standard. This is referred to as standards level adaptivity. Algorithm-selection is the second level of adaptivity. Algorithms are used to implement the DSP functions. In this level, the communication system selects an algorithm from a set of algorithms. Algorithm parameter level is the third level of adaptivity, for a specific algorithm, it has the opportunity to change its parameters [1]. A reconfigurable architecture in a wireless terminal makes sense when it suits the needs of a user at a better efficiency and an acceptable complexity when compared to a traditional non-adaptive wireless terminal. The continuous development in wireless networks with different platforms leads to an increased interest in the design of reconfigurable architecture. 2. Reconfigurable Architecture Multi standard wireless communications demands several parameters like flexibility, scalability, computational complexity, and power [11]. Among the available options, an Application Specific Integrated Circuit (ASIC) would meet the high computing power requirement, but it is inflexible which makes them unsuitable for prototyping. Digital signal processing (DSP) chips are flexible, but it fails to provide Sufficient computing power. Field Programmable Gate Arrays (FPGA) are now widely being used in the base station designs. Due to the form factor and low power requirements have prevented their usage in handsets. Reconfigurable hardware for Digital Base-Band (DBB) processing is gaining its massive usage in multi standard wireless communication devices. 3. Reconfiguration process Reconfiguration is a mechanism of modifying the functions of a module by altering its internal structure at real time. The functions of the hardware which changes with respect to the situation or the need in real time. For example if a 1428

3 hardware is designed to receive a data in two different standards it will change its function in real time with respect to the data it receives. Reconfiguration leads to a better performance with good efficiency and smaller system size. On the other hand coarse-grained architecture requires a very less configuration time and lower potential energy compared to a coarse-grained architecture because of fewer elements for programming. The process of implementing reconfigurability in one module by without affecting the rest of the module is the mechanism implemented in DPR. Due to this capability the area constraints can be reduced in the hardware. 3.1 MONTIUM architecture The MONTIUM processor is a reconfigurable processor which targets the 16 bit digital signal processing (DSP) algorithm. The architecture of a Montium processor looks similar to a VLIW processor but the control structure of Montium processor is different. Fig 1. MONTIUM TILE Processor 3.2 MOLEN Polymorphic Architecture The MOLEN architecture is capable of using both microcode and customconfiguring hardware mechanism for applications which demands high speed. It examines all kinds of processor requirements, from embedded systems to supercomputers. This working of this architecture is divided into two phases. The first phase takes care of the reconfigurable hardware and the fixed core units are 1429

4 executed in the second phase. The microcode instructions perform both the reconfiguration process and the execution of the core units. The microcode which is used again and again is located permanently inside the fixed part of an on-chip storage facility, and the microcode which is used infrequently is stored into the pagable part of the same storage unit. Due to the above capability this approach is used in various applications. 3.3 SDR (Software Defined Radio) Software defined radio (SDR) is a Flexible architecture that is suitable for many wireless standards which allows implementation of the signal processing algorithms in software instead of hardware. Through sampling & quantization process analog input signal is converted into fixed-point digital data. It founds applications in many fields such as communication, Electronic warfare, and instrumentation and broad-spectrum surveillance etc... Moving analog-to-digital converters (ADCs) and digital-to analog converters (DACs) as close as possible to the antenna, and to process the digitized data by a software is the core idea of SDR. 3.4 Reconfigurable heterogeneous Architecture Heterogeneous reconfigurable architecture might become the future of wireless hardware. The basic idea behind the use of heterogeneous reconfigurable hardware is that one can match the granularity of the DSP algorithms with the granularity of the hardware [3]. For example some algorithms perform operations best on bit-level while other performs best on word-level. Four types of processing elements can be distinguished: general purpose processor, fine-grained reconfigurable hardware, coarse-grained reconfigurable hardware and dedicated hardware. 3.5 Morphing system The MORPHOSYS system is an array of closely coupled reconfigurable cells associated with the core processor known as the tiny Reduced Instruction Set Computing (TinyRISC) processor, which performs million instructions per second (MIPS) processor. In this system each reconfigurable cell consists of 16 and 32 bit registers respectively with shift register, input/output (I/O) multiplexers, and an ALU. The direct memory access controller initiates the process by loading the configuration bits into the context memory from the main memory to transfer the data between the main memory and the frame buffer. MORPHOSYS is a reconfigurable single-instruction multiple-data architecture consists of various modules such as RC array and DMA module. In this system, dynamic reconfiguration is made possible by implementing the SDR architecture on top of the MORPHOSYS reconfigurable processor by updating the reconfigurable cells. 1430

5 3.6 ADRES system The ADRES system is an appropriate platform for both dynamic and partial reconfigurable operations and it gives a high degree of design freedom due to its flexibility. It is considered as an architecture design template for both dynamically reconfigurable and statically scheduled CGRA. It consists of various functional units such as instruction cache memory, global program RFs, and global data RFs for the purpose of speeding up the process of its execution. It is done by executing a single sequential logic thread for all its operations such as arithmetic, logical and predicate computing instructions. 4. Conclusion This paper focused on various research methods on reconfigurable architectures in recent years. Enormous number of research works were focused on reconfigurable architecture in the past few years. Due to the booming of IoT in recent days, the demand for an effective architecture for wireless communication system is increasing day by day and also the need for large amount of data transmission is increasing day by day because of increase in handheld electronic devices which is connected to the internet which ultimately leads to the computational complexity and dynamically changing software types. In order to match the current requirements and to provide the platform for the future needs, the performance of FPGA based architectures and devices needs to be improved in effective way by considering various parameters such as power consumption, data rate, physical size of the device, security etc... This study discussed different methods and techniques proposed in the earlier approaches to increase the performance of the FPGA based communication and also to provide an effective architecture for future wireless communication system. From the above survey it is clear inorder to achieve need for designing a new strategy for reconfiguring FPGA in terms of memory utilization, speed, cleaning, DSP, reducing the time, energy consumption and less cost. REFERENCES [1]. C. Subashini and Dr.K.Senthil Kumar,A Survey: Dynamic Reconfigurable Architectures in FPGA.Advances in Natural and Applied Sciences. [2]. Gerard J.M. Smit, Gerard K. Rauwerda, Reconfigurable Architectures for Adaptable Mobile Systems 1431

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