CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2011

Transcription

1 CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2011 GENERAL DEVELOPMENT CYCLE WITH FPGAS FOR A NEW CHIP 1. Introduction A digital product is developed as a new (digital) chip or as a new printed circuit board (PCB). The development for chips and PCBs involves three cycles and are similar. The cycles for a new chip are the development cycle on computers, the development cycle with Field Programmable Gate Array chips and finally, the development cycle on a prototype chip. The cycles for a new PCB are the development cycle on computers, the development cycle with offthe-shelf chips and finally, the development cycle on a prototype PCB. These development cycles are described in detail in the handout titled Digital Product Development. The development cycle on computers for chips and PCBs consists of three steps : the logic design, test and modify. The logic design consists of obtaining the precise input-output relationship and implementation. The test consists of simulation and verification of the circuit and modification is the simple change of the design after an error is encountered during testing. If we simulate and verify the design considerably to the point that we feel we have covered acceptable number of input combinations (test vectors) for which the output is correct, we can assume the circuit is correct. Therefore, the second development cycle can be started. What we would do depends on what we want to manufacture : a new chip or a new PCB. We would do the development cycle with FPGA chips, if we develop a new chip. Otherwise, we would do the development cycle with off-the-shelf chips. We will use an FPGA chip in the lab, hence in the lab we will practice developing a new chip. During lectures, however, we learn how to develop both new chips and new PCBs. This handout describes this second cycle for developing a new chip, the development cycle with FPGA chips : how to convert Xilinx schematics to a bit file, how to download the bit file to the FPGA chip and how to test the design on the FPGA chip. Consequently, this handout will be used throughout the semester. For all the labs, this process is the same. Here, we describe the process by using the standalone 2-to-1 MUX circuit. 2. Design Move from Computer to the FPGA to Develop a New Chip The development cycle with FPGA chips consists of three steps : mount, test and modify. Mounting means FPGA chips are mounted on bread/boards and wired. Then the FPGA chips are programmed. Testing means input combinations are applied to the bread/board circuits and outputs are observed. If unexpected outputs result, we modify the circuit on the bread/board. New FPGA chips might be mounted, as well as new wirings. We test the new circuit on the bread/board and continue the test until we are satisfied. If, however, modifying the circuit on the bread/board cannot correct the current error, the circuit on the computer is modified. After simulations and verifications show it is correct, we would return to the bread/board development cycle. If necessary, we mount new FPGA chips, do new wirings and program the FPGAs. We test it again and continue the test until we are satisfied. In the lab, the FPGA chip is already mounted and that is enough to complete the term project. Thus, we only perform FPGA programming in the mount step. The testing includes flipping switches and pressing push buttons to input different input values (test vectors) and observe the outputs connected to 7-segment displays and LED lights. If the output is incorrect, we have to change the schematic. We download the new design to the FPGA chip again. To modify the schematic, we go back to the development cycle on computers to modify the circuit. Then, we start the development cycle on the bread/board again. Finally, we would start the third development cycle, which is a prototype chip Mount Step of the Cycle with FPGA Chips As mentioned above, in CS2204, the mount step requires only the programming of the FPGA chip ( downloading the circuit to the FPGA chip), since our FPGA chip is already mounted on the board. Also, we do not mount any offthe-shelf chip. We just program (download to) the FPGA chip on the board. Thus, in the lab, we learn the development cycle with FPGA chips for a new chip. On Xilinx software, programming the FPGA chip requires two steps : Xilinx IMPLEMENTATION and PRO- Polytechnic Institute of NYU Page 1 of 8 General - Development Cycle with FPGAs for a New Chip February 1, 2011

2 GRAMMING. Note that the word IMPLEMENTATION is capitalized to indicate that it is a Xilinx step. The name IMPLEMENTATION is selected by Xilinx and we keep it. To start the Xilinx IMPLEMENTATION step, we have to have the Project Manager window on the screen : Xilinx IMPLEMENTATION : This step generates the bit file. When we do the first Xilinx IMPLEMENTATION on a project, Xilinx asks you to verify project information and allows you to change a number of IMPLEMENTATION options. Then, this step generates the bit file and other IMPLEMENTATION data if the project does not have errors. Subsequent IMPLEMEN- TATIONs on the same project uses the same options and utilizes the previous IMPLEMENTATION data to save time. However, because of software bugs, after a large number of IMPLEMENTATIONs, this data becomes corrupt and incorrect bit files are generated. Therefore, students are suggested that, they remove (clear) this IMPLEMENTA- TION data after four/five IMPLEMENTATIONs and then they do a new Xilinx IMPLEMENTATION : Follow Project -> Clear Implementation Data on the Project Manager window to clear that data. Click on IMPLEMENTATION button under the Flow tab in the Project Manager window. If a window appears asking whether to update the netlist from the schematic editor, select Yes. The Implement Design window appears : Polytechnic Institute of NYU Page 2 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

3 In the Implement Design window, the FPGA device used is XCS10PC84 of the Xilinx Spartan family where, XCS10 is the device type and PC84 is the packaging type 84-pin PLCC. Thus, S10PC84 as the option is correct. The device speed should be 3. The version name and revision name are automatically chosen by the software. For simple projects, such as the 2-to-1 MUX project, we do not have to change the IMPLEMENTATION options. But, for complex projects, such as the Tictac and Term Project, the IMPLEMENTATION options need to be changed so that a better bit file is generated. More specifically, the new options will require the Xilinx software to generate a faster and more efficient design so that the FPGA chip utilization and wire delays are within acceptable limits. If we are doing the Xilinx IMPLEMENTATION of the design the very first time or we cleared the implementation data on the Project Manager window, changing the options is as follows : Click on Options... on the Implement Design window. Change the Place and Route Effort Level to the maximum : High Effort. Go through the following menu selections starting with the same window. Locate the Program Options area of the window. Click Edit Options... of the Implementation : On the SPARTAN Implementation Options: Default window, click on Place and Route. Locate the Router Options area and then change the Routing Passes level from Auto to 50 and the Delay-Based Cleanup Passes level from 0 to 5. Click OK twice to close both windows. If the Xilinx IMPLEMENTATION has been done before and the IMPLEMENTATION data has not been cleared, the options are kept, so we do not have to enter them again : If you want to make sure the options you selected before are there, you can click on Options... on the Implement Design window. You can verify the options to confirm now. After changing the implementation options for a complex project, we are ready to start the conversion of the schematic design to the bit file, by clicking on Run in the Implement Design window. The Xilinx Flow Engine window shown below will appear and show the progress of the implementation : The IMPLEMENTATION steps are as follows : Polytechnic Institute of NYU Page 3 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

4 1) Translate : translation of the schematic components into FPGA elements corresponding to the target device (the Spartan XCS10PC84 chip), 2) Map : optimization of the logic and mapping of the design in the target FPGA device, 3) Place & Route : placing and routing of the design on FPGA configured logic blocks (CLBs), where the options of this are changed for complex projects as described on the previous page, 4) Timing (Sim) : calculation of timing information for timing simulations (the verification step), 5) Configure : generation of the bit file which will be used to program the FPGA The step that is performed at the moment is indicated as Running on the Flow Engine window and steps that are completed are marked as Completed. If you forgot to make FPGA pin assignments, the mapping step will optimize away the whole design, attempting to do both. But, often the pin assignment will not be incorrect. Therefore, after the Xilinx implementation completes, you will need to make the pin assignments yourselves after which you will do the Xilinx IMPLEMENTATION again. When the IMPLEMENTATION is complete a small window will pop up informing you that the Flow Engine Completed Successfully. Click OK. In the main Project Manager window, a green check mark appears next to all the schematic files of the project, also next to IMPLEMENTATION under the Flow tab, indicating that the implementation has been carried out successfully. The green check mark next to IMPLEMENTATION is often delayed by minutes. The successful completion also means that the bit file of the circuit has been created. In the context of the 2-to-1 MUX project, it means the bit file named mux2to1_bit has been generated. The PROGRAMMING button is now highlighted. If there is an implementation problem, the IMPLEMENTATION will be stopped. You need to read the error messages in the Implementation Log File accessable from the Reports selection of the Project Manager window. Based on the error messages, modify the schematic design and test it via functional simulations. Then, do another Xilinx IMPLEMENTATION. If there are problems, read the Implementation Log File again and continue modifying the schematic design until the implementation results in no errors. How much the IMPLEMENTATION options are effective can be observed by reading the Implementation Log File. Scroll down the text until you see the line that starts as Number of CLBs: At the end of the line a percentage is given which indicates the amount of space used by the design, i.e. the chip utilization. Scroll down the file text again until you see the Timing Summary: section. The maximum net delay is given for the whole design. If there are IMPLEMENTATION errors or the chip utilization or the wire delay is too high, continue to modify the design (schematics) and change the implementation options. After the Xilinx IMPLEMENTATION is completed, perform timing simulations (VERIFICATION) on the circuit, by trying the input combinations tried during the functional simulations and observing the outputs again. You would perform timing simulations to determine what causes unnecessarily long wire delay reported in the Implementation Log File to correct the design (schematic). Make sure to observe the outputs in the Glitch mode to see if there are timing hazards Downloading to (PROGRAMMING) the FPGA : Once the bit file is generated, it is downloaded to the FPGA chip during PROGRAMMING. That is, we download the schematic design to the FPGA chip so it behaves like our circuit. To program the FPGA, Click on the PROGRAMMING icon under the Flow tab of the Project Manager window). A small window appears presenting a choice of two programming tools, impact and PROM File Formatter. Select impact and click OK. Polytechnic Institute of NYU Page 4 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

5 The impact window below appears where a Xilinx chip picture with the name xcs10 is shown : Next, we select the Slave Serial mode to download the design : Click on Slave Serial in the impact window. You will see the impact window shown on the next page It is now time to take a look at the FPGA board. First, locate the parallel cable connector, a DB25 connector on the board. It is connected to the black Bitronics Data Switch. To the left of the DB25 connector is the power indicator LED light. Next, locate switch number 9 which is between the DB25 connector and the breadboard. SW9 determines how this parallel connection is to be used : either for programming of the FPGA or as a parallel port. Make sure SW9 is in the PROG position : only in the PROG position, the FPGA is programmable. Before we download the bit file to the FPGA chip, we need to make sure our PC is able to communicate with the FPGA board through the parallel connection. Notice that the FPGA board is shared by two PCs. Therefore, the two PCs cannot communicate with the FPGA board at the same time, and so, the two PCs cannot download to the FPGA board at the same time. At this point, students will discuss who will download first and the selected student will proceed with the steps below : Turn on the FPGA board. Locate the Bitronics Data Switch that has two PC cables connected to. It has two large arrow-shaped buttons used to select the PC to download. There are also two green LED lights next to these buttons. Only one of them is on at a time, pointing at the PC selected. Click on the arrow-shaped button pointing at the PC selected. The green light next to it will be lit, though not so bright. On the impact window shown on the next page, perform the following sequence of selections starting with the menu : Output -> Cable AutoConnect. Notice that the parallel cable is recognized and the No Connection message on the bottom of the impact window is replaced by Parallel Port LPT1 indicating that a download cable is present on parallel port lpt1. Polytechnic Institute of NYU Page 5 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

6 One can also check the cable connection, by right clicking on the Right click to Add Device text line in the middle of the impcat window, and selecting : Cable Auto Connect. If the cable is not detected, a window will pop up with the message that communications with the cable could not be established. It could be that the FPGA board is off. Check the power indicator LED light on the FPGA board. If the light is off, turn on the board. If the power is on and the cable is not detected, check if SW 9 is in the PROG position. If it is, there might another reason. Hence, inform the professor or a TA. Now, we are ready to download the bit file : Right click on the Right click to Add Device text line in the middle of the impact window and select Add Xilinx Device.... The Add Device window appears which shows the bit file to be downloaded. Polytechnic Institute of NYU Page 6 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

7 One can get the same Add Device window in another way : Make the following sequence of selections in the impact window : Edit -> Add Device -> Xilinx Device... Click on the bit file name and then click on Open. The device is now shown in the impact window : Right click on the device (the chip picture with the XILINX name and logo) and select Program This will download the bit stream (bit) file to the FPGA and a blue Programming Succeeded message appears. We complete the mount step! 2.2. Test Step of the Cycle on Breadboards with FPGA Chips We can now test the design. For our board in general, we do testing by using toggle switches, push buttons, 7-segment displays and LED lights on the FPGA board. These input and output devices are located on the side that is closer to you. The 2-to-1 MUX project has three inputs that are connected to SW1, SW2, and SW3 toggle switches and one output that is connected to LED light LD4. If one pulls the handle of a toggle switch towards himself/herself (i.e towards its label, such as SW1 ), the switch is turned on, generating 1. Otherwise, the switch generates 0. When LD4 gives off light, it means the output is 1. One has to check all input combinations to prove that the circuit behavior is as expected. For this 3-input circuit, the outcome of the test situations are shown on the table below : SW1 SW2 SW3 LD Polytechnic Institute of NYU Page 7 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011

8 Note that LD4 = 0 means the light is off and LD4 = 1 means the light is on. Test the circuit on the FPGA board, by trying all the test vectors that were tried during the functional and timing simulations and observing the outputs. Before we complete our discussion on PROGRAMMING, we give the pin assignment of switches and LED lights to the FPGA pins. The table below shows which FPGA pin is connected to what on the FPGA board. The FPGA chip pin assignment is from the Digilent web site where red entries indicate the pins usable by students this semester : Pin # Name Pin # Name Pin # Name Pin # Name Pin # Name Pin # Name 1 GND 15 PWT 29 O1 43 GND 57 BTN3 71 DIN (O5) 2 Vdd 16 PD5 30 M1_NC 44 A1 58 BTN2 72 DOUT (RXD) 3 PWE 17 PD7 31 GND 45 CG 59 BTN1 73 CCLK 4 PD0 18 PD6 32 MODE 46 CF 60 LD8 74 Vdd 5 PD1 19 SW8 33 Vdd 47 CE 61 LD7 75 TXD (PINT) 6 PD2 20 SW7 34 M2_NC 48 CD 62 LD6 76 GND 7 PD3 21 GND 35 CLK2 49 CC 63 Vdd 77 R 8 PD4 22 Vdd 36 O2 50 CB 64 GND 78 G 9 PAS 23 SW6 37 O3 51 CA 65 LD5 79 B 10 PRS 24 SW5 38 A4 52 GND 66 LD4 80 HS 11 Vdd 25 SW4 39 A3 53 DONE 67 LD3 81 VS 12 GND 26 SW3 40 A2 54 Vdd 68 LD2 82 PS2C 13 CLK1 27 SW2 41 INIT (O4) 55 PROG 69 LD1 83 PS2D 14 PDS 28 SW1 42 Vdd 56 BTN4 70 LDG 84 PINT 2.3. Modify Step of the Cycle on Breadboards with FPGA Chips If an output does not match your expected result, you will need to modify the circuit on the breadboard. However, in our case, no circuit on the FPGA board will be modifiable. Therefore, our only choice is going back to the schematic design to correct it : Modify the schematic design on the computer if errors are encountered. That is, modify the schematic design. Perform the test (functional simulation) step of the development cycle on computers step. If the results are correct, do a Xilinx IMPLEMENTATION, download the bit file and continue with testing. 3. Industry Schematic Design Practices Students are suggested that they study the three documents at the course web site, describing the Digilent FPGA board. For example, one of the documents is the Schematic diagram of the board. This is mentioned here to emphasize to the students that what is learned in CS2204 is what is practiced in engineering. That is, all our schematic design conventions, such as wire drawing, component placement, naming, etc. are in fact followed by industry. Polytechnic Institute of NYU Page 8 of 8 CS2204 General - Development Cycle with FPGAs for a New Chip February 1, 2011