Status of ADF System Design October 2002
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1 Status of ADF System Design October 2002 D. Calvet DSM/DAPNIA/SEDI, CEA Saclay Gif-sur-Yvette Cedex
2 Content Analog Splitters ADF board ADF crate Timing card High speed links Test bench Software Short term plans 2 Saclay, 3 October 2002
3 Analog Splitter Cabling of 1 board 80% completed - 1 minor error found: DC/DC converter need to be soldered on other side of PCB due to top/bottom view inversion Test of prototype scheduled for October - Need BLS/CTFE style cables: some short (~10cm) some ~5 m - 3 other boards to cable - will be done internally or not? Still on schedule for installation in D0 during 2003 shutdown (February?) even if a second iteration of design/pcb/cabling is necessary calvet@hep.saclay.cea.fr 3 Saclay, 3 October 2002
4 ADF Board Core FPGA (digital filter) VHDL coding 100% completed and simulated 8 channels synthetized, fitted in XC2V500 FG456-4 Post-route simulation done VME interface and bootstrap interface VHDL coding 100% completed and simulated Programmable logic fitted in XC9572XL 10 TQ100C CPLD Post-route simulation done Board-level VHDL simulation Includes 4 FPGA s + VME interface + bootstrap logic Just started for behavioral model; must have a more powerful PC for post-route simulations (1Gbyte RAM min.) Need some control software to exercice the VHDL model calvet@hep.saclay.cea.fr 4 Saclay, 3 October 2002
5 VME BUS VME interface and bootstrap logic AM DS1*-DS0* AS* DTACK* WRITE* A23-A1 D15-D0 XC17S05 SPROM CY7C960A VME Slave Interface 74 LVC ABT LVC 245 Slot ID 5-0 A23-A16 D15-D8 JTAG XC9572 CPLD PROG_B0..3 C_CS_B0..3 C_RD_WR* C_CLK INIT_B DONE BUSY CS0*-CS3* A15-A2 LACK* DBE3-DBE0 D15-D0 WR/RD* Digital Filter FPGA s Download FPGA configuration via VME: - all 4 FPGA s loaded at once or different config on each FPGA VME interface A24 D16-D8 only; no DMA; no interrupt Provides 5V <-> 3.3V conversion; Virtex 2 I/O not 5V tolerant calvet@hep.saclay.cea.fr 5 Saclay, 3 October 2002
6 ADF Crate Custom backplane 20 ADF boards VME Interface VME64 backplane ADF Board (6U) J1 J0 J2 1timing cable 60 (20?) TABs cables Fan unit Power Supply 320 BLSs cables Rear-side Crate to be delivered ~November 2002 Custom backplane: design not started Right view 6 Saclay, 3 October 2002
7 Custom Backplane External Side: 20 x 16 AMP 8 points connectors option with J0 transition connector Internal Side: 20 VME 160 points connectors Passive backplane; controlled impedance traces Need some mechanics to hold (heavy) cables calvet@hep.saclay.cea.fr 7 Saclay, 3 October 2002
8 Power Estimation FPGA Core 1.5V 3.2 A per ADF board -> converted from +5V with eff.: 1.2 A / board 23 A /crate Logic 3.3 V 0.75 A per board -> converted from +5V with eff.: 0.6 A / board 12 A /crate ADC 3.3 V 2.8 A per board; 60 A per crate ADC driver 5 V 0.6 A per board; 12 A per crate Crate requirement: +5V 45A; +3.3V 60A; -5V 12A calvet@hep.saclay.cea.fr 8 Saclay, 3 October 2002
9 J1 Timing Card J2 PROM configuration FPGA logic SCL Receiver Mezzanine (Arizona U.) HM 2 mm connector 4-6 Cables to ADF crate SCL Fiber/Cable VHDL design in progress 3U or 6U mechanics; No slow control Baseline: segmentation 0.2 x 0.2 No slot available in ADF crate: back of slot 0? Space in TAB crate? calvet@hep.saclay.cea.fr 9 Saclay, 3 October 2002
10 High Speed links Use 36 bit out of 48 available in Channel Link 32 data bit 1 start of frame bit (active when LSB s of data are present) 1 indicator of frame length (8 bit or 10 bit) Normal operation: 8 bit frames (digital filter output) If L1 trigger and send raw data enabled: burst of N frames of 10 bit (raw ADC samples for that trigger) 1 BX count Normal operation: counter from SCL; 1 to 159 When sending raw ADC samples: send BX Count and Turn Count 1 parity bit Operating mode of channel link? DC balanced or not? Deskew? Cable: HM 2mm 8 or 10 pairs No progress since last report calvet@hep.saclay.cea.fr 10 Saclay, 3 October 2002
11 Test bench ADF board PC PCI/VME Interface Digital I/O Card Evaluation kit FPGA Virtex 2 G Waveform generator Deserializer High Speed cable A D F VME crate V M E Dedicated Mezzanine card Standards items + dedicated mezzanine card(s) Requested summer student for design in > Need PCI/VME interface; EISA/VME unusable (EISA obsolete and not found in PCs for few years) calvet@hep.saclay.cea.fr 11 Saclay, 3 October 2002
12 Software Address map: each ADF crate takes full 16 MB space of VME A24 - need map MB windows of VME A24-D16/08 in PCI space of TCC computer A23 A 19 A18 A17-A16 A15-A13 A12-A0 0 FPGA ID Channel ID Registers & LUT 0 0 Config. PROG_B and CS_B ADF Card ID 0 1 Config. DATA Config. RD_WR_B, CCLK 0 1 Config. INIT_B, DONE, BUSY Compatibility and smooth integration with existing TCC software - OS : Windows NT/2k? Language: C, C++? Tool: Visual Studio? - Libraries: Rogue Wave? STL? Others - Application: multi-threaded? Polling? Some code development started to perform board level simulation calvet@hep.saclay.cea.fr 12 Saclay, 3 October 2002
13 Short Term Plans Test Analog Splitter ~1 week Complete ADF board level simulations ~1 week Design power supply circuit for ADF board FPGA s ~2 weeks Start ADF board schematic capture Begin ~end October at best calvet@hep.saclay.cea.fr 13 Saclay, 3 October 2002
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