ROBIN Functional demonstrator of the ATLAS Trigger / DAQ Read-Out Buffer O.Gachelin, M.Huet, P.Le Dû, M.Mur C.E.A. Saclay - DAPNIA

Transcription

1 1 ROBIN Functional demonstrator of the ATLAS Trigger / DAQ Read-Out Buffer O.Gachelin, M.Huet, P.Le Dû, M.Mur C.E.A. Saclay - DAPNIA

2 2 Basic principles Data flow : output < input including L2 and L3 according to strategy from few % to ~20 % optimisation between Input buffering and Output data request (e.g. Calorimeter vs muons ) sequential processing : C architecture : increase requests decrease data mix control, requests and data try to reduce number of links to switch Group several Inputs on one Output

3 3 Conceptual Architecture One buffer per input link Input rate = 1 Gbit/s large and fast memory with intermediate Fifo Local fast data collector bus 1 Gbit/s Local intelligence decode requests prepare data transmission preprocessing if necessary 132 MByte/s ROBin ROBin ROBin ROBin Bi-directionnal downstream link receive requests send RoI data fragment (L2) Event data ( Filter ) Local Intelligence Downstream Link

4 4 Today Implementation ROB backbone on VME board CES - RIO2 PPC 604 DRAM Local Intelligence CPU on board Bridge Ethernet VME Bridge Inputs & buffers Network Port PMC boards Output ATM Port on PMC PMC#2 ROBin Data generator Some limitations Port number Power Possibility to extend port number with extension boards serial ROL ROL serial to parallel PMC#1 input data port FIFO Main Buffer Logic TTC & L1 Interface bridge CPU + Memory

5 5 Implementation -> Next step Compact based ROB backbone Crate Local Intelligence CPU board (Ex : RIOC) Inputs & buffers Output ROBin boards ATM Port possibility to adapt PMCs in Compact up to 8 slots without additionnal bridge To be purchased for end of 97

6 6 Short history of the project C80 implementation investigated on commercial board dual port VRAM memory 2 CPU possibility to connect input ports on links drawback very long delay ~ 1.5 year more additionnal electronics than foreseen available Cracow (April) -> new approach concept presented Balaton ( September ) pre design ( Balatonfüred September 23-27, 1996 ; p 204 ) 1997 Design Difficulties : PMC design CPU knowledge VHDL description components supplying few board space low power very flat package small quantities

7 7 ROBin present design PMC format Input Port 32 bits // Event Buffer Fifo 64 kb FPGA type MACH on site programming with JTAG port (through PLX9080) Local Memory 512KB FPGAs Local Memory Event Memory & Control Event Buffer Control Bus Arbitration Event Memory 4 MB jtag Local Bus 33Mhz not used RP -> BGA JD -> Power increase CPU i960jf Bridge PLX9080 eeprom bridge cicular message queue eprom : on site programming

8 8 Two steps Input Port 32 bits // PMC format Version 1 Event Buffer Fifo 64 kb Version 2 Local Memory 512KB FPGAs Local Memory Event Memory & Control Event Buffer Control Bus Arbitration Event Memory 4 MB jtag Local Bus 33Mhz CPU i960jf Bridge PLX9080 eeprom

9 9 Planning Step 1 Schematics : end of October CAO : components description placement started board cabling : foreseen during december Step 2 foreseen 4/98 Present cost Estimated future cost ~ 7000 FF few pieces ~ 5000 FF large series

10 10 Software tools No OS and No communication port in ROBin Local Monitor downloaded in SRAM Remote Monitor for Host delivered by intel for i960 family connected to local monitor through Ctools compiler linker Board debugging on PMC carrier located in a slot on PC Remote Monitor to be translated on RIO-CES/LynxOS

11 11 In parallel, 2 boards have been purchased and are in use. * board with i960rp * PMC board equipped with SHARC Transtech ASP-C2

12 12 i960 evaluation evaluation board with intel960 Cyclone IQ-SDK familiarize with : intel tools pci protocol ROBin circular message queue for request transmission ROBin DMA for data sending to Host in PC environment DRAM 2 MB Console Port Local Bus i960rp CPU + Bridge Secondary flash rom i960rp 2 M DRAM monitor in rom DMA on both s Primary

13 13 ROBin emulation PMC Transtech ASP-C SHARC M DRAM 6 * 40M Bytes/s links 40 MHz Bus Bridge FIFOs DRAM Flash ROM emulate ROBin in Demonstrator real data flow on Driver to be converted for LynxOS