Using the SPECS in LHCb

Transcription

1 LHCb DAQ 21 January 2003 Using the in LHCb Dominique Breton, Daniel Charlet Laboratoire de l Accélérateur Linéaire - Orsay ABSTRACT This document attempts to describe how to use the in LHCb. The technical specifications of the bus itself are given in another document [1]. This note presents how the can be interfaced with the various sub-systems. Contact : charlet@lal.in2p3.fr, breton@lal.in2p3.fr

2 Page 2 Using the in LHCb LHCb

3 LHCb Using the in LHCb Page 3 1 Context The has been designed to allow control of the front-end electronics of LHCb. The system mostly consists of three elements : a bus master located on a PCI board in the counting rooms (see fig 1), a in the cavern, delivering JTAG, I2C and a parallel interface to control the electronics, and dedicated software to drive the system from the PVSS II SCADA environment upon which the LHCb ECS system is built. The board housing the masters is shown on fig 1. It s a PCI board providing 4 outputs. Two of them are mixed, which allows the users to drive JTAG or I2C directly from their PC for test bench purpose (for instance). As a is integrated within the board, the system behaves like the expanded one. In particular, the software is identical. On the first prototype of the board, the mixed outputs won t provide. or JTAG LVDS bus or I2C LVDS bus LVDS bus LVDS bus Firmware version 2.0 LVDS drivers LVDS drivers bus LVDS drivers LVDS drivers 4 Masters + 1 Slave APEX 20K200E PQFP 240 PCI target interface PLX 9030 PQFP 176 PCI connector PLX local bus PCI bus PCI Master board PC mother board Fig 1 : the PCI master board. The technicalities of the protocol between master and (s) are described in ref[1] and are not too relevant here. The main discussion concerns indeed the location of the, and the types of bus it can deliver. The will be designed as a portable Verilog code and physically integrated in an ACTEL anti-fuse PGA. With this technology, the is SEU immune, provided the internal registers are appropriately protected by triple voting techniques, and states machines use one-hot state. It is also reasonably radiation tolerant, up to 10 krads (with some safety factor, the ACTEL having been tested up to 40 krads) over the lifetime of the experiment. It can then be placed at most locations where we foresee to have electronics, but not in or near the Velo tank. Fig 2 shows the block diagram of the s interconnections. It may also be envisaged by users to use the Verilog code as a block within a bigger Actel FPGA. As shown on fig 2, the bus is bi-directional, two electrical pairs being dedicated to each direction. On the top side, one can find the different control signals necessary for a proper functioning. On the right side, the parallel I/Os are represented. Finally, the bottom side describes the JTAG and I2C I/Os. It s also envisaged to allow the user to ask for a replacement of the parallel bus if unused by other JTAG or I2C outputs, or maybe even to customize all the outputs depending on the requirements from the host board.

4 Page 4 Using the in LHCb LHCb PBA [3:0] (Partial Broadcast Address) Slave Address 40 MHz Clk [7:0] Reset* User s Interrupt SDA_MS SCL_MS SDA_SM SCL_SM Actel 54SX?? Data[7:0] Subadd[7:0] Read* Write* SerialOutEnable ChipSelect*[7:0] NTA[15:0] Byte number[3:0] JTAG (TMS, TCK, TDI, TRST) JTAG (TDO) I2C I2C (SDAreturn, (SDA, SCLreturn) SCL) Fig 2 : the. 2 Direct implementation of the. The simplest way to use the is to place the FPGA on the board one wants to control. This gives direct access to JTAG and I2C, together with the parallel bus. One needs to provide the 40 MHz clock (from TTCrx) and to specify the personal and the group broadcast addresses of the by jumpers for instance. A connector is defined as standard to receive the signal from the master and send it back thereto (see fig 3). Differential to TTL MS_SDA bus (4 diff pairs) from master (up to 100m) RJ 45 MS_SCL SM_SDA SM_SCL Fig 3 : standard interconnection.

5 LHCb Using the in LHCb Page 5 As the same master can drive several s (up to 240 different addresses), the bus may be daisy-chained locally. Be careful anyway not to drive too many s with the same physical bus to avoid loading the lines too heavily for obvious signal integrity reasons (32 sounds like a reasonable limit). Impedance adaptation should also be provided at the extremities of the bus. If the master is located far from the s zone, a repeater has to be implemented in the latter (see fig 4). This may imply the use of removable arrays of resistors, to be put on the board for the termination adaptation. Remote bus Long distance differential MS_SDA MS_SCL SM_SDA SM_SCL master Diff to TTL Up to 240 addresses Diff repeater Fig 4 : remote bus implementation. The advantage of this method is simplicity. This is the solution we intend to use in the calorimeter. The bus will actually be distributed on the backplane by the so-called Crate Controller board, which also distributes the TTC signals to all the boards in the crate. This allows us to ensure a perfect integrity to the signals. This dedicated backplane already exists, and is available for use by other detectors. (See ref[2]) 3 Implementation using only JTAG or I2C. In this solution, an intermediate board (6U VME), provided by LAL-Orsay, contains the s, and provides JTAG and I2C connections on its front panel (see Fig 5). The user board needs a connector for either JTAG or I2C input, with the proper cabling as described on fig 6. The system is seen in this case as a JTAG or I2C provider, and its internals can be completely ignored. This option is mandatory for boards situated in high radiation areas, like the Velo on detector boards, for it isn t possible to put the FPGA at these locations. Please notice that on fig 6, both remote SDA and SCL have to be sent back to the board to allow a proper sampling, which actually does not depend on the length of the I2C cable.

6 Page 6 Using the in LHCb LHCb Front panel connector BACKPLANE CONNECTOR + TTC MS_SDA MS_SCL SM_SDA SM-SCL SLAVE I2C Bus JTAG Bus Actel 54SX?? en[7] en[0] JTAG or I2C Bus En JTAG or I2C DIFFERENTIAL LINK 8BUSSES SLAVE BOARD En JTAG or I2C DIFFERENTIAL LINK Fig 5 : board. There are two ways to deliver the bus to the boards : either using the lines of the standard calorimeter backplane (see ref [2]) if the required overall crate data bandwidth does not exceed 1MByte/s, or using a dedicated connector on the board s front panel otherwise. These configurations (more detailed in ref[1]) will be selectable thanks to straps located on the board. PECL/LVDS differential adapted lines Rad «OK» COTS SCL board I2C interface JTAG interface connectors OC SDA TDI TMS TCK TDO On detector Remote board Cat5 cables 26LS32 or DS92LV040 10H116D or DS92LV040 Fig 6 : to detector electronics cabling.

7 LHCb Using the in LHCb Page 7 4 Different sub-detector implementations. The implementations of the system vary depending on the sub-detector. Possible solutions based on our current understanding of the subsystems are shown below. It s anyhow very likely that some evolutions already occurred, which may make them obsolete. Please react thereto rapidly, to allow us to update this documentation! Fig 7 : VELO/Inner Tracker possible implementation.

8 Page 8 Using the in LHCb LHCb Baracks 100m Safety tunnel Detector Specs protocol Cat5 cable 4pairsLVDS TTC link Crate "controler" Commercial Line drivers Specs 25 Concentrator Crates 20 boards TTC distribution GTL+/LVDS Specs bus Jtag + data 4000 TDC boards TDC board (1kb) ASDBR Patch Pannel 1000 Analog Treshold DAC Crate -> I2C crate Fig 8 : Outer Tracker possible implementation. Counting Room PCI2Specs boards PC 11 Links (or 1? ) 17 Links (or 1? ) Beside the wall L0 electronic 6U Crate on the top of the detector and on the floor 100m 11 boards 100-1k rad/y 17 boards 100 rad/y Detector 10 m 84 adaptor boards on RICH1 I2C 136 adaptor boards on the RICH2 I2C Pilot TTCrx Pilot TTCrx Pilot TTCrx Pilot TTCrx 3Krad/y 3Krad/y Fig 9 : Rich possible implementation.

9 LHCb Using the in LHCb Page 9 Baracks 100m Top of detector Cat5 cable 4 pairs LVDS/PECL protocol TTC link Commercial Line drivers Point to point distribution Clock GTL+/LVDS Specs bus Specs 21 boards Crate "Controller" Fig 10 : Calorimeter implementation. 5 References [1] Serial Protocol for the Experiment Control System of LHCb, Version 2.0, D.Breton and D.Charlet, LHCb note [2] Powerpoint presentation of D.Charlet about the common calorimeter backplane at the calorimeter electronics review, July 2002,