RZ/A1H Group. Application Note. SSI Sample Program. Introduction. Target Devices. R01AN2076EJ0101 Rev Jul. 16, 2014

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1 Application Note RZ/A1H Group R01AN2076EJ0101 Rev.1.01 Introduction This application note describes a sample program for full-duplex communication with an audio codec (WM8978) through the use of the serial sound interface (hereinafter referred to as SSI) function of RZ/A1H. The features of the SSI program are as follows: - It sets SSI to master transceiver mode to establish full-duplex communication with an audio codec (WM8978). - It provides an example of starting and stopping playback by switching the operation of SSI (starting and stopping operation) every five seconds. Target Devices RZ/A1H Group When applying the sample program covered in this application note to another microcomputer, modify the program according to the specifications for the target microcomputer and conduct an extensive evaluation of the modified program. R01AN2076EJ0101 Rev.1.01 Page 1 of 63

2 Contents 1. Specifications Operation Check Conditions Related Application Note Peripheral Functions Description of Hardware Hardware Configuration List of Pins to Be Used Software Description Operation Outline Memory Mappings Allocation of Sample Program Sections MMU Settings Interrupts Basic Data Types List of Constants/Error Codes List of Structures/Unions List of Variables List of Functions Function Specifications R_SSI_RamInit R_SSI_SsiInit R_SSI_DmaInit R_SSI_SsiStart R_SSI_DmaStart R_SSI_SsiStop R_SSI_SsiDmaStop R_SSI_SsiDmaAdsSet Flowcharts Main Processing Main Processing (during SSI Operation) Main Processing (Stopping SSI) Main Processing (Resuming SSI) DMA Transfer End Interrupt Processing OS Timer Interrupt Processing Initialization of SSI Control Information SSI Initialization DMAC Initialization SSI Activation DMAC Activation SSI Termination Termination of SSI Transmission and Reception Buffer Registration SSI Error Interrupt Processing Initialization of DMA Control Information Queue Initialization Queue Setup Enabling of DMA Transfer Termination of DMA Transfer Initialization of DMA (Buffer -> SSI) Update of DMA Transfer Source Addresses R01AN2076EJ0101 Rev.1.01 Page 2 of 63

3 Initialization of DMA (SSI -> Buffer) Update of DMA Transfer Destination Addresses Termination of DMA Transfer Sample Code Documents for Reference R01AN2076EJ0101 Rev.1.01 Page 3 of 63

4 1. Specifications Table 1.1 lists the peripheral functions to be used and their uses. Table 1.1 Peripheral Functions to Be Used and Their Uses Peripheral functions SSI channel 0 INTC (Interrupt ID: 172) INTC (Interrupt ID: 41) INTC (Interrupt ID: 42) INTC (Interrupt ID: 135) DMAC channel 0 DMAC channel 1 OSTM channel 1 RSPI channel 4 Uses SSI transmission and reception SSI error (transmission underflow error, reception overflow error) detection DMA transfer end (SSI -> buffer) detection DMA transfer end (buffer -> SSI) detection Timing generation for switching operation to stop playback Audio data transfer (SSI -> buffer) Audio data transfer (buffer -> SSI) For time measurement for switching operation to start and stop playback Audio codec (WM8978) control R01AN2076EJ0101 Rev.1.01 Page 4 of 63

5 2. Operation Check Conditions The operation of the sample code covered in this application note is checked under the following conditions: Table 2.1 Operation Check Conditions Item Description Microcomputer used RZ/A1H Operating frequency [MHz] CPU Clock(Iφ): 400 MHz Image processing clock(gφ): MHz Internal Bus Clock(Bφ): MHz Peripheral Clock(P1φ): MHz Peripheral Clock(P0φ): MHz Operating voltage Power-supply voltage(i/o): 3.3 V Power-supply voltage (internal): 1.18 V Integrated development ARM integrated development environment environment ARM Development Studio 5 (DS-5TM) Version 5.16 C compiler ARM C/C++ Compiler/Linker/Assembler Ver.5.03 [Build102] Compiler options (excluding addition of directory paths) -O3 -Ospace --cpu=cortex-a9 --littleend arm --no_unaligned_access -g --asm --no_autoinline -c Operating mode Boot mode 0 (CS0 space 16-bit boot) Board to be used R7S72100 CPU board: RTK772100BC00000BR Device used (functionality to be used on the board) <R7S72100 CPU board: on RTK772100BC00000BR> - Functional setting of the DIP switch SW2-2 for system configuration: ON (P4_[7:4] is used as the SSIF pin.) - Jumper JP10: 1-2 short (P4_1 is used as the SSL40 output pin.) R01AN2076EJ0101 Rev.1.01 Page 5 of 63

6 3. Related Application Note The application notes related to this application note are listed below for reference. RZ/A1H Group Initialization Example (R01AN1864EJ) RZ/A1H Group Register Definition Header File iodefine.h (R01AN1860EJ) RZ/A1HGroup Renesas Serial Peripheral Interface EEPROM Read/Write Example (R01AN1806EJ) R01AN2076EJ0101 Rev.1.01 Page 6 of 63

7 4. Peripheral Functions The information about the basics of SSIF, DMAC, INTC, RSPI and OSTM is found in "RZ/A1H Group User's Manual Hardware." R01AN2076EJ0101 Rev.1.01 Page 7 of 63

8 5. Description of Hardware 5.1 Hardware Configuration Figure 5.1 gives an example of Hardware Configuration RZ/A1H SSI SSISCK MHz AUDIO_X1 SSIWS0 SSIRxD0 R Flash Memory Large-capacity On-chip RAM RSPI SSITxD0 RSPCK4 MOSI4 SSL40 Audio Codec (WM8978) Figure 5.1 Example of Hardware Configuration 5.2 List of Pins to Be Used Table 5.1 lists Pins to Be Used and Their Functions. Table 5.1 Pins to Be Used and Their Functions Pin name I/O Description AUDIO_CLK Input Not used. AUDIO_X1 Input Oversampling clock input. AUDIO_X2 Output Not used. SSISCK0 Output Serial bit clock. SSIWS0 Output Word selection. SSITxD0 Output Serial data output. SSIRxD0 Input Serial data input. RSPCK4 Output Clock output. MOSI4 Output Master transmission data. SSL40 Output Slave select R01AN2076EJ0101 Rev.1.01 Page 8 of 63

9 6. Software Description 6.1 Operation Outline Figure 6.1 shows a schematic diagram of operation of the sample code. Audio data received from the SSIRxD0 pin is transferred to the reception FIFO data register (SSIFRDR) via the reception data register (SSIRDR) of SSI channel 0. After the data is transferred to the SSIFRDR register, SSI activates DMAC channel 0 by using a DMAC transfer request made through a received-data-full interrupt. A buffer (large-capacity on-chip RAM) for 441 samples (1764 bytes) is configured as the transfer destination of DMAC channel 0. The buffer has four sides and successively receives data by switching between the sides each time a DMA transfer is completed. A DMAC transfer request made through a transmitted-data-empty interrupt of SSI is used to activate DMAC channel 1 to transfer audio data stored in a buffer (large-capacity on-chip RAM) to the transmission FIFO data register (SSIFTDR) of SSI channel 0. The data that has been transferred to the SSIFTDR register is transferred to the the transmission data register (SSITDR) when it is detected that the SSITDR register is empty, and then it is output from the SSITxD0 pin. Each time a transfer of data from one buffer side is completed, the buffer is switched to another side to successively transfer data. The full-duplex communication described above is carried out for five seconds, and it is stopped for five seconds. Then, this operation is repeated. Large-capacity on-chip RAM Serial sound interface (SSI) Lch Rch Channel 0(transmission) DMAC (Channel 1) SSITxD0 Audio data Lch Rch Audio data received by SSI channel 0 is directly transmitted to SSI channel 0 Buffer 4sides Lch Rch Channel 0(reception) DMAC (Channel 0) Lch Rch SSIRxD0 Audio data Figure 6.1 Overview of Operation R01AN2076EJ0101 Rev.1.01 Page 9 of 63

10 6.2 Memory Mappings Figure 6.2 shows the address spaces of the RZ/A1H group and the memory map of the R7S72100 CPU board RTK772100BC00000BR. In the sample program, code and data that use the ROM area are allocated to the R flash memory connected to the CS0 space, and code and data that use the RAM area are allocated to the large-capacity on-chip RAM. Address spaces of the RZ/A1H group R7S72100 CPU board memory mapping H FFFF FFFF Others (2550 MB) Others (2550 MB) Mirror spaces H 60A H H 5C H Large-capacity on-chip RAM (10MB) SPI multi-i/o-bus space 2 (64 MB) SPI multi-i/o-bus space 1 (64 MB) Large-capacity on-chip RAM mirror space SPI multi-i/o-bus mirror space 2 SPI multi-i/o-bus mirror space 1 CS5 space (64 MB) CS4 space (64 MB) CS5 mirror space CS4 mirror space H H 4C CS3 space (64 MB) CS3 mirror space H CS2 space (64 MB) CS2 mirror space H CS1 space (64 MB) CS1 mirror space H CS0 space (64 MB) CS0 mirror space Others (502 MB) Others (502 MB) H 20A H H 1C H Large-capacity on-chip RAM (10 MB) SPI multi-i/o-bus space 2 (64 MB) SPI multi-i/o-bus space 1 (64 MB) Large-capacity on-chip RAM (10 MB) Serial flash memory (64 MB) Serial flash memory (64MB) Normal spaces CS5 space (64 MB) CS4 space (64 MB) User area H H 0C CS3 space (64 MB) SDRAM (64 MB) H H H CS2 space (64 MB) CS1 space (64 MB) CS0 space (64 MB) SDRAM (64 MB) R flash memory (64 MB) R flash memory (64 MB) Figure 6.2 Memory Map R01AN2076EJ0101 Rev.1.01 Page 10 of 63

11 6.2.1 Allocation of Sample Program Sections In the sample program, in order to ensure the high-speed handling of interrupts, the exception handling vector table and the IRQ interrupt handler are allocated to the large-capacity on-chip RAM to operate these on the large-capacity on-chip RAM. A scatter loading function is used to perform the following: transferring data from R flash memory areas for the exception handling vector table and for the program code of the IRQ interrupt handler to the large-capacity on-chip RAM; clearing, to 0, data sections that do not have initial values; and initializing data sections that have initial values. For details of the scatter loading function, refer to the chapter of Image Structure and Generation in Using the Linker in ARM Compiler toolchain, which is provided by ARM. Table 6.1 and Table 6.2 show the sections used in the sample program, and Figure 6.3 shows the initial allocation of sections (load view) of the sample program, and the allocation of the sections after the use of the scatter loading function (execution view). R01AN2076EJ0101 Rev.1.01 Page 11 of 63

12 Table 6.1 Sections to Be Used (1/2) Area Name Description Type Load Area Execution Area VECTOR_TABLE Exception handling vector table. Code FLASH FLASH RESET_HANDLER Program code area for reset handler operation. This area consists of the following sections. - INITCA9CACHE (L1 cache setting) - INIT_TTB (MMU setting) - RESET_HANDLER (reset handler) Code FLASH FLASH CODE_BASIC_SETUP Program code area for operating frequencies and flash memory optimization. Code FLASH FLASH InRoot CODE_FPU_INIT CODE_RESET CODE_IO_REGRW CODE CONST This area consists of sections allocated to the root area, such as the standard C library. Program code area for initialization of NEON and VFP. This area consists of the following sections. - CODE_FPU_INIT - FPU_INIT Program code area for hardware initialization. This area consists of the following sections. - CODE_RESET (start-up operation) - INIT_VBAR (vector base setting) Program code area for read/write functions for IO registers. Default program code area. All sections of code types with section names that are not defined in C sources are allocated to this area. Default constant data area. All sections of RO data types with section names that are not defined in C sources are allocated to this area. Code and RO Data FLASH FLASH Code FLASH FLASH Code FLASH FLASH Code FLASH FLASH Code FLASH FLASH RO Data FLASH FLASH R01AN2076EJ0101 Rev.1.01 Page 12 of 63

13 Table 6.2 Sections to Be Used (2/2) Area Name Description Type Load Area Execution Area VECTOR_MIRROR_ TABLE CODE_HANDLER_ JMPTBL CODE_HANDLER DATA_HANDLER_ JMPTBL Exception handling vector table. (Section for transfer to and execution on the large-capacity on-chip RAM) Program code area for user-defined functions of the IRQ interrupt handler. Program code area for the IRQ interrupt handler. This area consists of the following sections. - CODE_HANDLER - IRQ_FIQ_HANDLER Registration table data area for user-defined functions of the IRQ interrupt handler. Code FLASH LRAM Code FLASH LRAM Code FLASH LRAM RW Data FLASH LRAM ARM_LIB_STACK Application stack area. ZI Data - LRAM IRQ_STACK IRQ mode stack area. ZI Data - LRAM FIQ_STACK FIQ mode stack area. ZI Data - LRAM SVC_STACK Supervisor (SVC) mode stack area. ZI Data - LRAM ABT_STACK Abort (ABT) mode stack area. ZI Data - LRAM TTB MMU conversion table area. ZI Data - LRAM ARM_LIB_HEAP Application heap area. ZI Data - LRAM DATA Area for data with default initial values. RW Data FLASH LRAM All sections of RW data types with section names that are not defined in C sources are allocated to this area. BSS Area for data without default initial values. All sections of ZI data types with section names that are not defined in C sources are allocated to this area. ZI Data - LRAM BSS_AUDIO_OUT_BUF Section that stores audio data. ZI Data - LRAM [Note] 1. In load areas and execution areas described in the table, FLASH and LRAM denote areas for the R flash memory and the large-capacity on-chip RAM, respectively. [Note] 2. The names of sections are basically the same as those of their respective areas; however, RESET_HANDLER, InRoot, CODE_FPU_INIT, CODE_RESET, CODE, CONST, CODE_HANDLER, DATA, and BSS each consist of multiple sections. For details of areas and sections, refer to manuals of ARM Compiler toolchain. R01AN2076EJ0101 Rev.1.01 Page 13 of 63

14 H'FFFF FFFF RZ/A1H group address space H'609F FFFF Section arrangement (load view) Memory allocation after scatter loading Section arrangement (execution view) H'60A H' Large-capacity onchip RAM (10MB) H' H' Clear to 0 BSS_AUDIO_OUT_BUF H' H'209F FFFF Clear to 0 H'200B 8000 Initialize data that have initial values. BSS DATA H' H' H' H' H'2002 E000 H'2002 C000 H' Obtain areas for stacks and the like. Initialize data that have initial values. ARM_LIB_HEAP TTB ABT_STACK SVC_STACK FIQ_STAC IRQ_STACK ARM_LIB_STACK DATA_HANDLER_JMPTBL CODE_HANDLER H' CODE_HANDLER_JMPTBL H' VECTOR_MIRROR_TABLE H' H'03FF FFFF H' DATA DATA_HANDLER_JMPTBL H'20A H' H'1C H' H' Large-capacity onchip RAM (10MB) CODE_HANDLER CODE_HANDLER_JMPTBL CONST CODE CODE_IO_REGRW CODE_RESET CODE_FPU_INIT InRoot Transfer program code that requires high-speed processing to the onchip RAM. CONST CODE CODE_IO_REGRW CODE_RESET CODE_FPU_INIT InRoot H'0C H' H' H' CS0space (64MB) H' H' H' CODE_BASIC_SETUP RESER_HANDLER VECTOR_MIRROR_TABLE VECTOR_TABLE Transfer the exception handling vector to the on-chip RAM. CODE_BASIC_SETUP RESER_HANDLER VECTOR_TABLE Figure 6.3 Section Allocation R01AN2076EJ0101 Rev.1.01 Page 14 of 63

15 6.2.2 MMU Settings The MMU is set to manage 4 GB of memory, starting at address H , in 1-MB units according to the memory mappings for the hardware resources for RZ/A1H7S72100 CPU board RTK772100BC00000BR (the MMU settings are configured in the ttb_init.s file). When this memory area is customized for your system, the minimum unit should be 1 MB. Table 6.3 shows the MMU Settings for the sample program. Table 6.3 MMU Settings Definition name Description Address Size Memory type M_SIZE_R CS0 and CS1 spaces (R flash memory) H to H 07FFFFFF 128MB Normal memory with L1 cache enabled M_SIZE_SDRAM CS2 and CS3 spaces (SDRAM) H to H 0FFFFFFF M_SIZE_CS45 CS4 and CS5 spaces H to H 17FFFFFF M_SIZE_SPI SPI multi-io-bus spaces 1 and 2 M_SIZE_RAM M_SIZE_IO_1 Large-capacity on-chip RAM space On-chip peripheral module and reserved area H to H 17FFFFFF H to H 209FFFFF H 20A00000 to H 3FFFFFFF M_SIZE_R_M CS0 and CS1 mirror spaces H to H 47FFFFFF M_SIZE_SDRAM_M CS2 and CS3 mirror spaces H to H 4FFFFFFF M_SIZE_CS45_M CS4 and CS5 mirror spaces H to H 57FFFFFF M_SIZE_SPI_M M_SIZE_RAM_M M_SIZE_IO_2 SPI multi-io-bus mirror spaces 1 and 2 Large-capacity on-chip RAM mirror space Mirror spaces for both on-chip peripheral module and reserved area H to H 57FFFFFF H to H 609FFFFF H 60A00000 to H 7FFFFFFF 128MB 128MB 128MB 10MB 502MB 128MB 128MB 128MB 128MB 10MB 2550MB Normal memory with L1 cache enabled Strong reorder memory with L1 cache disabled Normal memory with L1 cache enabled Normal memory with L1 cache enabled Strong reorder memory with L1 cache disabled Normal memory with L1 cache disabled Normal memory with L1 cache disabled Strong reorder memory with L1 cache disabled Normal memory with L1 cache disabled Normal memory with L1 cache disabled Strong reorder memory with L1 cache disabled R01AN2076EJ0101 Rev.1.01 Page 15 of 63

16 6.3 Interrupts Table 6.4 shows interrupts for the sample code. Table 6.4 Interrupts for the Sample Code Interrupt (factor ID) Priority Process Outline SSII0 (172) 4 When a SSI error (transmission underflow error, reception overflow error) is detected, this interrupt occurs. It is used to perform a soft reset of the SSI module to reset SSI. After that, SSI transmission and reception operations are performed. DMAINT0 (41) 5 When an audio data transfer is completed (SSI -> buffer), this interrupt occurs. The period is about 10 ms, and this interrupt is used to assign the start address of the next buffer to the DMAC destination address register. DMAINT1 (42) 5 When an audio data transfer is completed (buffer -> SSI), this interrupt occurs. The period is about 10 ms, and this interrupt is used to assign the start address of the next buffer to the DMAC source address register. OSTMI1 (135) 6 This interrupt occurs every five seconds. It is used as a trigger to stop playback. R01AN2076EJ0101 Rev.1.01 Page 16 of 63

17 6.4 Basic Data Types Table 6.5 shows basic data types for the sample code. Table 6.5 Basic Data Types for the Sample Code Symbol Description char_t 8-bit character bool_t Logical data type. The value is true (= 1) or false (= 0). int_t Signed integer for high-speed operation. The signed integer for this sample code is a 32-bit integer. int8_t 8-bit signed integer int16_t 16-bit signed integer int32_t 32-bit signed integer int64_t 64-bit signed integer uint8_t 8-bit unsigned integer uint16_t 16-bit unsigned integer uint32_t 32-bit unsigned integer uint64_t 64-bit unsigned integer float32_t 32-bit floating point float64_t 64-bit floating point float128_t 128-bit floating point R01AN2076EJ0101 Rev.1.01 Page 17 of 63

18 6.5 List of Constants/Error Codes Table 6.6 to Table 6.11 list constants used in the sample program, and Table 6.12 lists error codes of the sample program. Table 6.6 Constants for the Sample Code (1) Constant Setting Description AUDIO_BUFF_SIZE 1764 Audio buffer byte size. SAMPLE_MODE_IDLE 0 Idle state. SAMPLE_MODE_PLAY 1 Playback state. SAMPLE_MODE_MAX 2 Number of states. SAMPLE_EVENT_OFF 0 Timer events are disabled. SAMPLE_EVENT_ON 1 Timer events are enabled. SAMPLE_EVENT_MAX 2 Number of timer events. SSI_CHANNEL0 0 SSI Channel 0. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL1 1 SSI Channel 1. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL2 2 SSI Channel 2. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL3 3 SSI Channel 3. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL4 4 SSI Channel 4. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL5 5 SSI Channel 5. This constant is used to specify the SSI channel number to be used. SSI_CHANNEL_MAX 6 Number of SSI channels. SSI_RX 1 SSI reception (SSI -> buffer) operation. This constant is used to choose SSI reception operation. SSI_TX 2 SSI transmission (buffer -> SSI) operation. This constant is used to choose SSI transmission operation. SSI_FULLDUPLEX 3 SSI full-duplex operation. This constant is used to choose SSI full-duplex operation. SSI_ID_SSII0 172 SSI channel 0 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. SSI_ID_SSII1 175 SSI channel 1 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. SSI_ID_SSII2 178 SSI channel 2 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. SSI_ID_SSII3 180 SSI channel 3 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. R01AN2076EJ0101 Rev.1.01 Page 18 of 63

19 Table 6.7 Constants for the Sample Code (2) Constant Setting Description SSI_ID_SSII4 183 SSI channel 4 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. SSI_ID_SSII5 185 SSI channel 5 interrupt ID. This constant is used to specify the SSI interrupt ID to be used. SSI_SSICR_TUIEN_INIT_VALUE H The initial setting of the TUIEN bit of a SSI control register. (Transmission underflow interrupt is disabled.) SSI_SSICR_TOIEN_INIT_VALUE H The initial setting of the TOIEN bit of a SSI control register. (Transmission overflow interrupt is disabled.) SSI_SSICR_RUIEN_INIT_VALUE H The initial setting of the RUIEN bit of a SSI control register. (Reception underflow interrupt is disabled.) SSI_SSICR_ROIEN_INIT_VALUE H The initial setting of the ROIEN bit of a SSI control register. (Reception overflow interrupt is disabled.) SSI_SSICR_IIEN_INIT_VALUE H The initial setting of the IIEN bit of a SSI control register. (Idle mode interrupt is disabled.) SSI_SSICR_MUEN_INIT_VALUE H The initial setting of the MUEN bit of a SSI control register. (Not in a mute state.) SSI_SSICR_TEN_INIT_VALUE H The initial setting of the TEN bit of a SSI control register. (Transmission operation is disabled.) SSI_SSICR_REN_INIT_VALUE H The initial setting of the REN bit of a SSI control register. (Reception operation is disabled.) SSI_SSICR0_CKS_VALUE H The setting of the CKS bit of the SSI channel 0 control register. (Oversampling clock: AUDIO_X1) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_CHNL_VALUE H The setting of the CHNL bit of the SSI channel 0 control register. (Channel: Each system word consists of one channel.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_DWL_VALUE H The setting of the DWL bit of the SSI channel 0 control register. (Data word length: 16 bits) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SWL_VALUE H The setting of the SWL bit of the SSI channel 0 control register. (System word length: 32 bits) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SCKD_VALUE H The setting of the SCKD bit of the SSI channel 0 control register. (Serial bit clock direction: master mode) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SWSD_VALUE H The setting of the SWSD bit of the SSI channel 0 control register. (Serial WS direction: master mode) This setting is defined in drv_ssif_user.h. Change it as necessary. R01AN2076EJ0101 Rev.1.01 Page 19 of 63

20 Table 6.8 Constants for the Sample Code (3) Constant Setting Description SSI_SSICR0_SCKP_VALUE H The setting of the SCKP bit of the SSI channel 0 control register. (Serial bit clock polarity: SSIWS and SSIDATA are changed on a falling edge of SSISCK.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SWSP_VALUE H The setting of the SWSP bit of the SSI channel 0 control register. (Serial WS polarity: SSIWS is low level on the 1st channel and high level on the 2nd channel.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SPDP_VALUE H The setting of the SPDP bit of the SSI channel 0 control register. (Serial padding polarity: low level) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_SDTA_VALUE H The setting of the SDTA bit of the SSI channel 0 control register. (Serial data alignment: serial data and padding bits are transmitted and received in this order.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_PDTA_VALUE H The setting of the PDTA bit of the SSI channel 0 control register. (Parallel data alignment: the lower part of parallel data (SSITDR, SSIRDR) is first transmitted and received.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_DEL_VALUE H The setting of the DEL bit of the SSI channel 0 control register. (Serial data delay: a delay of one clock cycle between SSIWS and SSIDATA.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR0_CKDV_VALUE H The setting of the CKDV bit of the SSI channel 0 control register. (Serial oversampling clock division ratio: AUDIOφ/8.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR1_CKS_VALUE H The setting of the CKS bit of the SSI channel 1 control register. (Oversampling clock: AUDIO_X1.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR1_CHNL_VALUE H The setting of the CHNL bit of the SSI channel 1 control register. (Channel: each system word consists of one channel.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR1_DWL_VALUE H The setting of the DWL bit of the SSI channel 1 control register. (Data word length: 16 bits.) This setting is defined in drv_ssif_user.h. Change it as necessary. R01AN2076EJ0101 Rev.1.01 Page 20 of 63

21 Table 6.9 Constants for the Sample Code (4) Constant Setting Description SSI_SSICR1_SWL_VALUE H The setting of the SWL bit of the SSI channel 1 control register. (System word length: 32 bits.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSICR1_SCKD_VALUE H The setting of the SCKD bit of the SSI channel 1 control register. (Serial bit clock direction: master mode.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSIFCR_TIE_INIT_VALUE H The initial setting of the TIE bit of a SSI FIFO control register. (Transmission interrupt enable: transmitted-data-empty interrupt (TXI) requests are disabled.) SSI_SSIFCR_RIE_INIT_VALUE H The initial setting of the RIE bit of a SSI FIFO control register. (Reception interrupt enable: received-data-full interrupt (RXI) requests are disabled.) SSI_SSIFCR_TFRST_INIT_VALU E SSI_SSIFCR_RFRST_INIT_VALU E H The initial setting of the TFRST bit of a SSI FIFO control register. (Transmission FIFO data register reset: reset operation is enabled.) H The initial setting of the RFRST bit of a SSI FIFO control register. (Reception FIFO data register reset: reset operation isenabled.) SSI_SSIFCR0_TTRG_VALUE H The initial setting of the TTRG bit of the SSI channel 0 FIFO control register. (Transmitted data count trigger: 7.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSIFCR0_RTRG_VALUE H The initial setting of the RTRG bit of the SSI channel 0 FIFO control register. (Received data count trigger: 1.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_SSITDMR_RXDMUTE_INIT_ VALUE H The initial setting of the RXDMUTE bit of a SSI TDM mode register. (Received direct data MUTE setting: received data is output directly.) SSI_SSITDMR_TDM_INIT_VALUE H The initial setting of the TDM bit of a SSI TDM mode register. (DM mode: TDM mode is disabled.) SSI_SSITDMR0_CONT_VALUE H The initial setting of the CONT bit of the SSI channel 0 TDM mode register. (WS continue mode: WS continue mode is disabled.) This setting is defined in drv_ssif_user.h. Change it as necessary. SSI_ERR_INT_LV 4 SSI error (transmission underflow error, reception overflow error) interrupt level. DMA_TRNEND_INT_LV 5 DMA transfer end interrupt level. SSI_IDLE_WAIT 45 Wait time for transition to an idle state during an attempt to stop SSI (fail-safe function) When stopping SSI, it is necessary to wait until the SSI module enters an idle state. Because of a possible failure in transition to an idle state, this setting is used to determine the wait time as a fail-safe means. This setting is defined in drv_ssif_user.h. Change it as necessary. R01AN2076EJ0101 Rev.1.01 Page 21 of 63

22 Table 6.10 Constants for the Sample Code (5) Constant Setting Description DMA_CHANNEL0 0 DMA channel 0. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL1 1 DMA channel 1. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL2 2 DMA channel 2. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL3 3 DMA channel 3. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL4 4 DMA channel 4. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL5 5 DMA channel 5. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL6 6 DMA channel 6. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL7 7 DMA channel 7. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL8 8 DMA channel 8. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL9 9 DMA channel 9. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL10 10 DMA channel 10. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL11 11 DMA channel 11. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL12 12 DMA channel 12. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL13 13 DMA channel 13. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL14 14 DMA channel 14. This constant is used to specify the DMA channel number to be used. DMA_CHANNEL15 15 DMA channel 15. This constant is used to specify the DMA channel number to be used. R01AN2076EJ0101 Rev.1.01 Page 22 of 63

23 Table 6.11 Constants for the Sample Code (6) Constant Setting Description N0_SIDE 0 When updating DMA Next0 registers, this constant is used to specify the registers to be updated. N1_SIDE 1 When updating DMA Next1 registers, this constant is used to specify the registers to be updated. DMA_TRANSFER_SIZE_16 H DMA transfer size is 16 bits. DMA_TRANSFER_SIZE_32 H DMA transfer size is 32 bits. DMA_STOP_WAIT 200 Wait time for the DMA module to stop during an attempt to stop DMA (fail-safe function) When stopping DMA, it is necessary to wait for the DMA module to stop. To prepare for a possible failure of DMA to be stopped, this setting is used to determine the wait time as a fail-safe means. This setting must be adjusted by the user. R01AN2076EJ0101 Rev.1.01 Page 23 of 63

24 Table 6.12 Error Codes for the Sample Code Constant Setting Description DEVDRV_SUCCESS 0 Value returned if operation is successfully completed. DEVDRV_ERROR -1 Value returned if operation has failed. DEVDRV_QUEUE_EMPTY -10 Value returned if no buffer is registered in the queue. DEVDRV_QUEUE_FULL -11 Value returned if the queue is full (a buffer cannot be registered in the queue). R01AN2076EJ0101 Rev.1.01 Page 24 of 63

25 6.6 List of Structures/Unions Figure 6.4 to Figure 6.6 show the structures and unions used in the sample program. typedef struct{ Function pointer to be executed in the main routine according to the state. int32_t (* SampleFunc)(void); /* Function pointer */ } sample_ssif_play_t; Figure 6.4 Structures and Unions Used in the Sample Program (Main) typedef struct{ SSI module register addresses volatile uint32_t *ssicr; /* control register(ssicr) */ volatile uint32_t *ssifcr; /* FIFO control register(ssifcr) */ volatile uint32_t *ssisr; /* status register(ssisr) */ volatile uint32_t *ssifsr; /* FIFO status register(ssifsr) */ volatile uint32_t *ssiftdr; /* Tx FIFO data register(ssiftdr) */ volatile uint32_t *ssifrdr; /* Rx FIFO data register(ssifrdr) */ volatile uint32_t *ssitdmr; /* TDM mode register(ssitdmr) */ } ssif_reg_t; typedef struct DMAC channel numbers used by SSI modules. { uint32_t txdma_channel; /* DMA registration situation */ uint32_t rxdma_channel; /* DMA registration situation */ } ssi_regist_info_t; Figure 6.5 Structures and Unions Used in the Sample Program (SSI Module) R01AN2076EJ0101 Rev.1.01 Page 25 of 63

26 typedef struct{ DMA module register addresses. volatile uint32_t *n0sa; /* Next0 Source Address Register(N0SA) */ volatile uint32_t *n0da; /* Next0 Destination Address Register(N0DA) */ volatile uint32_t *n0tb; /* Next0 Transaction Byte Register(N0TB) */ volatile uint32_t *n1sa; /* Next1 Source Address Register(N1SA) */ volatile uint32_t *n1da; /* Next1 Destination Address Register(N1DA) */ volatile uint32_t *n1tb; /* Next1 Transaction Byte Register(N1TB) */ volatile uint32_t *chstat; /* Channel Status Register(CHSTAT) */ volatile uint32_t *chctrl; /* Channel Control Register(CHCTRL) */ volatile uint32_t *chcfg; /* Channel Configuration Register(CHCFG) */ volatile uint32_t *chitvl; /* Channel Interval Register(chitvl) */ volatile uint32_t *chext; /* Channel Extension Register(CHEXT) */ volatile uint32_t *dstat_en; /* DMA Status EN Register(DSTAT_EN) */ volatile uint32_t *dctrl; /* DMA Control Register(DCTRL) */ volatile uint32_t *dmars; /* DMA Expansion resource selector(dmars) */ } dma_reg_t; typedef struct { Control information to be used in the DMA driver. uint32_t direct; /* Transfer direction */ uint32_t module_name; /* Name of transmit peripheral module */ uint32_t module_channel; /* Channel number of the DMA */ bool_t transfer_continue; /* Transfer continuation */ fp_type user_trnend_func; /* Callback interrupt function */ } dma_regist_info_t; Figure 6.6 Structures and Unions Used in the Sample Program (DMA Module) R01AN2076EJ0101 Rev.1.01 Page 26 of 63

27 6.7 List of Variables Table 6.13 and Table 6.14 list static variables, and Table 6.15 lists const type variables. Table 6.13 Static Variables (1) Type Variable Name Contents Function Used uint32_t audio_out_buf Buffer for storing data received from the audio codec. To the audio codec, data received by this buffer is transmitted. This buffer consists of four sides, and each time a transmission or reception is completed, the buffer is switched between the sides to perform successive transmissions and receptions. uint32_t mute_buf Buffer for storing mute data. When transmitting mute data to the audio codec, the mute data is transmitted from this buffer. uint32_t g_txbuf_side Variable for controlling the transmission side of audio_out_buf. The transmission side is switched during transmission operations as follows: side 2 -> side 3 -> side 0 -> side 1 -> side 2 -> side 3 -> side 0. uint32_t g_rxbuf_side Variable for controlling the reception side of audio_out_buf. The reception side is switched during reception operations as follows: side 0 -> side 1 -> side 2 -> side 3 -> side 0 -> side 1 -> side 2. uint32_t sample_rx_flag Variable for indicating that a transfer of audio data to one side (1764 bytes) of audio_out_buf is completed. uint32_t sample_timer_ event This variable is used to control switching operation to start and stop playback. This variable is set by an OSTM interrupt (five seconds), and is referred to by the main routine. The main routine stops playback according to this variable. Sample_Main Sample_ssif_StartPlay Sample_ssif_Play DMA_DmaInit DMA_DmaTxInit DMA_TxRegSet DMA_CheckDmaMute DmaInt Sample_Set_TxbufSide Sample_Get_TxbufSide Sample_Updata_TxbufS ide Sample_Set_RxbufSide Sample_Get_RxbufSide Sample_Updata_RxbufS ide Sample_Main Sample_ssif_StartPlay Sample_ssif_Play Sample_RxDMA_Interru pt Sample_Clear_eventFla g Sample_Get_eventFlag Sample_OSTM1_Interru pt R01AN2076EJ0101 Rev.1.01 Page 27 of 63

28 Table 6.14 Static Variables (2) Type Variable Name Contents Function Used ssi_regist_info_t ssi_regist_info This variable is used to control the DMA channel number to be used by SSI modules. dma_regist_info_t dma_regist This variable is used to manage DMA module control information related to SSI. queue_inf_t queue This variable is used to manage information on the transmission and reception buffers specified by the user*. * Information such as the start address and the byte size of transmission and reception buffers. Values to be specified in DMA Next registers are a buffer address and a transfer size that are stored in this variable. R_SSI_RamInit R_SSI_DmaInit R_SSI_DmaStart R_SSI_SsiDmaStop R_SSI_SsiDmaAdsSet SsiErrInt DMA_DmaInit DMA_DmaAdsSet DMA_DmaStart DMA_DmaTxInit DMA_DmaRxInit DMA_TxRegSet DMA_RxRegSet DmaInt DMA_DmaAdsSet DMA_QueueInit DMA_DmaStop DMA_TxRegSet DMA_RxRegSet QueueSet DmaInt R01AN2076EJ0101 Rev.1.01 Page 28 of 63

29 Table 6.15 Const Type Variables Type Variable Name Contents Function Used ssif_reg_t Ssif Stores register addresses of each SSI module. uint16_t ssi_int_id Stores the interrupt ID of each SSI module. uint32_t ssi_ssicr_reg Stores the initial setting of each SSI control register. uint32_t ssi_ssifcr_reg Stores the initial setting of each SSI FIFO control register. uint32_t ssi_ssitdmr_reg Stores the initial setting of each SSI TDM mode register. uint8_reg_bit_inf_t ssi_swrstcr1_bit_ tbl Stores the amount of masking and shifting of software reset bits for each SSI module. uint32_reg_bit_inf_t ssi_ssifcr_bit_tbl Stores the amount of masking and shifting of TIE, RIE, TFRST, and RFRST bits in SSI FIFO control registers. uint32_reg_bit_inf_t ssi_ssisr_bit_tbl Stores the amount of masking and shifting of TUIRQ, ROIRQ, and IIRQ bits in SSI status registers. uint32_reg_bit_inf_t ssi_ssicr_bit_tbl Stores the amount of masking and shifting of TUIEN, ROIEN, TEN, and REN bits in SSI control registers. dma_reg_t g_dma_reg_tbl Stores register addresses of each DMA module. uint16_t dma_ssif_dmars_ reg Stores the initial setting of each DMA extended resource selector register. uint16_t dma_int_id Stores the interrupt ID of each DMA module. R_SSI_SsiInit R_SSI_SsiStart R_SSI_SsiStop R_SSI_SsiDmaAdsSet SsiErrInt R_SSI_SsiInit R_SSI_SsiStart R_SSI_SsiStop R_SSI_SsiInit R_SSI_SsiStop SsiErrInt R_SSI_SsiInit R_SSI_SsiStop SsiErrInt R_SSI_SsiInit R_SSI_SsiStop R_SSI_SsiInit R_SSI_SsiStop SsiErrInt R_SSI_SsiStart R_SSI_SsiStop R_SSI_SsiStart R_SSI_SsiStop R_SSI_SsiStart R_SSI_SsiStop R_SSI_SsiDmaAdsSet SsiErrInt DMA_DmaStart DMA_DmaStop DMA_DmaTxInit DMA_DmaRxInit DMA_TxRegSet DMA_RxRegSet DmaInt DMA_DmaTxInit DMA_DmaRxInit DMA_DmaStart DMA_DmaStop R01AN2076EJ0101 Rev.1.01 Page 29 of 63

30 6.8 List of Functions Table 6.16 list the List of Functions. Table 6.16 List of Functions Function Name Page Number R_SSI_RamInit 31 R_SSI_SsiInit 31 R_SSI_DmaInit 32 R_SSI_SsiStart 33 R_SSI_DmaStart 34 R_SSI_SsiStop 35 R_SSI_SsiDmaStop 36 R_SSI_SsiDmaAdsSet 37 R01AN2076EJ0101 Rev.1.01 Page 30 of 63

31 6.9 Function Specifications This section contains the specifications for the functions that are implemented in the sample code R_SSI_RamInit R_SSI_RamInit Synopsis Header Declaration Description This function initializes control information used by the SSI driver. drv_ssif.h drv_ssif_user.h void R_SSI_RamInit(void) This function performs the following operation. - Initialization of control information used by the SSI driver. Be sure to execute this API before executing other APIs. Arguments None None Return value None R_SSI_SsiInit R_SSI_SsiInit Synopsis Header Declaration Description This function initializes a SSI. drv_ssif.h drv_ssif_user.h int32_t R_SSI_SsiInit(uint32_t ssi_channel) This function initializes the SSI specified by the argument ssi_channel. - Make the SSI exit a module standby state. - Perform software rest on the SSI and then release software reset. - Specify settings for SSI pins (SSISCK, SSIWS, and SSIDATA). Provide code for these settings in a user function described in drv_ssif_user.c, according to the SSI to be used. - Initializes the SSI (system word length, data length, transfer size, etc.). The initial settings are described as macros in ssif_user.h. Change them according to the settings to be used. - Specify settings for SSI interrupts (transmission underflow, reception overflow). Arguments uint32_t ssi_channel The channel number of the SSI to be initialized. Return value DEVDRV_SUCCESS: Initialization is successful. DEVDRV_ERROR: Initialization failed. - The channel number of the SSI specified by the argument does not exist. R01AN2076EJ0101 Rev.1.01 Page 31 of 63

32 6.9.3 R_SSI_DmaInit R_SSI_DmaInit Synopsis Header Declaration Description Arguments Return value This function initializes a DMAC. drv_ssif.h drv_ssif_user.h int32_t R_SSI_DmaInit(uint32_t ssi_channel, uint32_t dma_channel, uint32_t direct, fp_type func) This function initializes the DMAC to be used for SSI transmission and reception operations. The argument direct selects the transfer direction between transmission and reception. If the value of direct is SSI_TX, transmission (buffer -> SSI) is selected and the DMAC specified by the argument dma_channel is initialized accordingly. Also, if the value of direct is SSI_RX, reception (SSI -> buffer) is selected and the DMAC specified by the argument dma_channel is initialized accordingly. Configuration of a DMAC is as follows: - Set the DMA mode to register mode. - Set the DMA transfer mode to single transfer mode. - Set the DMA transfer size to 32 bits. - Set the levels of DMAC ACK and DREQ signals. - Select SSI transmitted-data-empty interrupt as the factor for activating the DMA (buffer -> SSI). - Select SSI received-data-full interrupt as the factor for activating the DMA (SSI -> buffer). - Specify settings for DMA transfer end interrupt. - Register the callback function specified by the argument func so that it is called after a transfer is completed. uint32_t ssi_channel The channel number of the SSI to be initialized. (0-5) uint32_t dma_channel The channel number of the DMA to be initialized. (0-15) uint32_t direct Selection from transmission and reception (SSI_TX: void *func transmission, SSI_RX: reception) The callback function to be called upon completion of a transfer. DEVDRV_SUCCESS: Initialization is successful. DEVDRV_ERROR: Initialization failed. - The channel number of the SSI or the DMAC does not exist. - An attempt is being made to reconfigure the DMAC that has already been initialized. R01AN2076EJ0101 Rev.1.01 Page 32 of 63

33 6.9.4 R_SSI_SsiStart R_SSI_SsiStart Synopsis Header Declaration Description This function activates a SSI. drv_ssif.h drv_ssif_user.h int32_t R_SSI_SsiStart(uint32_t ssi_channel, uint32_t direct) This function specifies settings for activating a SSI. The argument direct selects the transfer direction between transmission and reception. If the value of direct is SSI_TX, transmission (buffer -> SSI) is selected, and the SSI specified by the argument ssi_channel is configured to enable transmission. Also, if the value of direct is SSI_RX, reception (SSI -> buffer) is selected, and the SSI specified by the argument ssi_channel is configured to enable reception. The SSI specified by the argument is configured as follows: If the value of direct is SSI_TX : - Initialize the transmission FIFO. - Clear the error interrupt status (transmission underflow). - Enable error interrupt (transmission underflow). - Enable transmitted-data-empty interrupt. - Enable transmission. If the value of direct is SSI_RX : - Initialize the reception FIFO. - Clear the error interrupt status (reception overflow). - Enable an error interrupt (reception overflow). - Enable received-data-full interrupt. - Enable SSI reception. If the value of direct is SSI_RX SSI_TX. - Initialize the transmission and reception FIFOs. - Clear the error interrupt status (reception overflow, transmission overflow). - Enable error interrupt (reception overflow, transmission underflow). - Enable transmitted-data-empty interrupt and received-data-full interrupt. - Enable SSI transmission and reception. Arguments Return value uint32_t ssi_channel uint32_t direct The channel number of the SSI to be initialized. (0-5) Selection from transmission and reception (SSI_TX: transmission, SSI_RX: reception) DEVDRV_SUCCESS: Activation is successful. DEVDRV_ERROR: Activation failed. - The channel number of the SSI does not exist. - A macro other than SSI_TX and SSI_RX has been assigned to direct. R01AN2076EJ0101 Rev.1.01 Page 33 of 63

34 6.9.5 R_SSI_DmaStart R_SSI_DmaStart Synopsis Header Declaration Description This function activates a DMAC. drv_ssif.h drv_ssif_user.h int32_t R_SSI_DmaStart(uint32_t ssi_channel, uint32_t direct) This function activates a DMAC, and if transmission is selected (the value of direct is SSI_TX), it enables transmission of data to a SSI. If reception is selected (the value of direct is SSI_RX), it enables reception of data from the SSI. If transmission is selected (direct: SSI_TX), execute the R_SSI_SsiDmaAdsSet function to register a buffer in the queue before executing this function. If this function is executed without executing the R_SSI_SsiDmaAdsSet function, mute data is output. If reception is selected (direct: SSI_RX), execute the R_SSI_SsiDmaAdsSet function to register a buffer in the queue before this function. If this function is executed without executing the R_SSI_SsiDmaAdsSet function, a value indicating an error is returned and reception is not started. Also, before executing this function, be sure to use the R_SSI_SsiInit function and the R_SSI_DmaInit function to initialize the SSI and the DMAC. Arguments Return value uint32_t ssi_channel uint32_t direct The channel number of the SSI to be initialized. (0-5) Selection from transmission and reception (SSI_TX: transmission, SSI_RX: reception) DEVDRV_SUCCESS: Activation is successful. DEVDRV_ERROR: Activation failed. - The channel number of the SSI does not exist. - A macro other than SSI_TX and SSI_RX has been assigned to direct. - The DMAC has not been initialized by using the initialization function. - With reception selected, no buffer has been registered using the R_SSI_SsiDmaAdsSet function. R01AN2076EJ0101 Rev.1.01 Page 34 of 63

35 6.9.6 R_SSI_SsiStop R_SSI_SsiStop Synopsis Header Declaration Description This function stops a SSI. drv_ssif.h drv_ssif_user.h int32_t R_SSI_SsiStop(uint32_t ssi_channel) This function stops operation of the SSI specified by the argument ssi_channel. For transmitter (transmission) operation: - Stop transmission process. - Disable transmitted-data-empty interrupt. - Disable error interrupt (transmission underflow error). - Wait until the SSI enters an idle state. - Perform software rest on the SSI specified by the argument. For receiver (reception) operation: - Stop reception process. - Disable received-data-full interrupt. - Disable error interrupt (reception overflow error). - Wait until the SSI enters an idle state. - Perform software reset on the SSI specified by the argument. For transceiver (full-duplex communication) operation: - Stop transmission and reception process. - Disable transmitted-data-empty interrupt and received-data-full interrupt. - Disable error interrupt (transmission underflow error, reception overflow error). - Wait until the SSI enters an idle state. - Perform software reset on the SSI specified by the argument. Arguments uint32_t ssi_channel The channel number of the SSI to be initialized. (0-5) Return value DEVDRV_SUCCESS: SSI successfully stopped. DEVDRV_ERROR: SSI failed to stop. - The channel number of the SSI does not exist. R01AN2076EJ0101 Rev.1.01 Page 35 of 63

36 6.9.7 R_SSI_SsiDmaStop R_SSI_SsiDmaStop Synopsis Header Declaration Description This function stops SSI transmission and reception. drv_ssif.h drv_ssif_user.h int32_t R_SSI_SsiDmaStop(uint32_t ssi_channel) This function stops operation of the SSI specified by the argument ssi_channel. For transmitter (transmission) operation: - Stop the DMAC (buffer -> SSI) related to the SSI specified by an argument. Then, set the source address register to specify a mute buffer, and start output of mute data. For receiver (reception) operation: - Stop reception process. - Disable received-data-full interrupt. - Disable error interrupt (reception overflow error). - Wait until the SSI enters an idle state. - Perform software reset on the SSI specified by an argument. For transceiver (full-duplex communication): - Stop transmission and reception process. - Disable transmitted-data-empty interrupt and received-data-full interrupt. - Disable error interrupt (transmission underflow error, reception overflow error). - Wait until the SSI enters an idle state. - Perform software reset on the SSI specified by an argument. Arguments Return value uint32_t ssi_channel uint32_t direct The channel number of the SSI to be initialized. (0-5) Selection from transmission and reception (SSI_TX: transmission, SSI_RX: reception) DEVDRV_SUCCESS: SSI successfully stopped. DEVDRV_ERROR: SSI failed to stop. - The channel number of the SSI module does not exist. R01AN2076EJ0101 Rev.1.01 Page 36 of 63

37 6.9.8 R_SSI_SsiDmaAdsSet R_SSI_SsiDmaAdsSet Synopsis Header Declaration Description This function registers a buffer in the queue. drv_ssif.h drv_ssif_user.h int32_t R_SSI_SsiDmaAdsSet( const uint32_t ssi_channel, const uint32_t direct, volatile const void * const buf, const uint32_t buf_size ) This function registers transmission and reception buffers in the queue. If an argument is set for transmission (direct: SSI_TX), it registers a transmission buffer in the queue, or if the argument is set for reception (direct: SSI_RX), it registers a reception buffer in the queue. A four-stage queue is provided separately for transmission and reception. If transmission is selected (direct: SSI_TX), use this function to register a transmission buffer in the queue before a transfer is completed for the transmission buffer already registered in the queue. If registration is not in time, mute data is output. If reception is selected (direct: SSI_RX), register the next reception buffer in the queue before the reception buffer already registered in the queue becomes full. If registration is not in time, the lastly registered reception buffer is overwritten with data. Arguments Return value uint32_t ssi_channel uint32_t direct void * const buf, uint32_t buf_size The channel number of the SSI to be initialized. (0-5) Selection from transmission and reception (SSI_TX: transmission, SSI_RX: reception) The start address of a transmission or reception buffer. The size of a transmission or reception buffer. DEVDRV_SUCCESS: Queue registration is successful. DEVDRV_ERROR: Queue registration failed. - The channel number of the SSI does not exist. DEVDRV_QUEUE_FULL: Registration failed because the queue was full. R01AN2076EJ0101 Rev.1.01 Page 37 of 63