Taking Advantage of Using the dmax DMA Engine in Conjunction with the McASP Peripheral on the TMS320C67x DSP

Transcription

1 Taking Advantage of Using the dmax DMA Engine in Conjunction with the McASP Peripheral on the TMS30C67x DSP SPRP498 Name: Gaganjot Singh Maur Title: Application Engineer Company Name: Texas Instruments

2 TMS30C67x TM Device Overview 56K Bytes SRAM 768K Bytes ROM EMIF HPI TMS30C67x Floating-Point DSP Instruction Cache 3K Bytes C67x+ TM DSP Core Memory Controller Max Switch Control Max dmax Config DMA SPI 0 IIC 0 IIC 1 McASP 0 McASP 1 McASP SPI 1 RTI TImer 300 MHz DSP core 300 MHz 67x+ core 64 Reg + Additional FP instructions Code Compatible with 6713 Devices Large on-chip memory 768KB on-chip ROM 56KB on-chip RAM 3KB Inst. cache (Int Mem + EMIF) EMIF for expansion Enhanced Audio IO 16 serial data pins Up to 6 different clock rates dmax - Support for dma, circular and multi-tap memory delay (for Reverb) HPI supports mux A/D and nonmux A/D

3 TMS30C677/C676/C67 High Performance Audio Processors and Low System Cost Options C67 00/50 MHz C MHz C677 50/300 MHz MFLOPS Memory McASP I C SPI HPI EMIF 100/ K Bytes SRAM 384 K Bytes ROM 3 K Bytes Instr. Cache N/A K Bytes SRAM 384 K Bytes ROM 3 K Bytes Instr. Cache 3 N/A 1350/ bit 16-bit 3-bit dmax Yes Yes Yes 56 K Bytes SRAM 384 K Bytes ROM 3 K Bytes Instr. Cache 3 Yes Availability Today! Today! Software Compatible Today! Typical Applications Musical Instruments Sound and musical modification and generation Audio conferencing Audio broadcast, encoding and studio applications 3

4 dmax Block Diagram High Priority PaRAM Event Entry Table HiMAX RAM R/W Transfer Entry Table Control R/W Low Priority PaRAM Event Entry Table LoMAX RAM R/W Transfer Entry Table Event Entry #0 Event Entry #k Event Entry #31 Reserved Transfer Entry #0 Transfer Entry #k Transfer Entry 7 Event Entry #0 Event Entry #k Event Entry #31 Reserved Transfer Entry #0 Transfer Entry #k Transfer Entry 7 HiMAX LoMAX dmax High Priority REQ EventEncoder + Event and Interrupt Registers Low Priority REQ HiMAX Interrupt Lines to The CPU LoMAX Events The dmax comprises: Event and interrupt processing registers. Event encoder. Address generation hardware for High Priority Event (HiMAX) Address generation hardware for Low Priority Event (LoMAX). High priority event Parameter RAM (HiPaRAM). Low priority event Parameter RAM (LoPaRAM). Transfers Supported General Purpose (1D, D, 3D) FIFO Read, FIFO Write One Dimensional burst SPI Slave data transfer 4

5 McASP Block Diagram Features: Independent clock generator modules for transmit and receive TDM streams from to 3, and 384 time slots Data formatter for bit manipulation Up to 16 individually assignable serial data pins Wide variety of IS and similar bit-stream format S/PDIF, IEC , AES-3 formats Extensive error checking and recovery 5

6 General Purpose Transfer SINDX1=-3 0x x x x C 0x x x x C 0x x x x100010C 0x x x x C 0x x x x C 0x x x x C Source A0 D0 B0 E0 C0 F0 A1 D1 B1 E1 C1 F1 A D B E C F SINDX0= SINDX0= SINDX= DINDX=-19 Destination 0x x A0 0x A1 0x100000C A 0x x B0 0x B1 0x100001C B 0x x C0 0x C1 0x10000C C 0x x D0 0x D1 0x100003C D 0x x E0 0x E1 0x100004C E 0x x F0 0x F1 0x100005C F 0x DINDX0=4 DINDX0=4 DINDX1=4 DINDX0=4 DINDX0=4 Features: 1 Dimension (Block Move), Dimension (Sub-frame extraction) 3 Dimension (Data De- Interleaving) transfer support Separate IDX for 1 st, nd and 3 rd dimension Separate IDX for source and destination Transfer first dimension for an event or complete the entire transfer Supports two reload addresses for source and destination for effective Ping-Pong 6

7 FIFO Transfers FIFO Features: SOURCE DESTINATION Moves data b/w two dimensional linear address and a circular buffer. Circular buffer size need not be ^n Table based multi tap delay transfer support Transfer Entry for FIFO Write SRC Pointer Transfer Entry for FIFO Read DST Pointer Reload allows Ping-Pong implementation for linear buffer CPU notification for FIFO Watermark conditions Delay Table 0 CNT1 CNT 0 IDX1 IDX 0 Reference CNT RLDSRC1 RLDSRC0 FIFO Base FIFO Size Read Pointer Write Pointer CNT1 CNT 0 IDX1 IDX 0 Reference CNT RLDDST1 RLDDST0 Delay Table 0 Error checking for FIFO overflow and underflow Ptr to Delay Tables Error Flags Ptr to Delay Tables Pointer to FIFO DESC Pointer to FIFO DESC Delay Table 1 FIFO DESC Delay Table 1 7

8 McASP Transfer Format TDM streams from to 3, and 384 time slots Wide variety of IS and similar bit-stream format S/PDIF, IEC , AES-3 formats 8

9 dmax McASP Servicing LEFT1 RGHT1 LEFT RGHT LEFT3 RGHT3 LEFT4 RGHT4 Frame CLK McASP Pin 1 McASP Pin McASP Pin 3 dmax Services the McASP and does data sorting Pin 1 LEFT Pin 1 RGHT Pin LEFT Pin RGHT Pin 3 LEFT Pin 3 RGHT 9

10 Delay Based Effects OLD WRITE PTR FIFO WRITE TRANSFER INPUT LINEAR BUFFER AUDIO AUDIO ALGORITHM. ALGORITHM. N N TAP TAP PROCESSING PROCESSING NEW WRITE PTR FIFO READ TRANSFER FIFO Write dmax transfer updates the FIFO with new data FIFO Read Transfer reads N TAP data Read and Write PTR updated by dmax dmax takes care of circular buffering Error reporting for FIFO under run or overflow BUFF BUFF BUFF 1 N LINEAR BUFFERS BUFF N OLD READ PTR NEW READ PTR DELAY TABLE DLY IDX 1 DLY IDX DLY IDX 3 DLY IDX N 10

11 Example Audio Processing System AUDIO THREAD McASP RX Audio I/O Driver RX F/W Audio Thread Audio I/O Driver TX McASP TX Audio Data on McASP Pins Audio Processing Alg 1 Audio Processing Alg Audio Data on McASP Pins FIFO FIFO PING PING CTRL DATA TRANSFER B/W THREAD PONG PONG Ctrl data on SPI/IC CONTROL THREAD SPI/IC Control I/O Driver F/W Ctrl Thread dmax TRANSFERS CPU PROCESSING 11

12 Example Audio System dmax Performance Data CPU CPU 300MHz 300MHz EMIF EMIF 100MHz 100MHz 3bit 3bit TRANSFER MAX Unit LOAD % 8 Channel 19KHz Audio RX 8 Channel 19KHz Audio TX 10MBPS SPI Control Data MAX 0 MAX TOTAL 95 % TOTAL 95 % TRANSFER MAX Unit LOAD % FIFO Write 3 * 19K Bytes FIFO Read 160 * 19K Bytes 10MB Read + Write to SDRAM MAX 1 MAX TOTAL 87 % TOTAL 87 % 1