This lecture. Virtual Memory. Virtual memory (VM) CS Instructor: Sanjeev Se(a

Transcription

1 Virtual Memory Instructor: Sanjeev Se(a This lecture (VM) Overview and mo(va(on VM as tool for caching VM as tool for memory management VM as tool for memory protec(on Address transla(on 2

2 Virtual Memory (Previous Lectures) Programs refer to virtual memory addresses movl (%ecx),%eax Conceptually very large array of bytes Each byte has its own address Actually implemented with hierarchy of different memory types System provides address space private to par(cular process Compiler and system Where different program objects should be stored All alloca(on within single virtual address space But why virtual memory? Why not physical memory? FF F 3 Problem : How Does Everything Fit? 64- bit addresses: 6 Exabyte Physical main memory: Few Gigabytes? And there are many processes. 4 2

3 Problem 2: Memory Management Physical main memory Process Process 2 Process 3 Process n x stack heap.text.data What goes where? 5 Problem 3: How To Protect Process i Physical main memory Process j Problem 4: How To Share? Process i Physical main memory Process j 6 3

4 Level Of Process Physical memory mapping Process n Each process gets its own private memory space Solves the previous problems 7 Address Spaces Linear address space: Ordered set of con(guous non- nega(ve integer addresses: {,, 2, 3 } Virtual address space: Set of N = 2 n virtual addresses {,, 2, 3,, N- } Physical address space: Set of M = 2 m physical addresses {,, 2, 3,, M- } Clean dis@nc@on between data (bytes) and their a[ributes (addresses) Each object can now have mul@ple addresses Every byte in main memory: one physical address, one (or more) virtual addresses 8 4

5 A System Using Physical Addressing CPU Physical address (PA) Main memory : : 2: 3: 4: 5: 6: 7: 8:... M- : Data word Used in simple systems like embedded microcontrollers in devices like cars, elevators, and digital picture frames 9 A System Using Virtual Addressing CPU Chip CPU Virtual address (VA) MMU Physical address (PA) Main memory : : 2: 3: 4: 5: 6: 7: 8:... M- : Data word Used in all modern desktops, laptops, worksta@ons One of the great ideas in computer science MMU checks the cache 5

6 Why Virtual Memory (VM)? Efficient use of limited main memory (RAM) Use RAM as a cache for the parts of a virtual address space some non- cached parts stored on disk some (unallocated) non- cached parts stored nowhere Keep only ac(ve areas of virtual address space in memory transfer data back and forth as needed Simplifies memory management for programmers Each process gets the same full, private linear address space Isolates address spaces One process can t interfere with another s memory because they operate in different address spaces User process cannot access privileged informa(on different sec(ons of address spaces have different permissions This lecture (VM) Overview and mo(va(on VM as tool for caching VM as tool for memory management VM as tool for memory protec(on Address transla(on 2 6

7 VM as a Tool for Caching : array of N = 2 n con@guous bytes think of the array (allocated part) as being stored on disk Physical main memory = cache for allocated virtual memory Blocks are called pages; size = 2 p Physical memory Disk VP VP Unallocated Cached Uncached Unallocated Cached Uncached Cached n- p - Uncached 2 n - 2 m - Empty Empty Empty PP PP PP 2 m- p - Virtual pages (VP's) stored on disk Physical pages (PP's) cached in DRAM 3 Memory Hierarchy: Core 2 Duo L/L2 cache: 64 B blocks Not drawn to scale CPU Reg Throughput: Latency: L I- cache 32 KB L D- cache ~4 MB L2 unified cache ~4 GB ~5 GB Main Memory 6 B/cycle 8 B/cycle 2 B/cycle B/3 cycles 3 cycles 4 cycles cycles millions Disk Miss penalty (latency): 3x Miss penalty (latency):,x 4 7

8 DRAM Cache DRAM cache driven by the enormous miss penalty DRAM is about x slower than SRAM Disk is about,x slower than DRAM For first byte, faster for next byte Consequences Large page (block) size: typically 4-8 KB, some(mes 4 MB Fully associa(ve Any VP can be placed in any PP Requires a large mapping func(on different from CPU caches Highly sophis(cated, expensive replacement algorithms Too complicated and open- ended to be implemented in hardware Write- back rather than write- through 5 Address Transla@on: Page Tables A page table is an array of page table entries (PTEs) that maps virtual pages to physical pages. Here: 8 VPs Per- process kernel data structure in DRAM Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 6 8

9 Address With a Page Table Page table base register (PTBR) Virtual address Virtual page number (VPN) Virtual page offset (VPO) Page table address for process Page table Valid Physical page number (PPN) Valid bit = : page not in memory (page fault) Physical page number (PPN) Physical address Physical page offset (PPO) 7 Page Hit Page hit: reference to VM word that is in physical memory Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 8 9

10 Page Miss Page miss: reference to VM word that is not in physical memory Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 9 Handling Page Fault Page miss causes page fault (an excep(on) Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 2

11 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 2 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 22

12 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Offending instruc(on is restarted: page hit! Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 23 Why does it work? Locality works because of locality At any point programs tend to access a set of ac@ve virtual pages called the working set Programs with befer temporal locality will have smaller working sets If (working set size < main memory size) Good performance for one process aher compulsory misses If ( SUM(working set sizes) > main memory size ) Thrashing: Performance meltdown where pages are swapped (copied) in and out con(nuously 24 2

13 This lecture (VM) Overview and mo(va(on VM as tool for caching VM as tool for memory management VM as tool for memory protec(on Address transla(on 25 VM as a Tool for Memory Management Key idea: each process has its own virtual address space It can view memory as a simple linear array Mapping func(on scafers addresses through physical memory Well chosen mappings simplify memory alloca(on and management Virtual Address Space for Process : VP... Address translanon PP 2 Physical Address Space Virtual Address Space for Process 2: N- N- VP... M- PP 6 PP 8... (e.g., read- only library code) 26 3

14 VM as a Tool for Memory Management Memory alloca@on Each virtual page can be mapped to any physical page A virtual page can be stored in different physical pages at different (mes Sharing code and data among processes Map virtual pages to the same physical page (here: PP 6) Virtual Address Space for Process : VP... Address translanon PP 2 Physical Address Space Virtual Address Space for Process 2: N- N- VP... M- PP 6 PP 8... (e.g., read- only library code) 27 Simplifying Linking and Loading Linking Each program has similar virtual address space Code, stack, and shared libraries always start at the same address Loading execve() allocates virtual pages for.text and.data sec(ons = creates PTEs marked as invalid The.text and.data sec(ons are copied, page by page, on demand by the virtual memory system xc x4 x848 Kernel virtual memory User stack (created at run@me) Memory- mapped region for shared libraries heap (created by malloc) Read/write segment (.data,.bss) Read- only segment (.init,.text,.rodata) Unused Memory invisible to user code %esp (stack pointer) brk Loaded from the executable file 28 4

15 This lecture (VM) Overview and mo(va(on VM as tool for caching VM as tool for memory management VM as tool for memory Address transla(on 29 VM as a Tool for Memory Protec@on Extend PTEs with permission bits Page fault handler checks these before remapping If violated, send process SIGSEGV (segmenta(on fault) Process i: VP : SUP No READ WRITE Yes No Address PP 6 Physical Address Space VP : : No Yes Yes Yes Yes Yes PP 4 PP 2 PP 2 PP 4 PP 6 Process j: VP : VP : : SUP No Yes No READ WRITE Yes Yes Yes No Yes Yes Address PP 9 PP 6 PP PP 8 PP 9 PP 3 5

16 This lecture (VM) Overview and mo(va(on VM as tool for caching VM as tool for memory management VM as tool for memory protec(on Address 3 Address Page Hit CPU Chip CPU VA MMU 2 PTEA PTE 3 PA Cache/ Memory 4 Data 5 ) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor 32 6

17 Address Page Fault Page fault handler 4 CPU Chip CPU VA 7 MMU 2 PTEA PTE 3 Cache/ Memory Vic@m page 5 New page Disk 6 ) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) Valid bit is zero, so MMU triggers page fault excep(on 5) Handler iden(fies vic(m (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restar(ng faul(ng instruc(on 33 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP PP PP 3 VP

18 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP 3 35 Handling Page Fault Page miss causes page fault (an excep(on) Page fault handler selects a vic(m to be evicted (here ) Offending instruc(on is restarted: page hit! Virtual address Physical page number or Valid disk address PTE null null PTE 7 Memory resident page table Physical memory VP (disk) VP VP 6 PP PP

19 Speeding up with a TLB Page table entries (PTEs) are cached in L like any other memory word PTEs may be evicted by other data references PTE hit s(ll requires a - cycle delay Solu@on: TranslaNon Lookaside Buffer (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages 37 TLB Hit CPU Chip TLB 2 PTE VPN 3 CPU VA MMU PA 4 Cache/ Memory Data 5 A TLB hit eliminates a memory access 38 9

20 TLB Miss CPU Chip TLB 4 2 PTE VPN 3 CPU VA MMU PTEA PA Cache/ Memory 5 Data 6 A TLB miss incurs an add l memory access (the PTE) Fortunately, TLB misses are rare 39 Simple Memory System Example Addressing 4- bit virtual addresses 2- bit physical address Page size = 64 bytes VPN Virtual Page Number VPO Virtual Page Offset PPN Physical Page Number PPO Physical Page Offset 4 2

21 Simple Memory System Page Table Only show first 6 entries (out of 256) VPN PPN Valid VPN 8 9 A B C D E F PPN D D Valid 4 Simple Memory System TLB 6 entries 4- way associa@ve TLBT TLBI VPN VPO Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 3 9 D D 2 4 A D A

22 Simple Memory System Cache 6 lines, 4- byte block size Physically addressed Direct mapped CT CI CO PPN PPO Idx Tag 9 5 B Valid B B 2 6D B F B3 8 9 Idx 8 9 A B C Tag 24 2D 2D B 2 Valid B 3A 93 B 5 B2 5 DA B3 89 3B D C2 F DF D 3 D E F B 5 D3 43 Address Transla@on Example # Virtual Address: x3d4 TLBT TLBI VPN VPO VPN xf TLBI 3 TLBT x3 TLB Hit? Y Page Fault? N PPN: xd Physical Address CT CI CO PPN PPO CO CI x5 CT xd Hit? Y Byte: x

23 Address Example #2 Virtual Address: xb8f TLBT TLBI VPN VPO VPN x2e TLBI 2 TLBT xb TLB Hit? N Page Fault? Y PPN: TBD Physical Address CT CI CO PPN PPO CO CI CT Hit? Byte: 45 Address Transla@on Example #3 Virtual Address: x2 TLBT TLBI VPN VPO VPN x TLBI TLBT x TLB Hit? N Page Fault? N PPN: x28 Physical Address CT CI CO PPN PPO CO CI x8 CT x28 Hit? N Byte: Mem 46 23

24 Summary Programmer s view of virtual memory Each process has its own private linear address space Cannot be corrupted by other processes System view of virtual memory Uses memory efficiently by caching virtual memory pages Efficient only because of locality Simplifies memory management and programming Simplifies protec(on by providing a convenient interposi(oning point to check permissions 47 24