COMP375 Practice Final Exam

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Shannon Haynes
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You are allowed one and only one 8½ by 11 inch page of notes during this exam. You are not allowed to use more than 187 square inches of paper surface to hold your notes.

1 You are allowed one and only one 8½ by 11 inch page of notes during this exam. You are not allowed to use more than 187 square inches of paper surface to hold your notes. Telephone calls and texting are not allowed during the exam. The following table represents the microcode for the simple CPU shown above. Each column represents the possible setting of the switches shown as small circles in the diagram. The possible tions are ADD, SUB, AND, OR, DECrement by 1 and INCrement by 1. The possible memory tions are READ, WRITE, and WAIT. 1. [8 points] add R2, 47 Add the constant to R2. Show the instruction fetch and program counter incrementation. IR IRadr result oprnd R1 R1 R2 R2 MAR Mem 2. [7 points] return Pop the return address from the stack and put it in the program counter. Assume R2 is the stack pointer. Do NOT show the instruction fetch. IR IRadr result oprnd R1 R1 R2 R2 MAR Mem (The tables may or may not be longer than necessary.) 3. [7 points] Imagine your company has a database server that you need to keep running even if one of the disk drives fails. The operating system uses 24 GB of space and the database requires 200 GB of space. There is a good deal on 320 GB drives. How should you configure the server s disks and how many disks are required? COMP Computer Architecture and Organization page 1 of 5 page total

2 A protocol requires the CPU to put the address on the during the first clock period. On the fourth clock period and every clock period afterwards data is retrieved from the RAM. 4. [10 points] Assume the system has a 256 bit wide. The system always reads 96 bytes at a time. How many clock cycles does it take from when the CPU first requests the data until 96 bytes have been read? (Note the diagram above may or may not show more or less cycles than necessary.) If the operates at 800 MHz, how long is a single clock cycle? How many nanoseconds does it take to read 96 bytes from the RAM? 5. [4 points] New Intel processors have a feature called Enhanced Intel SpeedStep Technology that reduces the system voltage and clock frequency when the system is relatively idle. Why might you want to do this? What advantage does this provide? 6. [7 points] You just purchased a server with a RAID 5 controller that has 5 physical disk drives of 320 GB each. How much data can you store on the server? COMP Computer Architecture and Organization page 2 of 5 page total

3 7. [12 points] Write a program in Intel assembler to perform the equivalent calculations as shown in C++. int horse, mule, donkey; cin >> horse >> mule >> donkey; // reads data in C++ _asm { /* write this part in assembler horse = donkey * (mule + horse); mule++; if ( mule > 42 ) { donkey = 23; } else { donkey = 12; } */ } cout << horse << mule << donkey << endl; 8. [8 points] Consider a system with a 64 bit address space, 4 MB cache with 64 byte lines using direct mapping. Divide the address below labeling each part of the address and specify the size of each field in bits. COMP Computer Architecture and Organization page 3 of 5 page total

4 Rotational Speed 15,000 RPM Average Read Seek Time 4.8 ms Track-To-Track Seek Time 2.0 ms Full Stroke Seek 19.2 ms Cylinders 32,767 Number of Heads (Physical) 4 Sectors Per Track 63 Bytes Per Sector [10 points] How long, on the average, will it take to read a 24 KB file from the above disk assuming all blocks are stored together on a track? 10. [9 points] A memory system has RAM with an access time of 54.0 nsec and cache memory with an access time of 4.8 nsec. If the system gets an average hit rate of 91%, what is the average memory access time? 11. [2 points] Roughly how many nanoseconds are there in a millisecond? COMP Computer Architecture and Organization page 4 of 5 page total

5 12. [8 points] Explain the two different forms of the locality of reference. 13. [8 points] Explain how locality of reference and the memory hierarchy work together to improve system performance. COMP Computer Architecture and Organization page 5 of 5 page total

Quiz for Chapter 6 Storage and Other I/O Topics 3.10

Quiz for Chapter 6 Storage and Other I/O Topics 3.10 Date: 3.10 Not all questions are of equal difficulty. Please review the entire quiz first and then budget your time carefully. Name: Course: 1. [6 points] Give a concise answer to each of the following