EEM478-WEEK7 PART B Bootloader

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1 EEM478-WEEK7 PART B Bootloader

2 Learning Objectives Need for a bootloader. What happens during a reset. Boot modes and processes. Memory map. Chapter 9, Slide 2

3 VCC EPROM What is the bootloader? VCC Boot Config EMIF DMA L2 Cache L1P Cache CPU Addr C6211/C6711 L1D Cache When the DSP is NOT powered or under reset the internal program memory is in a random state. Chapter 9, Slide 3

4 VCC EPROM What is the bootloader? VCC Boot Config L1P Cache EMIF DMA L2 Cache CPU PC=0000 PC=0001 PC=0002 PC=0003 Addr Chapter 9, Slide 4 C6211/C6711 L1D Cache When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero.

5 VCC What is the bootloader? VCC Boot Config L1P Cache EPROM EMIF DMA L2 Cache CPU C6211/C6711 L1D Cache With the boot, a portion of code can be automatically copied from external to internal memory. Chapter 9, Slide 5

6 What happens at reset: System timeline /RS pin CPU Reset Device Reset When the device is held in reset: The device is initialised to the default state. Most 3-state outputs are in the high impedance state. Chapter 9, Slide 6

7 What happens at reset: System timeline /RS pin CPU Reset Chapter 9, Slide 7 Device Reset CPU Reset Boot load in operation On the rising edge of the /RS pin: The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero.

8 What happens at reset: System timeline /RS pin CPU Reset Device Reset CPU Reset Boot load in operation Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. The CPU starts running from address zero. Chapter 9, Slide 8

9 C6211 and C6711 Memory map The C6211 and C6711 has only one memory map, MAP0. Internal memory is always located at address zero. Internal memory can be used as either program or data. Chapter 9, Slide 9

10 C6211 and C6711 Memory map Chapter 9, Slide 10

11 Boot modes and processes Two questions need to be answered about the bootloader, these are: What methods of boot are available and how are they selected? How does the DSP know what type of memory it is going to boot from? Chapter 9, Slide 11

12 Bootloader operational modes The TMS320C6211 and C6711 support the following boot configurations: (1) Host Port Interface (HPI) boot. (2) 8-bit ROM boot. (3) 16-bit ROM boot. (4) 32-bit ROM boot. Note: with the C6211 and C6711 there is no no-boot mode as for the other C6000 processors. Chapter 9, Slide 12

13 Bootloader configuration The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. Depending on the voltages on this pins one of the four modes is selected. HD[4:3] Boot mode HPI boot 8-bit ROM boot with different mapping 16-bit ROM boot with different mapping 32-bit ROM boot with different mapping Chapter 9, Slide 13

14 Endianess configuration The endian mode is determined at the same time as boot mode. Pulling pin HD[8] high or low selects the following endian modes. HD[8] 0 1 Device operation Big endian Little endian Note: ensure that the software development tools are also configured with the same endian type as the hardware. Chapter 9, Slide 14

15 Clock mode configuration The input clock mode is also determined at the same time as boot mode. Pulling CLKMODE0 pin high or low selects the following modes. CLKMODE0 0 1 PLL frequency multiplier No multiplication Input frequency is multiplied by 4 Chapter 9, Slide 15

16 Boot process: HPI boot mode In this mode the following sequence is used: The CPU is held in reset while the remaining of the device is released. The host processor initialises the CPU s memory space through the HPI. When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a 1 to the DSPINT bit filed of the Host Port Interface Control (HPIC) register. 17 DSPINT HPIC Chapter 9, Slide 16

17 Boot process: HPI boot mode /RS Boot Config L1P Cache HOST DRAM EMIF HPI DMA C6211/C6711 L2 Cache CPU L1D Cache Chapter 9, Slide 17

18 Boot process: HPI boot mode Question: How does the host processor check that the memory has been initialised correctly? Answer: The host can read and write to any address so it can check by reading the initialised memory. Chapter 9, Slide 18

19 Boot process: HPI boot mode Question: If an external memory needs to be initialised via the HPI how do you ensure that the EMIF is set correctly? Answer: The first thing the Host should do is to write the EMIF register then write to the external memory locations. Chapter 9, Slide 19

20 Boot process: ROM boot mode In this mode the following sequence is used: The CPU is held in reset while the bootloader operates. The bootloader copies 1Kbytes from CE1 with the default settings to internal memory at address zero. CPU is taken out of reset. CPU starts running code from address zero. Chapter 9, Slide 20

21 VCC Boot process: ROM boot mode /RS Boot Config L1P Cache ROM DRAM EMIF DMA C6211/C6711 L2 Cache CPU L1D Cache Chapter 9, Slide 21

22 WEEK7-PART B Bootloader - End -

TMS320C620x/C670x DSP Boot Modes and Configuration Reference Guide

TMS320C620x/C670x DSP Boot Modes and Configuration Reference Guide TMS320C620x/C670x DSP Reference Guide Literature Number: July 2003 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,