TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

Transcription

1 Application Report SPRA631 - April 2000 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology Kyle Castille TMS320C6000 DSP Applications ABSTRACT This document gives an overview of the memory technologies currently available in the semiconductor industry. It highlights the tradeoffs in memory selection in a TMS320C6000 External Memory Interface (EMIF) based system. The following memory technologies will be considered: Static RAM (SRAM) Dynamic RAM (DRAM) First In First Out (FIFO) Memory Contents 1 SRAM Overview Asynchronous SRAM Synchronous SRAM Flow-through vs. Pipeline Burst Burst Mode of SBSRAM Defined Next Generation SRAM DRAM Overview SDRAM Double Rate (DDR) SDRAM Rambus DRAM (RDRAM) FIFO Overview FWFT vs. Standard Synchronous FIFO EMIF Overview What s Next List of Figures Figure 1. SRAM Performance Trends Figure 2. Asynchronous SRAM Functional Block Diagram Figure 3. Asynchronous SRAM Timing Diagram Figure 4. Flow-through Synchronous SRAM Block Diagram Figure 5. Flow-through Synchronous SRAM Timing Diagram Figure 6. Pipeline Burst Synchronous SRAM Functional Block Diagram Figure 7. Pipeline Burst Synchrounous SRAM Timing Diagram Figure 8. Burst Enabled vs. Burst Disabled Interface Example TMS320C6000 is a trademark of Texas Instruments. 1

2 Figure 9. Next Generation SRAM Figure 10. DRAM Performance Trends Figure 11. SDRAM Functional Block Diagram Figure 12. SDRAM Timing Diagram Figure 13. DDR SDRAM Timing Diagram Figure 14. Rambus Block Diagram Figure 15. FIFO Block Diagram Figure 16. FWFT vs. Standard FIFO List of Tables Table 1. EMIF Comparison Table 2. EMIF Quick Reference Guide Table 3. I/O Standards for Next Generation Memory SRAM Overview Static random access memory (SRAM) typically uses a 4 to 6 transistor memory array that offers distinct advantages and disadvantages relative to dynamic random access memory (DRAM). The major advantage is that as long as power is applied, the 4/6 transistor cell maintains a stored value indefinitely. No special refresh or control cycles are necessary. The disadvantage of the 4/6 transistor cell is the density of an SRAM array as compared to a DRAM array. SRAM has a much smaller total storage space than DRAM. Typical depths for SRAM devices range from 1 MBit to 8 MBit devices with current production processes. Next generation devices are becoming available in configurations as deep as 16 MBit. Another advantage is that SRAM devices normally utilize a linear addressing scheme. In other words, with the address pins available for a given device, the entire depth of the SRAM memory can be directly addressed. There is no performance penalty for accessing opposite extremes of the SRAM memory. Figure 1 shows the performance roadmap of SRAM devices. The timeline for SRAM memory trends is presented versus performance improvements and time. The move to faster SRAM and different architectures does not preclude the usefulness of older and slower technologies. Since typical C6000 memory transactions (such as cache accesses or DMA paging) are linear bursts, SRAM does not offer a huge performance improvement over DRAM on a per cycle basis. Therefore, synchronous SRAM is sometimes used in order to reduce complexity and design effort (due to better AC timings compared to equivalent speed SDRAM devices). Slower asynchronous SRAM may be used as a cheaper alternative if lower performance is acceptable or if a simple shared memory scheme is implemented with some other external device. 2 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

3 ASRAM < 10 ASRAM < 100 < 166 Pipelined SBRAM ÍÍÍÍ Flow thru ÍÍÍÍ SBRAM < 133 Figure 1. SRAM Performance Trends ÏÏÏÏÏ Double Rate ÏÏÏ < 200 <400 ÍÍÍÍÍ Late Write < 300 ÍÍ ÍÍÍÍ ZBT < 166 Not compatible C6000 Compatible ÍÍÍÍÍÍÍ Next Generation ÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇ Not Planned ÇÇÇÇÇÇÇ 1.1 Asynchronous SRAM As the name implies, asynchronous SRAM operates asynchronously; that is, no clock is used internally to pipeline operations. The address at the inputs (in conjunction with the appropriate control signals) begins the read access to the memory array and the data is available at the outputs some time later. The amount of time between control/address valid to output data valid (t acc ) is totally dependent on device physics (such as process technology, route lengths, buffer strength) but is not dependent on a clock. The opposite is true for writes. The setup time required by the memory before the write actually takes place is dependent on the amount of time it takes for the external data to propagate into the memory array. Asynchronous SRAMs are typically available in speeds ranging from as slow as 100 ns access time up to speeds as fast as 8 to 10 ns. Figure 2 shows a functional block diagram of an asynchronous SRAM and Figure 3 shows a simplified timing diagram. TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 3

4 Memory Array Figure 2. Asynchronous SRAM Functional Block Diagram Fast ASRAM A1 A2 tacc = 10 ns tacc = 10 ns D1 D2 1 Slow ASRAM 1 1 A1 tacc = 100 ns D1 Figure 3. Asynchronous SRAM Timing Diagram 1.2 Synchronous SRAM Flow-through vs. Pipeline Burst Flow-through synchronous SRAM is used in embedded applications or slow (relatively speaking) memory systems. Flow-through synchronous SRAM registers inputs but not outputs, resulting in a read latency of 1 cycle and a write latency of 0 cycles. This allows pipelining of commands; but compared to a pipeline burst SRAM, the cycle speed of the device is slower. Typical flow-through speeds are in the range of 66 to 100. For the same architecture, a pipeline burst device typically achieves between a 25% to 50% faster clock cycle. The C6000 EMIF is not compatible with flow-through synchronous SRAM. Figure 4 shows a functional block diagram of a flow-through synchronous SRAM and Figure 5 shows a simplified timing diagram. 4 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

5 A /Reg B Memory Array C D Clock Reg Figure 4. Flow-through Synchronous SRAM Block Diagram Clock (A) (A) A1 A2 (B) (B) A1 A2 (C) D1 D2 (D) D1 D2 Figure 5. Flow-through Synchronous SRAM Timing Diagram Pipeline burst synchronous SRAMs (commonly called SBSRAMs in TI literature) achieve higher performance than synchronous flow-through SRAMs by registering both inputs and outputs, resulting in a 2-cycle read latency and a 0-cycle write latency. A register is inserted at the halfway point between the memory array and output buffer. This register allows the data to be moved from the memory array to the register in a single clock cycle. On the next clock cycle, the data is moved from the register to the outputs. Meanwhile, a new piece of data is propagated from the memory array to the register. The net effect is a faster clock frequency with 1 additional cycle of latency. SBSRAMs are available in both single cycle deselect and double cycle deselect. Both of these varieties are compatible with the C6000 EMIF. SBSRAMs are commonly available in speed grades ranging from 100 up to 166. Above 166, SBSRAMs are commonly moving to a new I/O technology (such as HSTL or SSTL), although LVTTL devices are available at speeds up to 200. Figure 6 shows a functional block diagram of a pipeline burst synchronous SRAM and Figure 7 shows a timing diagram. TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 5

6 A /Reg B Memory Array C Reg D E Clock Reg Figure 6. Pipeline Burst Synchronous SRAM Functional Block Diagram Clock (A) (A) A A1 A2 (B) (B) B A1 A2 (C) (D) C D D1 D1 D2 D2 (E) E D1 D2 Figure 7. Pipeline Burst Synchrounous SRAM Timing Diagram 1.3 Burst Mode of SBSRAM Defined SBSRAM devices offer a feature called burst. However, the SBSRAM definition of burst is different from the C6000 definition of burst. For SBSRAM, burst refers to the operation of the SBSRAM s internal burst counter. If the internal burst counter is enabled via the ADV input as shown in Figure 8, then a single read (write) command returns (accepts) 4 words of data. If the internal burst counter is disabled (via the ADV input), then a single read (write) command returns (accepts) a single piece of data. For the C6000, bursting is defined as reading or writing a piece of data every cycle, regardless of how it is performed. Depending on the specific C6000 device, a burst to SBSRAM is performed differently. In the case that the burst feature is supported (as in C6211/C6711), a read is performed, and the SBSRAM returns 4 pieces of data. If more than 4 words are requested, then the C6211 issues another read command so that the SBSRAM continues to return data uninterrupted. The result is that data is returned on every clock cycle, resulting in a maximum throughput equal to the clock frequency. 6 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

7 In the case that the burst feature of SBSRAM is not supported (as in C6201/C6701/C6202/ C6203/C6204/C6205), a read command returns 1 word of data. If a transaction requires more than 1 word, additional read commands are issued on back-to-back clock cycles. As a result, data is returned on every clock cycle, for a maximum throughput equal to the clock frequency. (See Figure 8.) In summary, there is no performance difference between the C6x0x approach and the C6x1x approach, since data throughput is equal to the EMIF clock frequency. Burst Mode Enabled Burst Mode Disabled ADV ADV C6x1x SBSRAM C6x0x SBSRAM Figure 8. Burst Enabled vs. Burst Disabled Interface Example 1.4 Next Generation SRAM The next trend in synchronous SRAM involves improving the turnaround time between a read and a write by forcing the write data to be delayed by 1 or 2 clock cycles from the write command. This improves the overall usage of the bus since commands can be issued with fewer dead cycles, as shown in Figure 9. Late write SRAM employs a write latency of 1 cycle and a read latency of 2 cycles. As seen in Figure 9, there is 1 less dead cycle than in SBSRAM interfaces. Late write memories are used primarily as L2 cache in high performance workstations, servers, and mainframes. Although some devices are available in LVTTL I/O, the vast majority are HSTL only. Zero bus turnaround (ZBT) SRAM is also known as no bus latency (NoBL) or no turnaround RAM (NtRAM). ZBT employs a write latency of 2 cycles and a read latency of 2 cycles. As seen, this potentially results in 100% bus utilization, since a write command can follow a read command with no dead cycles inserted. ZBT seems to be the next step in synchronous SRAM for mainstream embedded and networking applications. As such, speeds up to 166 can be found with LVTTL I/O. TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 7

8 Standard SBSRAM Clock / A B Write C D A B Write C D Late Write SRAM / A B Write C D A B Write C D ZBT SRAM / A B Write C D A B Write C D Figure 9. Next Generation SRAM 2 DRAM Overview Dynamic random access memory (DRAM) uses 1 capacitor per cell for the memory array, which offers distinct advantages and disadvantages relative to SRAM. The major advantage is that since only 1 transistor per cell is used for DRAM, denser memory arrays are achievable. For example, DRAM devices are commonly available in 16 MBit and 64 MBit configurations, with densities of 128 and 256 MBits becoming more common. One disadvantage of DRAM devices is that the charge on the capacitor cell leaks over time and must be continuously refreshed. This adds additional complexity to either the DRAM itself or to the memory controller, depending on which device is responsible for refreshing the memory. DRAM features a multiplexed row/column addressing scheme in order to support the banked architecture. The multiplexed row/column addressing is an advantage in that a larger address reach is possible with fewer pins. However, additional controller complexity and latency is added since separate control cycles are required for row addressing, column addressing, and other command overhead. Figure 10 shows trends in DRAM performance. This history is somewhat more restrictive (in terms of the C6000) than the SRAM history line; that is, the only type of DRAM that can directly interface to the C6000 is SDRAM. Older memory types (such as EDO and FPM) may still be used in embedded applications, but the PC industry has fully adopted SDRAM as the memory of choice. The usage model for the C6000 is to use SDRAM in a system where large amounts of external memory are required. Although the performance is slightly lower than SBSRAM, the performance degradation is negligible for most applications. 8 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

9 C6000 Compatible (C6201 C6701, C6202, C6203) ÇÇÇÇ Rambus ÇÇÇÇÇ DDR FPM, EDO DRAM ÑÑÑÑÑÑÑ ÍÍÍÍÍÍÍ SDRAM (all configurations) ÑÑÑ ÍÍÍ ÌÌÌÌÌÌ SDRAM (4 configurations) ÌÌÌÌÌÌ Not compatible C6000 Compatible (C6201,C6701, C6202, C6203, C6204, C6205) ÍÍÍÍÍÍÍÍÍ C6000 compatible (C6211, C6711) ÏÏÏÏÏÏÏÏÏ ÇÇÇÇÇÇÇÇÇ Not planned Figure 10. DRAM Performance Trends 2.1 SDRAM SDRAM is commonly used in applications that require a large amount of memory at fast speeds. The disadvantage of SDRAM is the number of control cycles required for operation as shown in Figure 11 and Figure 12. The timing diagram in Figure 12 shows the page-miss penalty when accessing SDRAM. This occurs if the pending access is not to the currently open row (or page). In this case, the current row must be closed, then the next page is opened, and then the read command can be performed. At this point, accesses can be performed with single cycle throughput to addresses within the open page. For random accesses within the current page, no penalty is incurred. For typical SDRAM configurations, page lengths range from 256 to 1024 words. SDRAM is commonly available in 16 MBit and 64 MBit and is emerging in 128 MBit and 256 MBit densities. Speeds range from 100 to 133 for common PC configurations (thus the titles PC100, PC133). An interesting note is that a PC100 memory is commonly labeled as a -8 speed grade by memory manufacturers; that is, a 125 device is normally the speed grade that complies with the PC100 specification. On the other hand, a 7.5 speed-grade device is the speed grade that complies with the new PC133 spec. Device configurations that are targeted at the graphics market (16MBit x 16, 64 MBit x 32, ) are available in 166 version and are potentially moving up to 200. TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 9

10 /Reg Row Latch Col Latch A C Memory Array B I/O Gate E D Clock Figure 11. SDRAM Functional Block Diagram Burst Length = 1 Clock Addr B D E trp A trcd tcl DCAB Actv Bank Row Col A Col B Col C Col D C A B C D 1 Burst Addr1 Length = 4 1 DCAB Actv Bank Row Col A Figure 12. SDRAM Timing Diagram A0 A1 A2 A3 2.2 Double Rate (DDR) SDRAM The next evolutionary step in DRAM technology is double data rate (DDR) SDRAM. For this interface, commands are issued in a similar fashion to normal SDRAM. The SDRAM acknowledges commands relative to the rising edge of the primary clock. For a read, data is driven on both the rising and falling edge of the primary clock, which is equivalent to the rising edges of both primary and inverted clocks as shown in Figure 13. Similarly, for a write, the memory controller drives data on both clock edges as well. An implementation detail for DDR SDRAM is that the data and DQS (data strobe) signal propagates in the same direction for both reads and writes. The DQS signal is used as the timing reference for the DDR memory to latch write data. DQS is also used by the memory controller as the timing reference to latch read data. The advantage of this scheme is that the round trip data delay is removed from timing considerations. The only concern is the skew between the DQS signal and the data; and since these signals propagate together, the skew is minimized. DDR SDRAM is commonly available with SSTL_2 or SSTL_3 I/O technology. Speed grades range from 100 to 133, resulting in 200 and 266 throughput, respectively. 10 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

11 Clock/Clock# Addr Col A tcl DQS D0 D1 D2 D3 Figure 13. DDR SDRAM Timing Diagram 2.3 Rambus DRAM (RDRAM) The next step in DRAM technology is Rambus, which is promoted as the memory of choice for next generation PCs, although at this time it is not clear that RAMBUS will be fully adopted. Rambus offers up to 1600 Mbytes/second data throughput with a total of only 30 high speed signals (16 data). Some of the techniques used by Rambus include using a packetized command and data flow, which allows tightly interleaved control and data flow. In addition, a low voltage swing signaling scheme, called Rambus signaling level (RSL) is used. The Rambus interface also uses a technique similar to the DQS technique employed by DDR SDRAM. For Rambus, the clock signal makes a round trip path from the last RDRAM in the system towards the memory controller, then is sent back to the RDRAMs in series as shown in Figure 14. This allows upstream and downstream data to be timed relative to the appropriate clock, minimizing the skew between clock and data. In addition, the total propagation delay time from the farthest memory to the memory controller (and vice versa) can be greater than a clock period, due to the extremely low clock/data skew. Rambus Interface Memory ler RDRAM RDRAM RDRAM Vref Termination Clock Rambus Channel Figure 14. Rambus Block Diagram TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 11

12 3 FIFO Overview A FIFO (first in, first out) memory is a memory with two data buses, one on the read side and one on the write side. As the name implies, the first data in on the write side is the first data out on the read side. FIFOs are typically used to pass data between two different clock domains, since each side of the FIFO can be accessed with an independent access rate. FIFOs use an SRAM-based memory array, with additional control logic surrounding the array to keep track of the head and tail of valid data, normally called the read pointer and write pointer, respectively. (See Figure 15.) The FIFO also produces status flags, based on the difference between the read pointer and write pointer. These status flags normally include a full flag, empty flag, half-full flag, almost full flag, and almost-empty flag. Although many different types of FIFOs are available with many different features, the broad categories of FIFOs can be summarized as follows: Asynchronous Strobed Standard synchronous First word fall through (FWFT) synchronous Each of the above FIFO types is available in different varieties with a range of features. FIFO memories range from traditional asynchronous devices with 5V I/Os to 3.3V synchronous devices. Most new designs use a synchronous interface, which can operate in either standard or FWFT mode. Speed grades for synchronous devices range from 50 to 133. The most widely available are 66 devices, with 100 becoming more common. Write Write Pointer Memory Array Pointer Status Flag Logic Status Figure 15. FIFO Block Diagram 3.1 FWFT vs. Standard Synchronous FIFO The two different architectures of synchronous FIFOs are differentiated as FWFT (first write falls through) or standard. (See Figure 16.) Many devices can operate in both modes. For FWFT FIFOs, the first write falls through to the output buffer; therefore, the first read can take place by turning on the output buffer which forces the word to be driven on the read side. For typical applications, the first read is read with a 0 cycle latency, and the read command causes the next data element to propagate from the memory array to the output buffers. Since a valid piece of data is stored at the output buffer, a FWFT FIFO has D+1 valid locations (D = memory depth). 12 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

13 For standard synchronous FIFOs, the first write data resides in the memory array. The first read occurs with a 1-cycle latency, since the data has to propagate from the array to the output buffer when the read command is registered. Since the output buffer is not used as a storage location, a standard sync FIFO has D valid locations (D = memory depth). Although the two synchronous FIFO types are differentiated based on the first write cycle, the write interface is the same for both standard and FWFT FIFOs. As described, the behavior of first write only affects the read interface. Write Clock Write Write Clock W0 D0 W1 D1 R0 R1 FWFT FIFO Q0 Q1 Standard FIFO Q0 Q1 Figure 16. FWFT vs. Standard FIFO 4 EMIF Overview For current devices, the EMIF can be divided into two types: C620x/C6701 style, which includes C6201, C6202, C6203, C6204, C6205 and C6701. C6211/C6711 style The two EMIFs are designed with compatibility in mind, but there are differences between the two. The main difference is that the C620x/C6701 EMIF is clocked internally at the CPU speed, but the synchronous interfaces are limited to x the CPU clock frequency. The C6211/C6711 EMIF, however, uses an external clock input, which can be completely independent of the CPU clock frequency. Additional differences and similarities are highlighted in Table 1 and Table 2. TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 13

14 Table 1. EMIF Comparison Device Bus Width Memory Spaces per Device able Space Synchronous Clock Speed Available Memory Types C620x/ C bits 4 52 Mbytes (byte addressable) 1/2x CPU clock Asynchronous Memory (flexible programmability) SDRAM supports 16 Mbit (x8, x16), 64 Mbit (x16, x32) SBSRAM (standard pipeline burst) CE1 supports 8/16 bit ROM C6211/ C bits Mbytes (byte addressable) 1x EMIF input clock Asynchronous Memory (flexible programmability) SDRAM supports almost all configurations SBSRAM (standard pipeline burst) 8, 16, 32 bit memory width supported for all memory types in all CE spaces C6000 Next Generation 64 bits or 32 bits (16 bits) 4 (+ 4) 1024 (+ 512) Mbytes (byte addressable) 1x, 1/2x EMIF input clock Asynchronous Memory (flexible programmability) SDRAM (supports almost all configurations) Generic synchronous interface (SBSRAM, ZBT SRAM, Standard FIFOs, FWFT FIFOs, other user logic) 8, 16, 32 (64) bit memory width supported for all memory types in all CE spaces Highest performance devices may have second 16-bit wide EMIF. 14 TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology

15 Table 2. EMIF Quick Reference Guide CPU Frequency 200 C6201 C6701 C6202 C6203 C6204 C6205 C6211 C C6000 Next Generation 300 to 1 GHz EMIF Frequency Asynchronous Memory/ Asynchronous IO SBSRAM (Pipeline Burst, SCD or DCD) Flow Thru ZBT Standard Sync FIFO FWFT FIFO SDRAM (4 configurations) SDRAM (all configurations) Interface supported on Expansion Bus (XBus) 5 What s Next The current I/O technology used on C6000 devices (3.3V LVTTL I/O) is reaching a plateau at ~166 to 200 due to the inherent limitations of LVTTL I/O buffers for both the C6000 and for memory devices. Although it is tempting to rush forward with adopting a new I/O switching standard, caution must be exercised in order to ensure that the right choice is made. One of the basic limitations is that, in the near future, a 3.3V bus will be needed for most applications for interfacing to slower peripherals, such as flash, A/D and D/A converters, FIFOs, and asynchronous memory. Since most of these devices will not be pushing past the 150 mark (or even the 100 mark), they may not migrate to different I/O technologies. Another limitation is that the choice of I/O switching standards must be made with a target memory in mind. Table 3 highlights the I/O technology used on three of the most common highspeed memory interfaces, which are all different. The conclusion is that a dedicated memory bus is needed for any one of these memory types to support the specific I/O technology. This requires waiting for the specs to settle down and/or for the PC industry to declare a winner. Table 3. I/O Standards for Next Generation Memory Memory DDR SDRAM Rambus Late Write SRAM I/O Standard SSTL-2 RSL HSTL TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology 15

16 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated