Electrical Recommendations for Lattice SERDES

Transcription

1 for Lattice SERDES November 2008 Introduction Technical Note TN1114 LatticeECP2/M and LatticeSC/M SERDES integrates high-speed, differential Current Mode Logic (CML) input and output buffers which offer significant advantages in switching speed while providing improved noise immunity and limited power dissipation. Additional advantages in current-mode design include reduced voltage swing operation and significant suppression of power supply noise since the supply current is constant. The CML differential receivers and drivers incorporate various programmable features and interfaces to other CML and non-cml logic signals. Off-chip signal interface design and characteristics are the focus of this document. Detailed interfacing requirements to external high-speed devices with LVDS and LVPECL characteristics are discussed as well as the transmission line interconnections between devices which are required because of high data rates. Practical considerations related to printed circuit boards are also discussed. For more detailed PCB recommendations, refer to TN1033, High-Speed PCB Design Considerations. While nominal resistor and capacitor values are shown throughout this document, optimal values will vary in each application. HSPICE models with the interface examples are provided to tune user-specific applications. CML Buffer Overview CML buffers are used as the common interface to the SERDES PCS. Internal input and output terminations are provided to simplify board level interfacing and AC coupling capacitors are available within the CML receiver. A simplified schematic of the serial input and output buffers is shown in Figure 1. The termination resistors and AC coupling capacitors are internal to the buffer. Figure 1. CML Input and Output Buffer Structure for LatticeSC and LatticeECP2M VDDOB (VCCOB) 1.2V to 1.5V VDDIB (VCCIB) 1.2V to 1.5V 50/75/5K Zo 50/75/2K (50/60/75 /high) 5 pf VCC12 (VCCRX) Zo A An Vbias VOD typ = 500mV VOCM typ = VDDOB V (VOD typ = 500mV VOCM typ = 0.8V) VID min = 80mV VICM_DC = V VICM_AC = 0-1.5V (VID min = 100mV VICM_DC = V VICM_AC = 0-1.5V) Note: Signal or parameter names and values in paranthesis are for LatticeECP2M Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 1 tn1114_01.9

2 SERDES Power Supplies The SERDES design provides separate final stage Rx and Tx power nodes, identified as VDDIB and VDDOB, for each CML input and output buffer. These allow the receiver input termination (50, 75Ω, 2KΩ) and transmitter output termination (50, 75Ω, 5KΩ) to be biased at different levels, independent of the core VCC voltage. The Rx termination (resistor connected to VDDIB) value can vary based on design requirements and can be left to float or AC-coupled to ground. Table 1. LatticeSC and LatticeECP2M SERDES Power Supplies LatticeSC SERDES Power Supply LatticeECP2M SERDES Power Supply Nominal Value Description Power Supply Tolerance VDDIB[0-3] VCCIB[0-3] 1.2V to 1.5V CML Input Termination Voltage Supply +/-5% VDDOB[0-3] VCCOB[0-3] 1.2V to 1.5V CML Output Termination Voltage Supply +/-5% VDDAX25 VCCAX33 2.5V/3.3V CML I/O Control Logic Power Supply +/-5% VCC12 1 VCCP/VCCRX/VCCTX 1.2V SERDES/PLL Analog Supply +/-5% 1. Internal 1.2V Power Supply Voltage for Configuration Logic and FPGA PLL, SERDES PLL Power Supply Voltage and SERDES Analog Supply Voltage. VCC12 supplies the analog circuitry blocks of the SERDES. All VCC12 supply pins must be connected to a voltage supply regardless of whether the channel is used in the application. Unused channels can be powered off internally to conserve power. The VCC12 supplies should be isolated on the PCB to deliver quiet, noise-free power supplies. This supply is identified as VCC12 and is used to supply analog power nodes within the SERDES blocks. VCC12 is an analog plane within the device that is shared between the SERDES and the PLLs. There are several power supplies associated with the SERDES/PCS of the device. These supplies need to be addressed based on the design. As previously mentioned, the VCC12 analog supply needs to be isolated from any other noise on the 1.2V PCB supply. All VCC12 pins must be connected regardless of the design. All VDDAX25 supply pins need to be connected to 2.5V. The VDDIB and VDDOB are used to supply the input and output terminations used to match the transmission line impedance. These supplies only need to be connected for the channels used in a design. Similarly the HDIN and HDOUT pins can be left unconnected in designs not using particular channels. In instances where PCB power distribution cannot be sufficiency bypassed, the designer might be tempted to use several different active devices, such as voltage regulators, to serve as the decoupling stages for these power supplies. Supplying DC power to each stage through a separate inductor or choke, while also bypassing to ground effectively accomplishes the same results without the use of active components. In these passive filter network schemes, the choke offers a high impedance path to any errant signals or noise between stages, while offering a very low resistance path to the DC power. The example in Figure 2 shows a method for isolating the SERDES analog supplies from the digital noise of the PCB supply. This technique should be used for the VCC12 power stages on the board. 2

3 Figure 2. Passive Filter Network Quiet Supply Example VCC12 Power Stage 1.2V Board Supply T VCC12 22pF --> 1000pF 1 per pin Located under device 10nF 100nF 10nF 100nF 1µF 10-22µF Decoupling caps distributed evenly as close to device as possible Note: The use of Passive-Filter Networks is not recommended for low-impedance power supplies such as VCC Core. High Q, minimum inductance decoupling caps SMT or chip capacitors made of ceramic are best. Use several size caps in parallel, e.g., 1ufd, 0.1ufd, 0.01ufd, etc. The reason for this is that each cap with its associated inductance will have its own series resonant frequency. Therefore, it is best to have a wide range of capacitor values to provide an overall lower power supply impedance over the effective frequency range. Use high Q low R Ferrite Bead The down-side of ferrite is that it will change inductance as the current or flux changes. In large currents, it can saturate. However, by correct component choice and understanding the frequency, AC and DC current requirements is important in choosing the correct inductor. A good choice is a bead from Murata, BLM41PG471SN1L. Other options of power distribution systems should also be explored to gain an understanding the sources of power supply noise and voltage ripple. Using the before-mentioned passive filter techniques is a good start to post filter the ripple generated by the power supplies. The filter must sufficiently attenuate the low-frequency harmonics of the primary switching supply so an understanding of the specifics of what frequency needs to be cut-off by the postsupply filter is important. A specific recommendation is to build an LC passive-network that will cut-off a decade below the primary frequency. Typically, high-frequency noise generated by supplies can be easily attenuated. This can commonly be achieved with the use of an additional ceramic decoupling capacitors placed after the post-filter as shown in Figure 2. Both linear and switching voltage regulators have advantages and disadvantages when used in Lattice FPGA systems. Depending on the requirements of the system either may be a suitable choice. Switching regulators are a better choice when the input voltage is less than or much greater than the desired output, when multiple outputs are desired, and when power dissipation must be kept low. There's no argument that switching regulators are more efficient than low drop-out regulators (LDO). A switching regulator can exhibit 90% efficiency versus 36% for an LDO. However a switching regulator may not always meet all the critical needs of the design. Switching Voltage Regulators have these advantages: High Efficiency (reduces source power requirements and need for heat sinking) Capable of handling higher power densities Single or multiple output voltages, greater or less than the input voltage. They have these disadvantages: Greater output noise/ripple, especially at the switching frequency Slower transient recovery time 3

4 Switching regulators are well suited for powering the FPGA core and I/O power supplies where high power requirements play a factor in the board power design. The high efficiency reduces heat and power concerns that linear regulators exhibit. However the finite ripple generated by the switching regulators is not desirable for use with the sensitive analog power supply VCC12. Using post supply filter networks can attenuate the unwanted ripple. Typically, the added noise on the output is at the switching frequency. If this frequency is below the bandwidth of the SERDES or PLLs it will directly affect the associated component jitter. Otherwise, it will be filtered. For SERDES connections, the receiver being transmitted to will also filter low frequency jitter, as generated by the switching regulator. In general, linear regulators are a better choice when the input voltage is a few volts higher than the output but not closer than the regulator s dropout voltage, and when the load current is less than about 3A. Linear Voltage Regulators have these advantages: Simple and small board application Low output ripple voltage Excellent line and load regulation Fast response time to load or line changes Low electromagnetic interference (EMI). They have these disadvantages: Low efficiency, especially with higher input voltages Large space requirement if heatsink is needed. This type of regulation is desired for the quiet analog supplies used in the PLLs and SERDES of the SERDES devices. These regulators have much better noise properties and faster transient response. They offer a good amount of noise rejection and generate no ripple. They work well to supply the lower power draw from the analog circuitry of the FPGA. Using a linear regulator to build quiet supplies provides the analog portions of the FPGA the needed power supply requirements. Figure 3. Combined Switching and Linear Regulator Power Scheme Intermediate Power Bus 2.5/3.3V Switching Regulator 1.2V Switching Regulator 1.2V Linear Regulator VDDIB VDDOB VCC12 VCCIO VCC Core VDDAX25 VCCAUX Combining the use of a switching regulator with a linear regulator is a way to reduce board current drain. An example of this is shown in Figure 3. In this design, a switching regulator provides the correct voltage levels while the 4

5 use of the linear regulator filters the switching noise. Note that the correct power supply decoupling and filtering is needed.switching regulators are most efficient when they're driving the loads for which they were designed. When the output voltage is not heavily loaded, however, the current needed to keep the switching regulator switching becomes more problematic. A linear regulator can be more efficient under these conditions. Using this combination of regulators is helpful to meet the requirements of high-performance FPGA designs that require distribution of multiple power supplies. This strategy will meet the needs of both the power and performance demands of the FPGA system. PCB Design Considerations Many existing documents provide guidance to prevent the pitfalls of PCB designs with SERDES based and highspeed I/O designs. There are still a few underlying issues that often go misunderstood or overlooked. The interaction of an FPGA s Simultaneously Switching Outputs (SSO) can cause many system level issues that lead to degradation of the overall SERDES performance. LatticeSC PURESPEED I/Os have enabled the building of many complex systems. These abundant and flexible FPGA I/Os include many speed and signal interface features such as drive strength and termination options. SSO is noise due to multiple I/O pins switching at the same time. These changing currents induce voltages inadvertently affecting other sensitive stages of the device. The LatticeSC devices include many innovative methods to overcome specific device and package sensitivities to SSO and in-package cross talk. Mostly this can be corrected by minimizing the total inductance of return paths similar to what has been done in LatticeSC package design. PCB designs need to apply careful techniques to reduce the likelihood of PCB related crosstalk and SSO that degrades system performance. The LatticeECP2M devices also employ many of the same techniques. The leading causes of PCB related SERDES crosstalk are related to FPGA outputs located in close proximity to the sensitive SERDES power supplies. These supplies require cautious board layout to insure noise immunity to the switching noise generated by FPGA outputs. Guidelines have already been provided to build quiet filtered supplies for the VCC12, however robust PCB layout is required to insure that noise does not infiltrate into these analog supplies. Although coupling has been reduced in the device packages of the LatticeSC devices where little crosstalk is generated, the vias within the BGA field of the PCB board can cause significant noise injection from any I/O pin adjacent to SERDES data, reference clock, and power pins as well as other critical I/O pins such as clock signals. Many PCB designs include adjacent structures that can create cross coupling of the FPGA I/O to the VCC12 analog supplies. The crosstalk created by via-to-via coupling can cause noise to attack the analog supplies. The noise aggressor is the culprit SSO pin potentially impacting the supplies and circumventing any provided PCB supply filtering. This coupled noise on the PCB from the aggressor can cause the SERDES performance to degrade dramatically. Enabling amplitude boost mode of the SERDES will typically improve noise immunity for both the Rx and Tx portions of the SERDES, especially noted at rates above 2.7Gbps. The system designer can mitigate this problem by implementing differential signaling standards to and from the FPGA rather than using single-ended buffers. Where single-ended signals must be used, the PCB designer must pay attention to via and signal placement when in close proximity to the analog power supplies and avoid routing the single-ended buses near the high-speed SERDES channels. It is a better practice to use the I/O pins in closer proximity of SERDES data, reference clock, and analog power pins for static control signals or signals with lowdrive strength, slow-slew rate, and limited capacitive loading (terminated signaling also improves this situation). The suggested pins to avoid for this purpose, if possible, are shown in Table 2 for each LatticeSC package. For LatticeECP2/M devices, see TN1159, LatticeECP2/M Pin Assignment Recommendations. 5

6 Table 2. LatticeSC PCB Aggressor I/O Pins Device Package Package Type Aggressive I/O Pins 1 SC fpBGA Wire-bond E7 SC15/SC fpBGA Wire-bond F22 2 SC25/SC fpBGA Flip Chip D2, E2, F2, D31, E31, F31 SC40/SC80/SC fpBGA Flip Chip D2, D33, F14, F21, G14, G21,H13, H14, H21, H22 SC80/SC fpBGA Flip Chip The best-case scenario is to drive these signals with a soft ground. Connecting an active output buffer and driving a low signal builds an effective soft ground. This pin should be connected to the ground plane of the PCB. This connection serves as a return path and helps create additional noise immunity. Pins are listed that will possibly influence with the analog supplies on the board as well as pins that are adjacent to high-speed SERDES data pin that could get coupled on the PCB. Additional recommendations include: Do not route the VCC12 connections as traces. Rather, use planes or very wide bus structures on other nonadjacent layers to high-speed signal routing and keep them shielded by adjacent ground layers. Blind-vias are better than through-hole vias for making connection to the I/Os. This limits the amount of coupling between vias. If through-hole vias are required, place high frequency decoupling capacitors directly beneath the device adjacent to the VCC12 power via. Maintaining the greatest distance between single-ended I/O and the analog supplies is always required. It is always best to keep the analog supplies and the single-ended traces separated vertically in the PCB stack-up when working in close proximity on the board. Figure 4. PCB Via Stack Up Detail F27, G1, G2, G3, J17, J18, G40, G41, G42, K18, M9, N9, N10, N33, N34, M34 1. I/O pins are potential PCB coupled noise sources to analog supplies and recommendations should be followed. 2. F22 is a dual function pin. When using SPI Flash, F22 is used to source the SPI Flash chip select and should not be connected to soft ground. sysio sysio LatticeSC BGA Device VCC12 Soft Ground BGA Pad/ Via Detail Blind Via Through ViaS Decoupling Capacitor In Figure 4, coupling is caused by the mutual inductance occurring in the area between the I/O signal path and the VCC12 via. Blinding the signal via and reducing the stub minimizes the capacitive coupling effect. Following recommendations designed to minimize this effect reduces the coupling. I/O pins having close proximity to the VCC12 pins vary in different packages and packaging variations also influences noise immunity. The issues related to these locations are due to the way the pins escape or route away from the device. Determining the best escape route from the device s BGA field is critical to minimizing the effects of coupled noise on the board. When possible, do not use specified PURESPEED I/Os directly adjacent to an analog designated VCC12 power pin. Routing should also be kept away from VCC12 power vias when escaping from the device. 6

7 It is best practice to shield any routing traces from the VCC12 connections. This can be done with power and ground planes (ground planes preferred) above and below as well as ground shield routing on the same layer. Carefully place same layer shielding as to not create edge-coupling issues. Typically 3W spacing is required to prevent edge coupling. Consider keeping VCC12 on first possible power layer closest to the device side where is can be shielded by a ground layer. High speed I/O signals should escape on the signal layer non-adjacent to the analog VCC12 supply. High-speed I/O signals should be routed after all SERDES and analog power is routed. If the VCC12 vias are blinded, this restriction can be relaxed as long as the VCC12 power plane is kept close to the device side of the board as possible. Special Considerations to Reduce Tx Jitter and Increase Jitter Tolerance for the LatticeSC For wire-bond packages, it is also a good practice at any speed to limit the number of single-ended outputs simultaneously switching outputs in I/O banks adjacent to the SERDES channels. For the 256-fpBGA, this is I/O Bank #1 and for the 900-fpBGA packages, these are I/O Banks #1, #2, and #7. This becomes a priority as the SERDES rate increases. At SERDES speeds above 3.2Gbps in wire-bond packages, the single-ended outputs in Bank #1 should be limited to configuration signals (including up to 8-bit MPI interface connections for the 900-fpBGA). For Banks #2 and #7, the number of single-ended outputs should be limited to 8 or less in the 900-fpBGA. For the 256-fpBGA package use Bank #1 for: Differential I/O or static configuration and control signals Single ended inputs Only if necessary, single ended outputs can be used but should be limited to a 4mA drive with slewlim mode enabled For the 900-fpBGA package, use Banks #1, #2 and #7 for: MPI pins (8-bit only) Differential I/O or static configuration and control signals Single ended inputs Only if necessary, single ended outputs can be used but should be limited to a 4mA drive with slewlim enabled It is less critical to limit the number of single-ended outputs in flip-chip packages. However limiting the number of outputs, reducing drive-strength, enabling slew limited mode and reducing the capacitive loads in Banks #1, #2, and #7 will also have a small effect on improving SERDES performance. At SERDES speeds greater than 3.2Gbps this effect becomes larger. SERDES External Interfaces The high speed of the serial SERDES I/O makes understanding the interface parameters especially important to the user. Proper interpretation of the parameters is needed for successful integration within a system. Signal interconnection performance, reliability and integrity are closely tied to these characteristics and their variation limits. This section attempts to summarize and discuss critical serial buffer interface parameters. Correctly specifying the buffer I/O is a complex process. Methods used include extensive SPICE simulation and laboratory measurements. The official specification listing for the SERDES should be obtained from the LatticeSC/M Family flexipcs Data Sheet. 7

8 All interconnection circuits described in this section should use matched length pairs of 50Ω transmission lines. Each should provide characteristic impedance termination of the line to provide maximum signal bandwidth. 50Ω, an industry standard, provides maximum compatibility and suits present printed circuit board technology interconnections well, for circuit pack and backplane applications. It is also consistent with 100Ω balanced transmission line interfaces, which are becoming popular for high bandwidth shielded pair cable connections. However, for ease of integration into 75Ω impedance characteristic systems such as video, the Lattice SERDES devices are optimized to terminate directly in both 50Ω and 75Ω applications. DC Coupling The SERDES high-speed serial buffers are optimized to interface externally to other similar buffers. For some interfaces, a direct interconnection of Lattice SERDES buffers requires no external devices or components at the PCB level. In instances where an interface has the same ground potential on the same board or system, DC coupling directly connects the components without any coupling capacitors. The advantages of DC coupling include simplified board design and no DC wander issues. It is also useful in all coded-data streams including SONET and NRZ data applications. Systems with a need for wide bandwidth or where DC unbalanced code is used, can take advantage of DC coupling. AC Coupling In some high-speed applications, AC coupling is preferred for various reasons. Lattice CML receivers integrate AC coupling capacitors. AC coupling is used to change the common-mode voltage level when interconnecting different physical layers. A capacitor removes the DC component of the signal (common-mode voltage), while passing along the AC component, or voltage swing. The resistors to RxTerm in Figure 1 represent the internal biasing structure used to set the common-mode voltage on the line side of the AC coupling capacitor. Biasing structures are either part of the internal biasing of the receiver or an external resistor pull-up and/or pull-down network. Interconnection to other vendor s non-cml buffers is possible, but may require the addition of some passive components. AC coupling generates baseline wander in high-speed serial data transmission because it is non-dc balanced. ANSI fiber channel 8B/10B encoded data is an example of DC-balanced signaling. The addition of external capacitors (Cext) for AC coupling requires some careful consideration. The designer should select a capacitor knowing the requirements of the system. It is important to minimize the pattern-dependent jitter associated with the low-frequency cutoff of the AC coupling network. When NRZ data containing long strings of identical 1 s or 0 s is applied to this high-pass filter, a voltage droop occurs, resulting in low-frequency, pattern-dependent jitter (PDJ). When using off-chip capacitors (Cext), it is possible to use both internal AC coupling or DC coupling modes. For AC coupling modes it is suggested that when Cext is connected in series to the internal AC coupling Cap of 5pF (typical), Cext > 100times +/- 5% tolerance. When off-chip AC coupling is required, recommended capacitor values are shown in Table 3. Table 3. Off-chip AC Coupling Capacitor LVDS Device Interface Description Min. Max. Units 8b/10b (XAUI) 4.7 nf SONET 100 nf PCI-Express nf LVDS, like CML, is intended for low-voltage differential signal point-to-point transmission. Many commercial LVDS devices provide internal 100Ω input terminations. They are typically intended for use with 100Ω characteristic impedance transmission line connections. Standard LVDS is specified with about 3 ma signal-current that translates to a nominal signal voltage of approximately 600 mvp-p (differential). Low power LVDS provides about 2 ma signal current. LVDS input and output parameters are shown in Table 4, as specified in the LVDS Standard. 8

9 Table 4. LVDS Specifications Symbol Parameter Conditions Min Max Units Driver Specifications VOH Output voltage high Rload (diff) = 100Ω 1475 mv VOL Output voltage low Rload (diff) = 100Ω 925 mv VOD Output differential voltage Rload (diff) = 100Ω mv Ro Output impedance, single ended Vcm = 1.0V to 1.4V Ω Receiver Specifications Vi Input voltage range mv Vidth Input differential threshold mv Vhyst Input differential hysteresis 25 mv Rin Receiver differential input impedance Ω Within common LVDS receivers, an internal or external input differential termination of 100Ω is typically needed between the P and N input ports. This termination resistor is usually floating with respect to ground. In the SER- DES CML receiver, the differential input termination resistor is center-tapped and AC coupled to ground or left floating. VDDIB can also be connected to a power supply equal to the common-mode level required for proper operation of the output buffer. In a common LVDS-to-CML application, a simple direct interface can be used in many applications. The Lattice CML output drivers and input receivers are internally terminated to 50Ω in this application. Figure 5 illustrates a recommended interface between Lattice CML buffers and commercial LVDS input and output buffers. This interface requires no external components utilizing the internal CML features. The simulation results of the interface are plotted in Figure 6. 9

10 Figure 5. DC-Coupled CML to LVDS Interface Diagram VDDOB (VCCOB) 1.2V to 1.5V 50 Zo = 50 Zo = CML Driver VOD default = 500mV VOCM = VDDOB V (VOD default = 500mV VOCM typ = 0.8V) VID min = 100mV VICM_DC = 0-2.4V LVDS Receiver VDDIB (VCCIB) 1.2V to 1.5V 50 Zo = 50 Zo = 50 CML Receiver VID min = 80mV VICM = V (VID min = 100mV VICM = V) VOD = mV VOCM = 1.2V LVDS Driver 10

11 Figure 6. Lattice CML Driver to LVDS Receiver Simulation Higher common mode noise tolerance may be achieved with alternate AC-coupled LVDS driver to SERDES receiver connection. Shown in Figure 7. This will increase the receiver tolerance to common-mode input noise voltage and provide a higher tolerance range to common-mode and system and ground noise 11

12 Figure 7. AC-Coupled LVDS Driver to CML Receiver Interface VDDOB (VCCOB) 1.2V to 1.5V VID min = 100mV VICM_DC = 0-2.4V 2.5V 50 Zo = uF Zo = CML Driver LVDS Receiver VDDIB (VCCIB) = 1.2V to 1.5V VCC12 (VCCRX) uF Zo = 50 Zo = 50 CML Receiver Internally AC Coupled LVDS Driver LVPECL Device Interface LVPECL is a differential I/O standard that requires a pair of signal lines for each channel. It is used in longer-haul electrical transmission. The differential transmission scheme is less susceptible to common-mode noise than single-ended transmission methods. LVPECL standards require external termination resistors to reduce signal reflection. The standard voltage swing for the differential pair is approximately 850mV, and the typical LVPECL VCC is 3.3V. 12

13 Table 5. Typical LVPECL Specifications Voh Vol Symbol Parameter Conditions Min Max Units Output voltage high Output voltage low Outputs terminated with 50Ω to Vcco - 2.0V Outputs terminated with 50Ω to Vcco - 2.0V mv mv Vod Output differential voltage Outputs terminated with 50Ω to Vcco - 2.0V mv Ro Output impedance, single ended Vcm =1.0V to 1.4V 3 10 Ω Vi Input voltage range, common-mode < 500mVp-p > 500mVp-p Vin-diff Input voltage range, differential mode 200 >2000 mvp-p Iih Input HIGH current -150 µa Iil Input LOW current µa The circuit in Figure 8 minimizes external components and provides DC signal coupling. The same voltage level of the SERDES VDDOB supply is used at the LVPECL input to bias the two 50Ω termination resistors, which characteristically terminate the transmission lines used for interconnection. A higher VDDOB value of 1.5V is preferred here to better align signal voltages. The simulation results are shown in Figure 9. The LVPECL driver output bias current flows through the series 62Ω resistors and the SERDES input internal 50Ω termination resistors. This configuration provides the voltage offset and attenuation required for proper interface to the SERDES receiver. It also provides the matched transmission line termination for the interconnection. An AC-coupled solution can be applied as shown in Figure 10. This scenario allows higher impedance termination at LVPECL Rx end, without causing signal distortion. Figure 11 shows the results of the simulation V 13

14 Figure 8. DC-Coupled CML to LVPECL Interface Diagram VDDOB = 1.2V to 1.5V 1.2V to 1.5V R1=50Ω R2=50Ω CML Driver 3.3V LVPECL Rx Input Zo=50 W-element lossy T-line model VDDIB=1.5V CML Receiver 62Ω 62Ω 3.3V LVPECL Tx Output 50Ω 50Ω Zo=50Ω W-element lossy T-line model Figure 9. DC-Coupled CML to LVPECL Simulation 14

15 Figure 10. AC-Coupled CML to LVPECL Interface Diagram External to Device VDDOB = 1.5V 3.3V 50Ω 50Ω 82Ω 82Ω V LVPECL Rx Input CML Driver Zo=50Ω W-element lossy T-line model 120Ω 120Ω External to Device VDDIB = 1.2V C1 3.3V LVPECL Tx Output R1=112Ω 0.01 to 0.1µFd (typical) C2 Zo=50Ω W-element lossy T-line model R2=112Ω CML Receiver Int. 50Ω Int. AC Coupling Figure 11. AC-Coupled CML to LVPECL Simulation 15

16 PCI Express Device Interface At the electrical level, PCI Express utilizes two uni-directional low voltage differential signaling (LVDS) pairs at 2.5Gbps for each lane. Transmit and receive are separate differential pairs, for a total of four data wires per lane. The Lattice CML buffers interface well with LVDS, thus allowing interconnection to PCI Express buses. An input receiver with programmable equalization and output transmitters with programmable pre-emphasis permits optimization of the link. The PCI Express specification requires that the differential line must be common mode terminated at the receiving end. Each link requires a termination resistor at the far (receiver) end. The nominal resistor values used are 100 ohms. This is accomplished by using the embedded termination features of the CML inputs as shown in Figure 12. The specification requires AC coupling capacitors (CTX) on the transmit side of the link. This eliminates potential common-mode bias mismatches between transmit and receive devices. The capacitors must be added external to the Lattice CML outputs. Table 6. Differential PCI Express Specifications Symbol Parameter Min. Nom. Max. Units Comments Location Z TX-DIFF-DC Z RX-DIFF-DC DC Differential TX Impedance DC Differential Input Impedance Figure 12. PCI Express Application Termination Ohm TX DC differential mode low impedance. ZTX-DIFF-DC is the small signal resistance of the transmitter measured at a DC operating point that is equivalent to that established by connecting a 100 Ohm resistor from D+ and D- while the TX is driving a static logic one or logic zero Ohm RX DC differential mode impedance during all LTSSM states. When transmitting from a Fundamental Reset to Detect, (the initial state of the LTSSM), there is a 5ms transition time before receiver termination values must be met on all un-configured lanes of a port. C TX AC Coupling Capacitor nf All transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. Internal on chip Internal on chip External to Lattice device VDDOB = 1.2V to 1.5V VDD1B = 1.2V to 1.5V VDDIB V TX-DIFF-DC 75 to 200nF per PCIe Spec V RX-DIFF-DC CML Driver Zo=50Ω CML Receiver External to Lattice Device 16

17 Interfacing to Reference Clock CML Buffers Some applications may require a reference clock interface. Interfacing to LVPECL requires external components as shown in the following figures. These show recommended configurations for Differential LVPECL driving CML, Single Ended PECL driving CML (DC coupled), and Single Ended LPECL driving CML (AC coupled with either Receiver ended or Source ended termination). Input reference clock levels should have a 500mV minimum differential input swing to permit the best performance for the SERDES. LVPECL signalling works well as an input reference clock to the SERDES. These levels will achieve full-swing input rise and produce low jitter. A 100-ohm differential input termination should be located very close to the true (P) and complimentary (N) inputs of the SER- DES reference clock. The best practice is to use two center-tapped 50-ohm resistors with an AC-coupled centertap to ground. The two 50-ohm resistors have two functions: the DC current loop for the LVPECL and match-resistors for the CML input buffers. The resistors are external to the device for LatticeSC/M. Figure 13. CML Reference Clock Input Buffer For LatticeSC Devices 1.2V REFCLKP 2K 5pF 2K 2K 2K REFCLKN 5pF Figure: ## CML Reference Clock Input Buffer For Lattice SC Device Figure 14. CML Reference Clock Input Buffer For LatticeECP2M Devices 1.2V REFCLKP 50-ohm 2K 5pF 2K REFCLKN 50-ohm 2K 5pF 2K 17

18 Figure 15. Reference Clock Buffer with Internal DC Coupling VCC LVPECL VCC 130-ohm Term 130-ohm Term 82-ohm Term 82-ohm Term 62-ohm 62-ohm 10nF 10nF + 50-ohm 50-ohm - Required for LatticeSC Device REF CLK Internal DC-Coupled Figure 16. Reference Clock Buffer with Internal AC Coupling VCC LVPECL VCC 130-ohm Term 130-ohm Term 82-ohm Term 82-ohm Term 62-ohm 62-ohm + 50-ohm 50-ohm - Required for LatticeSC Device REF CLK Internal AC-Coupled Figure 17. Single Ended PECL Driving CML Reference Clock Buffer (DC) VDD = 3.3 V VDD = 1.2 V 62 Zo = 50 Transmission Line 3.3 V LVPECL Reference Clock CML Buffer μ Reference clock buffer set to AC Coupling 18

19 Figure 18. Single Ended PECL Driving CML Reference Clock Buffer (AC, Receiver End Termination) 3.3 V VDD = 3.3 V 120 VDD = 1.2 V 120 Zo = 50 Transmission Line 0.1 μ 3.3 V LVPECL Reference Clock CML Buffer μ Reference clock buffer set to DC Coupling Figure 19. Single Ended PECL Driving CML Reference Clock Buffer (AC, Source End Termination) 3.3 V VDD = 3.3 V 120 VDD = 1.2 V 120 Zo = 50 Transmission Line 0.1 μ 3.3 V LVPECL Reference Clock CML Buffer μ Reference clock buffer set to DC Coupling Simulation Usage Details Analog simulation of interface circuits is a very useful part of the design process. Simple interfaces can be simulated using HSPICE models for the CML buffers that are available from Lattice. Two 50Ω ideal transmission lines of matched length can be provided between the SERDES and the interconnected device, representing PCB traces. As shown throughout this document, a random 622 Mbps digital signal pattern was used in the simulation to drive the SERDES buffer and the resulting signal voltage waveforms can be predicted by simulation. Device package parasitic-elements can be included. Other parameters and conditions assumed were nominal IC processing parameters, nominal supply voltage and room temperature Conclusion This document discusses the general termination and interface interconnections of Lattice SERDES devices. The use of Current Mode Logic (CML) input and output buffer structures and their capabilities to interface with other CML and non-cml devices was also discussed. Lattice SERDES devices offer a variety of input and output terminations that offer a reduction in external components. 19

20 References LatticeSC/M Family Data Sheet LatticeSC/M Family flexipcs Data Sheet LatticeECP2/M Family Data Sheet TN1033, High-Speed PCB Design Considerations TN1124, LatticeECP2M SERDES/PCS Usage Guide TN1159, LatticeECP2/M Pin Assignment Recommendations isplever Software Documentation Technical Support Assistance Hotline: LATTICE (North America) (Outside North America) Internet: Revision History Date Version Change Summary July Initial release. December Added discussion about Switching Voltage Regulators and Linear Voltage Regulators text section. PCI Express Application Termination figure updated. April Added additional recommendations for PCB layout for LatticeSC. June Added footnote 1 to LatticeSC and LatticeECP2M SERDES Power Supplies table. July Updated Interfacing to Reference Clock CML Buffers section. January Updated Interfacing to Reference Clock CML Buffers section. January Updated PCI Express Device Interface section. June Added footnote to LatticeSC PCB Aggressor I/O Pins table. Added a reference to TN1159 for LatticeECP2/M pin assigment information. Updated Differential LVPECL Driving CML Reference Clock Buffer (DC) figure and added a new figure after that (Figure 13 to to illustrate CML buffers. August LatticeECP2/M parameter names and values are corrected per data sheet. November Added a note to Passive Filter Network Quiet Supply Example figure. Added new figures showing CML Ref Clock Input Buffers for LatticeSCM and LatticeECP2M. 20

21 Appendix A. LatticeSC Devices An external calibration resistor is connected between the RESP pin and RESPN or between the RESP pins and board ground for packages not offering the dedicated RESPN pin. Each upper corner requires this resistor, so a maximum of two resistors are required per device. The value of the external resistor, 4.02KΩ, is an industry standard EIA E96 series value for 1% resistors. This circuitry also requires core VCC to be present and generates the VBIAS shown in Figure 20. Figure 20. RESP Connection RESP Pin RESP Pin 4 Kohm 4 Kohm RESPN Pin Buffer Description Table 7 describes input buffer parameters and characteristics that are needed for a typical application interface to other devices. Table 7. Input Buffer Parameters 1 Input Buffer Parameter Min. Typ. Max. Units Input swing (sensitivity) 2 80 mv p-p differential Input levels VSS VCC V V Input common mode range (DC coupled) 0.6 VCC12 V Input common mode range (AC coupled) 3, 4 Note 3 Note 3 V Input termination (single-ended) 5 50/75/2K Ω Return loss 6 Package dependent 1. Updated information can be found in the device data sheet. 2. Receiver equalization settings are provided, +6dB, +12dB. 3. When AC coupled, the input common mode range is determined by: input level min + (input peak to peak swing)/2 input common mode voltage input level max - (input peak to peak swing)/2. 4. AC coupling can be used to interface to LVPECL and LVDS. 5. The tolerance on these impedances is determined by the return loss specification. The default value for the impedance is 2KΩ. 6. Return loss, 18dB minimum without package for f 1.7GHz in the 50Ω configuration. This number allows for 3dB of additional degradation due to packaging effects. 21

22 Table 8. Output Buffer Parameters 1 Output Buffer Parameter Min. Typ. Max. Units Output swing, default setting 2, 3-15% % mv p-p differential Output swing, -12.5% setting 2, 3-15% % mv p-p differential Output swing, -25% setting 2, 3-15% % mv p-p differential Output swing, +12.5% setting 2, 3-15% % mv p-p differential Output common mode voltage VDDOB VDDOB VDDOB V Rise and fall times, 20% to 80% ps Output impedance (single-ended) 4 50/75/5K Ω Return Loss 5 Package Dependent 1. Updated information can be found in the device data sheet. 2. Output swing measured with bias-t network attached. Expect 20-30% reduction in amplitude when driving into AC coupled terminations. 3. Four transmitter pre-emphasis settings are provided, 0%, 17%, 33%, and 50%. 4. The tolerance on these impedances is determined by the return loss specification. 5. Return loss, 18dB minimum for f <= 1.7GHz in the 50Ω configuration. This number allows for 3dB of additional degradation due to packaging effects. 22

23 Appendix B. LatticeECP2M Devices Buffer Description Table 9 describes input buffer parameters and characteristics that are needed for a typical application interface to other devices. Table 9. Input Buffer Parameters Parameter Min. Typ. Max. Units Input swing sensitivity, differential 100 mvp-p Input level 0 V CCRX V Input common mode range (DC coupled) 0.5 V CCRX V Input common mode range (AC coupled) V Input termination (single-ended) 50/60/75/High Ohm Return loss 9 db 1. When AC coupled, the input common mode range is determined by: input level min + (input peak to peak swing)/2 < input common mode volgate < input level max - (input peak to peak swing)/2 Table 10 describes the output buffer parameters and characteristics necessary for a typical application interface to other devices. Table 10. Output Buffer Parameters Parameter Min. Typ. Max. Units Output swing, differential, default setting 1000 mvp-p Output common mode range (DC coupled) 0.8 V Rise and fall times (20% to 80%) 70 ps Output termination (single-ended) 50/75/5K Ohm Return loss 9 db 23