SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices

Transcription

1 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices May 2008, version 1.0 Application Note 518 Introduction Stratix III device family are one of the most architecturally advanced, high performance, and low power FPGAs available in the market place. Stratix III devices contain dedicated circuitry for supporting differential standards such as LVDS at various speeds including 1.25 Gbps. The high-speed LVDS I/Os of Stratix III devices support many high-speed networking, communications I/O interconnect standards, and applications including Serial Gigabit Media Independent Interface (SGMII). Support of SGMII on the LVDS I/Os allows for multi-port Gigabit Ethernet system implementations that require high port counts, low power, and lower cost. SGMII systems can be implemented with the soft-cdr mode of Stratix III FPGAs. This application note addresses soft-cdr mode in Stratix III devices and different aspects of SGMII implementation using this mode, as well as: Typical SGMII applications High-speed interface circuit requirements Soft-CDR architecture Soft-CDR mode clocking Hardware blocks required for SGMII PCS implementation Results Altera provides complete SGMII solutions through the Stratix III LVDS hard macro used in soft-cdr mode and TSE MegaCore, which implements the PCS and MAC functionality. Altera Corporation 1 AN

2 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Typical SGMII Interfaces Using Stratix III Devices SGMII is a standardized interface (refer to Cisco System s proprietary specification document Serial-GMII Specification Revision 1.7) designed to provide connectivity between a physical layer device (PHY) that has serializer/deserializer (SERDES) capabilities and an ethernet media access controller device (MAC). Figure 1 shows generic SGMII System Connectivity. Figure 1. Generic SGMII System Connectivity Optical cable 1000 Base-LX 1000 Base-SX SFP (optical) 0.01uF Port 1 AC coupled, 1.25 Gbps SGMII PHY (interface device) AC/DC coupled SGMII Host Processor Copper cable 10/ Base-T RJ45 SFP (optical) 0.01uF Port 16/24/32/48 Magnetics PHY SFP (copper) 0.01uF OR SGMII AC Coupled Backplane Driver AC/DC coupled Slot Slot Switch Port 1 MAC Slot RJ45 Magnetics PHY SFP (copper) 0.01uF BACKPLANE CHASSIS Port 16/24/32/48 OR Copper cable 10/ Base-T RJ45 Magnetics Port 1 PHY SGMII AC/DC Coupled RJ45 Magnetics PHY Port 16/24/32/48 Typically 16 to 48 full duplex ports on a single "Line Card" LINE CARDS Stratix III Soft-CDR Interfacing with an Optical SFP Transceiver You can easily implement SGMII connectivity with a Stratix III device. This device supports SGMII interfacing using LVDS hard macros on the transmit side and the LVDS hard macro configured in soft-cdr mode on the receive side. The following are examples of typical SGMII systems. As shown in Figure 2, Stratix III devices provide connectivity between a gigabit ethernet (small form factor pluggable [SFP] optical module) port, a host processor, and a backplane driver on a line card. Stratix III devices also support a wide range of interfaces with other devices on a typical line card. 2 Altera Corporation

3 Typical SGMII Interfaces Using Stratix III Devices Figure 2. SGMII Connectivity with a Stratix III Device and Optical SFP Host Processor Optical cable 1000Base-LX 1000 Base-SX SFP (optical) 0.01uF Port 1 AC coupled, 1.25 Gbps SGMII link Port 1 SFP (optical) 0.01uF Port 16/24/32/48 Port 16/24/32/ Stratix III 3 Backplane Driver AC/DC coupled 4 Slot Slot Switch Typically 16 to 48 full duplex ports on a single "Line Card" 0.01uF Slot BACKPLANE CHASSIS LINE CARDS The various interface points in Figure 2 are marked with red numbers from 1 to 4. The interface marked 1 is typically AC coupled on the SFP module itself with a typical capacitor value of 0.01 uf (refer to Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement). Interfaces 2 through 4 can be AC or DC coupled, depending on an individual system s connection feasibility. The LVDS differential I/O electrical parameters of Stratix III devices are included in this application note to facilitate an SGMII link design. Stratix III Soft-CDR Interfacing with a Copper SFP Transceiver Figure 3 shows typical SGMII system connectivity using a Stratix III device connected to a copper SFP module. Figure 3. SGMII Connectivity Using Stratix III Device with Copper SFP Host Processor Copper cable 10/100/1000Base-T RJ45 Magnetics PHY SFP (copper) 0.01uF Port 1 RJ45 Magnetics PHY SFP (copper) 0.01uF Port 16/24/32/48 AC coupled, 1.25 Gbps SGMII link 1 Port 1 Port 16/24/32/48 2 Stratix III 3 Backplane Driver AC/DC coupled 4 Slot Slot Switch Typically 16 to 48 full duplex ports on a single "Line Card" Slot BACKPLANE CHASSIS LINE CARDS Altera Corporation 3

4 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices In this case, the PHY device is part of the copper SFP module which re-times the data to enable interoperability. In this connectivity, the interface marked 1 in Figure 3 is typically AC coupled on the SFP module itself with a typical capacitor value of 0.01 uf (refer to Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement ). Here again, Stratix III devices are used to provide an interface to the gigabit ethernet PHY, optional host processor, and backplane driver. Stratix III Interfacing with PHY Device (without SFP Module) Stratix III devices can interface with RJ45 via a PHY device. This link can be AC/DC coupled as shown in Figure 1. Stratix III Soft-CDR Features Stratix III devices have built-in SERDES circuitry that supports high-speed LVDS interfaces up to data rates of 1.25 Gbps. The SERDES circuitry is configurable to support source synchronous and asynchronous serial data communication for SGMII interfaces. The Stratix III family supports three receiver data path modes: non-dpa mode, Dynamic phase alignment (DPA) mode, and soft-cdr mode. For SGMII interfaces, data communication can be achieved using soft-cdr mode and DPA mode (source synchronous mode) in the receive data path. There are three typical SGMII system scenarios: Soft-CDR mode in Asynchronous Systems In this system, there is no source synchronous clock sent with the data channels from the upstream transmitter. The upstream transmitter and receiver nodes use reference clocks from two different sources. This causes a potential PPM difference between the upstream transmitter and receiver nodes. The maximum PPM difference allowed between the two clock sources is +/-100 PPM. Typically, an asynchronous system is between chip-to-chip, or board-to-board with optional backplane. Soft-CDR mode in Synchronous Systems In this system, there is no source synchronous clock sent with the data channels from the upstream transmitter. Both upstream transmitter and receiver nodes use the same reference clock source. Source synchronous mode In this system, a source synchronous clock is sent with the data channels. The receiver nodes use this source synchronous clock to recover the received data. 4 Altera Corporation

5 I/O Standards Interoperable with Stratix III LVDS I/O Standards Interoperable with Stratix III LVDS This section discusses various I/O standards that can be involved in a data communication system s line card employing an SGMII interface. Table 1 shows the input/output voltages and common modes used in this application note. Table 1. Input and Output Voltages and Common Modes Parameter LVPECL (Optical and Copper SFP module) Minimum (V) Typical (V) Maximum (V) Minimum (V) LVDS (Stratix III) (1) Typical (V) Maximum (V) Supply Voltage Output Differential Voltage (V OD ) (single ended[peak-to-peak]) Output Common Mode Voltage (V OCM ) Input Differential Voltage (V ID ) (single ended[peak-to-peak]) Input Common Mode Voltage (V ICM ) Note to : (1) For more information on LVDS parameters, refer to the DC and Switching Characteristics of Stratix III Devices chapter of the Stratix III Devices Handbook. LVPECL (SFP, 3.3 V)-to-LVDS (Stratix III, 2.5 V) Interface The SFP modules (optical / copper) are AC coupled on the SGMII side of the interface. This AC coupling is present within the SFP modules. The network shown in Figure 4 assumes that the signal out of the SFP module is AC coupled and the trace impedance between the two devices is 50 Ω single ended. As shown in Table 1, the output swing of the LVPECL (SFP) transmitter and the input amplitude sustainable by the LVDS (Stratix III) receiver are compatible. Therefore, Altera recommmends a resistor network that can raise the common mode for the LVDS receiver. One such resistor network is shown in Figure 4. Altera Corporation 5

6 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Figure 4. LVPECL (SFP, 3.3 V)-to-LVDS (Stratix III, 2.5 V) SFP Connector Boundary Device Boundary V CC 3.3V node_a V CC 2.5V Zo = 50Ω V ICM R1 + LVPECL Zo = 50Ω R2 - LVDS node_an Figure 5 shows the accompanied HSPICE simulation result window. The depicted resistor network raises the common mode of the signal coming into the LVDS (Stratix III device) receiver to V ICM. The V ICM is set to 1.25 V to be in line with the receiver s input common mode range as shown in Table 1. 6 Altera Corporation

7 I/O Standards Interoperable with Stratix III LVDS Figure 5. LVPECL-to-LVDS HSPICE Simulation Result Window The values of resistors R1 and R2 is 50 Ω each. 1 In this interface, on-chip termination (OCT) on the Stratix III LVDS receiver is disabled. SFP modules are typically AC coupled. In cases where external RJ45, magnetics, and PHY devices are used instead of SFP, Stratix III devices support DC coupling. LVDS (Stratix III, 2.5 V)-to-LVPECL (SFP, 3.3V) Interface For the LVDS (Stratix III, 2.5 V)-to-LVPECL interface, there is no need for any resistive network because the input voltage and common mode tolerances of the LVPECL (SFP) receiver are greater than the maximum output amplitude and output common mode of the Stratix III LVDS transmitter (Table 1). It is assumed that the Stratix III LVDS transmitter is operating at maximum output voltage settings with maximum pre-emphasis (refer to Programmable Pre-Emphasis and Programmable V OD on page 25 for instructions on how to set these settings in Stratix III Altera Corporation 7

8 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices device). It is further assumed that the SFP module discussed in this interface is AC coupled, which is the typical connector in the SGMII systems. PCML (Stratix II GX)-to-LVDS (Stratix III, 2.5 V) Interface For the PCML (Stratix II GX)-to-LVDS (Stratix III, 2.5 V) interface, there is no need for any resistive network because DC coupling between a Stratix II GX PCML transceiver and a Stratix III LVDS interface is supported. Adjust the output amplitude of the Stratix II GX transmitter so that the signal amplitude at the input of Stratix III receiver is within the allowable minimum and maximum input voltage limit (refer to Table 1). The Stratix II GX transmitter supports 1.5 V and 1.2 V PCML standards and has common mode options of 0.6V or 0.7 V, and output amplitudes ranging from 0.2 V to 1.4 V. 1 In this interface, OCT on the Stratix III LVDS receiver is enabled. LVDS (Stratix III, 2.5 V)-to-LVDS (Stratix II GX) Interface For the LVDS (Stratix III, 2.5 V)-to-LVDS (Stratix II GX) interface, there is no need for any resistive network because AC or DC coupling between a Stratix III LVDS interface and a Stratix II GX PCML interface is supported. The Stratix II GX receiver must be configured to LVDS I/O standards with the input common mode voltage of 1.2 V. The input signal amplitude range of a Stratix II GX receiver is 100 mv to 900 mv (single ended). 1 In this interface, OCT on the Stratix II GX receiver is enabled. Stratix III devices provide a 100 Ω differential OCT option on each differential receiver channel for LVDS standards (refer to Figure 6). OCT saves board space by eliminating the need to add external resistors on the board. Figure 6. Differential I/O OCT LVDS Transmitter Zo = 50Ω Stratix III Differential Receiver with On-Chip 100-Ω Termination R D Zo = 50Ω 8 Altera Corporation

9 Links LVDS (Stratix III,2.5V)-to-Third Party LVDS Interface The Stratix III LVDS interface is compatible to the LVDS standard of devices other than Stratix III devices. Links Stratix III LVDS Transmitter and Receiver (Soft-CDR) Architecture A typical SGMII implemented system uses between 16 to 48 full duplex links. Stratix III devices allow the implementation of multiple full duplex channels because they offer up to 132 transmitters and receivers in the highest density package. For the SGMII link in such dense applications, the Stratix III LVDS I/O standard is preferred and used because of its low-voltage differential signaling capability. Stratix III transmitters have programmable output voltage settings, output common mode range, and four settings for pre-emphasis. On the receive side, Stratix III devices can operate with a wide range of input voltage amplitudes and input common modes. Transmit side circuitry has differential buffers, serializer and left/right PLLs,which can be shared between transmitter and receiver. Figure 7 shows the transmitter data path. If you use only one side of the Stratix III device to implement all your SGMIII LVDS interfaces, you only need one PLL. Figure 7. LVDS Transmitter Data Path Notes (1), (2) FPGA Fabric tx_in 10 2 Serializer DIN DOUT IOE IOE Supports SDR, DDR, or Non-Registered Datapath + - tx_out tx_coreclock LVDS Transmitter 3 (LVDS_LOAD_EN, diffioclk, tx_coreclock) Left/Right PLL tx_inclock LVDS Clock Domain (1) The tx_in port has a maximum data width of 10. (2) All disabled blocks and signals are grayed out. Altera Corporation 9

10 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices The LVDS receiver has the following hardware blocks: Differential buffer DPA block Synchronizer Data realignment block Deserializer Left/right PLLs that can be shared between the transmitter and receiver As shown in Figure 8, the synchronizer block is inactive in soft-cdr mode receiver architecture. The DPA circuitry selects an optimal DPA clock phase to sample the data from eight serial clock phases sent by the left/right PLL. The selected DPA clock is used for bit-slip operations and deserialization. The DPA block also forwards the selected DPA clock, divided down by the deserialization factor, called rx_divfwdclk, to the FPGA fabric along with the deserialized data. In Stratix III devices, every LVDS receiver channel can be used in soft-cdr mode. The rx_dpa_locked signal is not valid in soft-cdr mode because DPA continuously changes its phase to track a PPM difference between the upstream transmitter and local receiver input reference clocks. The parallel clock rx_outclock, generated by the left/right PLL, is also forwarded to the FPGA fabric. 10 Altera Corporation

11 + - Stratix III LVDS Transmitter and Receiver (Soft-CDR) Architecture Figure 8. LVDS Receiver Data Path in Soft-CDR Mode Notes (1), (2) FPGA Fabric rx_out 10 IOE Supports SDR, DDR, or Non-Registered Datapath 2 IOE LVDS Receiver rx_in Deserializer DOUT DIN DOUT Bit Slip DIN Synchronizer DOUT DIN DPA Circuitry Refined Data DIN DPA Clock rx_divfwdclk (LOAD_EN, diffioclk) 2 Clock Mux diffioclk LVDS_diffioclk DPA_diffioclk 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) rx_outclock LVDS Clock Domain DPA Clock Domain (LVDS_LOAD_EN, LVDS_diffioclk, 3 rx_outclk) 8 Serial LVDS Clock Phases Left/Right PLL rx_inclock Notes to Figure 8: (1) All disabled blocks and signals are grayed out. (2) The rx_out port has a maximum data width of 10. f For more details about transmitter and receiver architecture, refer to the High Speed Differential I/O Interfaces and DPA in Stratix III Devices chapter in the Stratix III Device Handbook. Configuration of the ALTLVDS Transmitter and Receiver for SGMII Implementation The Quartus II software provides the MegaWizard Plug-In Manager to generate the ALTLVDS megafunction to configure the hardware instantiation in different modes. Soft-CDR mode refers to receiver data path mode. To configure the ALTLVDS megafunction (for transmitter or receiver configuration) in the Quartus II software in soft-cdr mode, perform the following steps: LVDS Transmitter Configuration 1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager [page 1] dialog box appears. Altera Corporation 11

12 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices 2. Select Create a new custom megafunction variation and click Next. The MegaWizard Plug-In Manager [page 2a] dialog box appears. 3. In the Which megafunction would you like to customize list, click the + to expand I/O and select ALTLVDS. Under Which type of output file do you want to create?, select the HDL. Choose your device, the name of the output file, and click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 3 of 5] wizard appears. 4. Under This module acts as an, select LVDS transmitter. Select the number of channels. In the What is the deserialization factor? list, select 10 for SGMII interface implementation. Figure 9 shows how the wizard should appear. Figure 9. LVDS Transmitter Configuration, ALTLVDS Wizard Page 3 of 5 5. Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 4 of 7] wizard appears. 12 Altera Corporation

13 Stratix III LVDS Transmitter and Receiver (Soft-CDR) Architecture 6. For What is the output data rate, type Select the input reference clock. Under Specify the input clock rate by, select clock frequency at 125 MHz. If you want to share the left/right PLL to both transmitter and receiver instances, turn on Use shared PLL(s) for receivers and transmitters. Sharing the PLLs is allowed for transmitters and receivers on the same side of the device. Figure 10 shows how the wizard should appear. Figure 10. LVDS Transmitter Configuration, ALTLVDS Wizard Page 4 of 7 7. Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 5 of 7] wizard appears. 8. If you are using a synchronous/asynchronous system (receiver in soft-cdr mode), under Transmitter outclock, turn off Use tx_outclock output port. Figure 11 shows how the wizard should appear. Altera Corporation 13

14 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Figure 11. LVDS Transmitter Configuration, ALTLVDS Wizard Page 5 of 7 9. Click Finish to complete LVDS transmitter (softcdr_tx) configuration. LVDS Receiver Configuration 1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager [page 1] dialog box appears. 2. Select Create a new custom megafunction variation and click Next. The MegaWizard Plug-In Manager [page 2a] dialog box appears. 3. In the Which megafunction would you like to customize list, click the + to expand I/O and select ALTLVDS. Under Which type of output file do you want to create?, select the HDL. Choose your device, the name of the output file, and click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 3 of 5] wizard appears. 14 Altera Corporation

15 Stratix III LVDS Transmitter and Receiver (Soft-CDR) Architecture 4. Under This module acts as an, select LVDS receiver. Turn on Enable Dynamic Phase Alignment mode (receiver only). Select the number of channels. In the What is the deserialization factor? list, select 10 for SGMII interface implementation. Figure 12 shows how the wizard should appear. Figure 12. LVDS Receiver Configuration, ALTLVDS Wizard Page 3 of 5 5. Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 4 of 9] wizard appears. 6. For What is the output data rate, type Select input reference clock. Turn on Use pll_areset input port. If you want to share the left/right PLL to both transmitter and receiver instances, turn on Use shared PLL(s) for receivers and transmitters. Sharing the PLLs is allowed for transmitters and receivers on the same side of the device. Figure 13 shows how the wizard should appear. Altera Corporation 15

16 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Figure 13. LVDS Receiver Configuration, ALTLVDS Wizard Page 4 of 9 7. Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 5 of 9] wizard appears. 8. Turn on Use rx_divfwdclk output port and bypass the DPA FIFO to select soft-cdr mode. Figure 14 shows how the wizard should appear. 16 Altera Corporation

17 Stratix III LVDS Transmitter and Receiver (Soft-CDR) Architecture Figure 14. LVDS Receiver Configuration, ALTLVDS Wizard Page 5 of 9 1 The PPM value for What is the simulated recovered clock phase drift? is only for simulation purposes. It has no significance in the real hardware. 9. Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 6 of 9] wizard appears. 10. Under DPA Circuitry reset, turn on Use rx_reset input port. In soft-cdr mode, using the rx_dpa_locked output port is not necessary. You can turn on Use a DPA initial phase selection of, depending on the system design requirement in the increments of 45 degrees. The Quartus II software defaults to 0 degrees. Figure 15 shows how the wizard should appear. f For more information, refer to the High Speed Differential I/O Interfaces and DPA in Stratix III Devices chapter in the Stratix III Device Handbook. Altera Corporation 17

18 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Figure 15. LVDS Receiver Configuration, ALTLVDS Wizard Page 6 of Click Next. The MegaWizard Plug-In Manager - ALTLVDS [page 7 of 9] wizard appears. 12. Turn on Use rx_channel_data_align input port. Select 10 for the number of pulses for data alignment circuitry (bit-slip) to restore the latency back to 0. You can turn on Use rx_cda_reset input port as a reset to data realignment (bit-slip) circuitry. Figure 16 shows how the wizard should appear. 18 Altera Corporation

19 Clocking Scheme for Soft-CDR Mode in Stratix III Devices for SGMII Implementation Figure 16. LVDS Receiver Configuration, ALTLVDS Wizard Page 7 of Click Finish to complete the soft-cdr LVDS receiver (softcdr_rx) configuration. 1 If you instantiate a single channel SGMII transmitter or receiver instance multiple times to create a multi-channel SGMII interface, the Quartus II software automatically selects the same PLL to drive these multiple instances if the same reference clock source is shared. Clocking Scheme for Soft-CDR Mode in Stratix III Devices for SGMII Implementation Figure 11 shows the clocking scheme of both transmitter and receiver data paths with the hardware blocks required for transmitter and receiver PCS implementation. Altera Corporation 19

20 8 8 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Figure 17. Clocking Scheme for Soft-CDR Mode in Stratix III Device for SGMII Implementation Notes (1), (2) Transmitter PCS (3) LVDS Transmitter LVDS Receiver Configured in Soft-CDR Mode Receiver PCS (3) 8B10B encoder 10 TX bit reversal Data Phase Aligner (DPA) Deserializer and bit slip 10 Serializer 10 RX bit Word Elastic 8B10B 8 reversal aligner FIFO Decoder 8 diffioclk_tx (1250 MHz) rx_divfwdclk (125 MHz) Upper layer logic FPGA Fabric tx_coreclock (125 MHz) Hard Macro Left/Right PLL Left/Right 8 serial PLL clock phases 1250 MHz) Hard Macro rx_outclock (125 MHz) FPGA Fabric Receiver PCS (3) LVDS Transmitter LVDS Receiver Configured in Soft-CDR Mode Transmitter PCS(3) 8B10B Decoder Elastic FIFO Word aligner RX bit reversal 10 Deserializer and bit slip Data Phase Aligner (DPA) Serializer 10 TX bit reversal 10 8B10B encoder rx_divfwdclk (125 MHz) diffioclk_tx (1250 MHz) rx_outclock (125 MHz) Left/Right PLL 8 serial clock phases 1250 MHz) Left/Right PLL tx_coreclock (125 MHz) Upper layer logic FPGA Fabric Hard Macro Hard Macro FPGA Fabric 125 MHz +/- 100 PPM Reference clock source for upstream node (4) Reference clock source for downstream node (4) 125 MHz +/- 100 PPM Notes to Figure 17: (1) An example SGMII system implemented on Stratix III evaluation board with Altera s triple speed ethernet (TSE) MegaCore using a LVDS hard macro configured as soft-cdr. For more details, refer to Results on page 28. (2) In this diagram, both at upstream and downstream node, transmitter and receiver use shared PLL. (3) You should implement transmitter PCS and receiver PCS enclosed in the dotted box in the FPGA logic. (4) Reference clock sources for both transmitter and receiver typically use 125 MHz/62.5 MHz with a PPM tolerance of +/- 100 PPM. Stratix III devices have left/right PLLs on both sides of the device. For LVDS transmitters, left/right PLLs typically take a 125 MHz /62.5 MHz reference clock and produces three clocks: LVDS serial clock (diffioclk_tx) This serial clock is at 1.25 GHz (The LVDS serial clock is internal to the hard macro and is not brought out to the output port of the ALTLVDS transmitter instantiation) tx_outclock This clock is used in source synchronous LVDS systems (DPA mode) to send the synchronous clock along with transmitted data. This clock is not used in the soft-cdr mode of LVDS receivers. 20 Altera Corporation

21 Description of the Transmitter PCS Data Path f For more details about the DPA mode and tx_outclock use, refer to the High Speed Differential I/O Interfaces and DPA in Stratix III Devices chapter in the Stratix III Device Handbook. tx_coreclock This clock is used for clocking the following PCS functional blocks: 8B/10B encoder, TX bit reversal block, and any other FPGA fabric logic. This clock runs at 125 MHz. In the LVDS receiver, the left/right PLL typically takes the 125 MHz/62.5 MHz reference clock and produces two clocks: LVDS serial clock (diffioclk_rx) Eight LVDS fast clocks at 1.25 GHz with eight varying phases in the 45 degrees steps. (The LVDS serial clock is internal to the hard macro and is not brought out to the output port). All eight clocks with different phases are sent to the DPA block. rx_outclock This is the LVDS slow clock at 125 MHz that is sent to the FPGA fabric. You can use this clock for decoupling the clock domain from the rx_divfwdclk clock in the rate matcher or elastic FIFO block. In the LVDS receiver side, the DPA block takes eight phases of serial clock from the left/right PLL and chooses the serial clock, which is the best phase aligned to the incoming serial data. The DPA block also divides this selected high speed serial clock (1.25 GHz) by the serialization factor of 10 and sends rx_divfwdclk (125 MHz) along with the parallel data to the FPGA fabric. Description of the Transmitter PCS Data Path f Figure 17 shows the data path of a gigabit ethernet PCS implementation. On the transmitter side, you should implement an 8B/10B encoder and TX bit reversal block to complete the transmitter PCS layer with an LVDS hard macro. In the upstream transmitter side, upper layer logic sends 8-bit data to the 8B/10B encoder block in the PCS layer. After encoding, the 8B/10B encoder sends the 10-bit data to the TX reversal block. After inverting the bit order in the 10-bit word, the TX bit reversal block sends the data to the LVDS transmitter. In the LVDS transmitter, parallel data is serialized and sent to the transmitter buffers. For more details about the LVDS hard macro blocks (DPA, bit-slip, serializer, and deserializer), refer to the High Speed Differential I/O Interfaces and DPA in Stratix III Devices chapter in the Stratix III Device Handbook. Altera Corporation 21

22 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices 8B/10B Encoder The 8B/10B encoder block takes in 8-bit data from the MAC layer of the gigabit ethernet protocol in the FPGA fabric. It generates a 10-bit code group with proper running disparity from the 8-bit character. The 10-bit encoded data output from the 8B/10B encoder is fed to the TX bit reversal block. The 8B/10B encoder must conform to the IEEE standards. TX Bit Reversal Block By default, the LVDS transmitter serializer transmitted bit order is MSBit to LSBit. IEEE standards mandate the serialized data bit order from LSBit to MSBit. The Transmitter bit reversal block allows reversing the transmitted bit order as LSBit to MSBit. Figure 18 shows the transmitter bit reversal block functionality for 10-bit wide data. Figure 18. TX Bit Reversal Block D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] TX bit reversal block D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[0] Output from 8B/10B encoder D[9] Input to LVDS transmitter Description of the Receiver PCS Data Path As shown in Figure 17, you should implement an RX bit reversal block, word aligner block, rate matcher block, and 8B/10B decoder block to complete the receive PCS layer. The left/right PLL typically takes a 125 MHz/62.5 MHz reference clock and sends 8 phases of 1.25 GHz serial clocks to the DPA block. The DPA block takes the serial data at 1.25 Gbps and selects the best phase aligned clock using the incoming serial data. This selected DPA phase aligned clock is used to clock bit-slip and deserializer circuitry. The deserializer block converts the serial data 22 Altera Corporation

23 Description of the Receiver PCS Data Path stream into parallel 10-bit data and sends it to the RX bit reversal block in the FPGA fabric. The following sections discuss each of the receiver PCS hardware blocks. RX Bit Reversal Block By default, the LVDS receiver assumes an MSBit-to-LSBit transmission. IEEE specifications mandate the serialized data bit order from LSBit to MSBit. If the transmission order is LSBit to MSBit, the receiver RX bit reversal block sends out the bit-flipped version of the data on the FPGA fabric interface. This reorders the data word on the FPGA fabric interface from MSBit to LSBit. Figure 19 shows the transmitter bit reversal block functionality for 10-bit wide data. Figure 19. RX Bit Reversal Block D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] RX bit reversal block D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[0] Output from LVDS receiver D[9] Input to Word Aligner block Word Aligner Block Synchronization is required for SGMII interfaces to align the byte boundary of the receiver to the byte boundary of the upstream transmitter. Typically, in word aligner block, you implement a pattern detector and then synchronize the state machine. The word aligner block aligns the byte boundary with the first /K28.5/ 10-bit comma character in the serial data stream. After byte boundary alignment is fixed using the bit-slip module, the user-implemented pattern detector module checks for the standard patterns and sends the data to synchronization the state machine. Synchronization of the state machine is implemented for hysteresis purpose. Altera Corporation 23

24 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices You can implement a pattern detector module using data realignment (bit-slip) circuitry in the LVDS hard macro. The data realignment (bit-slip) circuit realigns the data by inserting bit latencies into the serial stream. An optional rx_channel_data_align port controls the bit insertion of each receiver, which is independently controlled from the internal logic. The data slips one bit for every pulse on the rx_channel_data_align signal. The following are requirements for the rx_channel_data_align signal (The minimum pulse width is one period of the parallel clock in the logic array): The minimum low time between pulses is one period of parallel clock This is an edge-triggered signal Valid data is available two parallel clock cycles after the rising edge of rx_channel_data_align The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. Set the programmable bit rollover point at 10 for SGMII implementation. An optional status port, rx_cda_max, is available to the FPGA fabric from each channel to indicate when the preset rollover point is reached. Synchronization is achieved when the receiver sees three consecutive ordered sets. An ordered set defined for synchronization is a /K28.5/ comma followed by any odd number of valid /Dx.y/ code (/Dx.y/ denotes any valid data code group). You should implement the SGMII synchronization state machine as per the IEEE specification. Elastic FIFO (Rate Matcher) Block In gigabit ethernet, the rate matcher compensates up to ±100 PPM (200 PPM total) frequency difference between the upstream transmitter and receiver. The write port of the rate matcher FIFO in each LVDS receiver channel is clocked by its forwarded clock (rx_divfwdclk). The read port is clocked by the LVDS low-speed parallel clock output of the left/right PLL. As per the IEEE specification, the rate matcher logic should insert or delete /I2/ (idle ordered-sets) to or from the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or IPG). If the autonegotiation feature is implemented as part of the system, the rate matcher needs to insert/delete the first two bytes of the /C2/ (configuration ordered sets) in addition to the insertion/deletion of /I2/ ordered sets. 24 Altera Corporation

25 Programmable Pre-Emphasis and Programmable V OD 8B/10B Decoder In gigabit ethernet, the 8B/10B decoder clocks in 10-bit data from the rate matcher and decodes it into 8-bit data. The 8-bit decoded data is fed to upper layer logic. Implement the 8B/10B decoder as per IEEE specification. Programmable Pre-Emphasis and Programmable V OD Programmable V OD and programmable pre-emphasis can help system designers drive SGMII interfaces. These two features provide advantages in driving serial data in chip-to-chip or backplane applications. Programmable V OD V OD settings can be statically assigned from the assignment editor. Table 2 shows the assignment name for programmable V OD and its possible values in the Quartus II software assignment editor. Table 2. Quartus II Software Assignment Editor To tx_out Assignment name Programmable V OD Allowed values 0, 1, 2, 3 Figure 20 shows an assignment of programmable V OD for a transmit data output in the Quartus II software assignment editor. Figure 20. Quartus II Software Assignment Editor - Programmable V OD Altera Corporation 25

26 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Table 3 shows four possible settings and their corresponding V OD values. Table 3. V OD Settings for LVDS Channels Note (1) Quartus II Assignment Editor V OD Settings Note to Table 3: (1) The default V OD setting is at 1. V OD (mv) (Single ended [peak-to-peak]) Programmable Pre-Emphasis Four different settings are allowed for pre-emphasis from the assignment editor for each LVDS output channel. Table 4 shows the assignment name and its possible values for programmable pre-emphasis in the Quartus II software assignment editor. Figure 21 shows assignments of programmable pre-emphasis for a transmit data output port in the Quartus II software assignment editor. Table 4. Quartus II Software Assignment Editor To tx_out Assignment name Programmable Pre-emphasis Allowed values 0,1,2,3 26 Altera Corporation

27 Hot Socketing Feature of Stratix III Devices Figure 21. Quartus II Software Assignment Editor - Programmable Pre-Emphasis Hot Socketing Feature of Stratix III Devices Stratix III devices offer hot socketing and power sequencing support without the use of any external devices. You can insert or remove a Stratix III device or a board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot socketing feature also removes some of the difficulty when you use Stratix III devices on printed circuit boards (PCBs) that contain a mixture of 3.3, 3.0, 2.5, 1.8, 1.5 and 1.2 V devices. With the Stratix III hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. The Stratix III hot socketing feature provides: Board or device insertion and removal without external components or board manipulation Support for any power-up sequence Non-intrusive I/O buffers to system buses during hot insertion f For more information, refer to the Hot Socketing and Power-On Reset in Stratix III Devices chapter in the Stratix III Handbook. Altera Corporation 27

28 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Results Table 5 shows SGMII specifications and corresponding Stratix III LVDS data. Table 5. SGMII Specifications and Stratix III LVDS Compliance Note (1) Parameter SGMII Specification (2) Stratix III LVDS (Single Ended [Peak-to-Peak]) Min Max Min Typ Max Output Offset Voltage (V OS ) mv Input Voltage Range (V I ) mv Output Voltage Range (V OD ) mv Transmitter output Jitter UI Receiver Jitter Tolerance UI Receiver PPM Tolerance PPM Soft-CDR run length 16,400 V OD fall time ps V OD rise time ps Receiver differential input impedance Ω Note to Table 5: (1) For more information about the Stratix III LVDS specifications, refer to the Stratix III Device Datasheet: DC and Switching Characteristics chapter in volume 2 of the Stratix III Device Handbook. (2) All the SGMII specifications conform to IEEE standard. Units Altera has implemented a complete solution with a TSE MegaCore with PMA, PCS, and MAC for Ethernet applications. Figure 22 shows a block diagram of a single channel duplex gigabit ethernet system implementation with Stratix III devices. The TSE MegaCore also uses a LVDS hard macro configured as soft-cdr. Contact the Altera sales team for information about the TSE MegaCore. 28 Altera Corporation

29 Results Figure 22. Altera TSE MegaCore Solution Note (1) Transmitter PCS LVDS Transmitter LVDS Receiver Configured in Soft-CDR Mode Receiver PCS Transmitter PCS + MAC 10 Data Deserializer Serializer Phase 10 Aligner and (DPA) bit slip Receiver PCS + MAC tx_coreclock (125 MHz) diffioclk_tx (1250 MHz) Left/Right PLL 8 serial clock phases 1250 MHz) Left/Right PLL rx_divfwdclk (125 MHz) rx_outclock (125 MHz) FPGA Fabric Hard Macro Hard Macro FPGA Fabric Receiver PCS LVDS Receiver Configured in Soft-CDR Mode LVDS Transmitter Transmitter PCS Receiver PCS + MAC 10 Deserializer and bit slip Data Phase Aligner (DPA) Serializer 10 Transmitter PCS + MAC FPGA Fabric rx_divfwdclk (125 MHz) rx_outclock (125 MHz) Left/Right PLL 8 serial clock phases 1250 MHz) Hard Macro diffioclk_tx (1250 MHz) Left/Right PLL Hard Macro FPGA Fabric tx_coreclock (125 MHz) 125 MHz +/- 100 PPM Reference clock source for upstream node Reference clock source for downstream node 125 MHz +/- 100 PPM Note for Figure 22: (1) An example SGMII system implemented on a Stratix III evaluation board with Altera s TSE MegaCore using a LVDS hard macro configured as soft-cdr. Altera Corporation 29

30 SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices Power Consumption of Soft-CDR Implemented SGMII Physical Layer Interface in Stratix III Devices Table 6 shows the approximate power consumption for 24-channel SGMII physical layer implementation in (EPL3SL150) Stratix III devices. Table 6 also shows the breakdown of power consumption. Table 6. Power Consumption of Soft-CDR Mode Implemented SGMII Interface Note (1) SGMII Physical Layer Design Twenty-four channel design Core Static Power Consumption (mw) (2) Core Dynamic Power Consumption (mw) (3), (4) I/O Power Consumption (mw) Total Power Consumption (mw) Notes to Table 6: (1) All the power consumption stated above has been calculated with the Early Power Estimator (EPE), an Altera power estimation tool that is used for power estimation in the early design phase. Depending on the design, actual power consumption values are expected to vary. (2) Power dissipation also depends on the Stratix III device chosen for the implementation purpose. (3) Core Dynamic Power Consumption involves total power consumption in four modules: clock network, PLL, hard macro (LVDS transmitter and receiver), and FPGA fabric. (4) Above power consumption has been calculated with the assumption that both transmitter and receiver PCS logic implementation per channel will take approximately 500 ALUTs for FPGA fabric implementation. For the transmitter PCS, this includes the 8B10B encoder and TX bit slip. For the receiver PCS, this includes the RX bit reversal, word aligner, elastic FIFO, and 8B10B decoder. Referenced Documents This application note references the following: Cisco System s proprietary specification document Serial-GMII Specification Revision 1.7 High Speed Differential I/O Interfaces and DPA in Stratix III Devices chapter in the Stratix III Device Handbook Hot Socketing and Power-On Reset in Stratix III Devices chapter in the Stratix III Handbook IEEE Specification Stratix III Device Handbook Stratix II GX Device Handbook' Small Form Factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA), September 14, Altera Corporation

31 Revision History Revision History shows the revision history of this application note. Table 7. Revision History Date and Version Number Changes Made Summary of Changes May 2008 v1.0 Initial release. Altera Corporation 31