Proposal for an Open Source Flash Failure Analysis Platform (FLAP)
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1 Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns
2 Introduction Cory
3 Introduction Flash Memory prevalence Cell Phones, MP3 Players, Cameras, Hard Drives Still a new Technology NAND flash memory has a limited number of read/write cycles, its behavior past this limit has not been widely analyzed Goals Create a open source system to test NAND flash memory
4 Bill of Materials Provided through the University Altera-DE2 Development & Education Board USB Cables Provided by Micron NAND Flash storage NAND Flash Daughter Board
5 Bill of Materials Software (Free Downloads) LibUSBDotNet (SourceForge) Visual Studio Express (C# version) Altera Quartus II Web Edition Verilog dev. environment Altera Nios II Embedded Design Suite
6 Daughter Board / Memory Controller and FPGA Jake
7 FPGA Altera DE2 Development Board Includes: System On a Programmable Chip (SOPC) NAND Controller Clock Generator Reset De-Bouncer On-chip dual port RAM Parts integrated using Verilog
8 NIOS 2 Embedded processor Programmed with C Controls Interfaces USB To the GUI on the computer To the Daughtboard Controls Displays Stores test results.
9 NAND Controller Direct Interface for controlling the NAND flash Runs with 66 MHz clock. Deals with the commands: Read Program Erase Read ID Reset Read Status
10 On-chip port RAM Used as a buffer Receive data Sending commands Controlled by two signals Used by: NIOS 2 NAND Controller
11 Reset De-Bouncer Hardware reset Debounces reset Waits for the clocks to be valid
12 USB interface Sze
13 USB interface FPGA USB interface Communicates with the host PC Is programmed in firmware Responsible for: receiving commands from the host PC Transmitting results back to the host PC
14 GUI USB Uses the LibUSBDotNet C# libraries to instantiate the device and communicate over the USB endpoints Don t have to write a Windows driver! Driver runs using managed code in user space 32 byte command sent from GUI to firmware 0: opcode 1: seed 2: algorithm 3: debug level 4-7: cycles 8-11: start address { 00, block(12), page(6), column(12) } = 32 bits 12-15: end address { 00, block(12), page(6), column(12) } = 32 bits 16-31: reserved
15 USB GUI Debug Endpoint Sends information about firmware state according to the debug level sent in command Status Endpoint Returns periodic status information about the progress of the job
16 USB Firmware State Machine for USB portion of firmware: Receive Job from GUI (Interrupt) Add Job to FIFO Queue To NAND FSM Wait for next Job/ Process NAND FSM
17 USB GUI Result Endpoint Sends the results of jobs as XML data <job id="4" opcode="128" seed="0" algorithm="0" cycles="10000" startaddress="0x " endaddress="0x000fc000" debug="0"> <data>u3vjaybtesbiywxscye=</data> <error count="1" address="0x0x000fc000"> <byte index="23" received="35"/> <byte index="444" received="255"/> </error> <time days="0" hours="0" minutes="0" seconds="7" millisec="519"/> <done failurecode="0" failures="1"/> </job>
18 USB interface USB interface on host PC stores results in a SQL database using the ActiveX Data Objects Classes of the.net framework to communicate with the database Normalized database T-SQL (Transactional SQL) extension to the SQL database programming language Initially SQL database will store basic info but can be expanded
19 Graphical User Interface on the PC Mike
20 GUI Team completed a very basic GUI They were unable to fully test it because of the problems with the USB
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24 Graphical User Interface on the PC Need to expand on s interface Automated Testing patterns can be specified range of blocks to test Number of cycles to run for Can use specific memory patters or randomly generated patterns for testing. Options for connecting to the database Loading the firmware onto the FPGA
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31 Database Structure Importance of data normalization Non-Normalized data Data is duplicated across many items This leads to problems when updating and querying data and adding additional fields If there is time we are planning to store additional information in the database Uses more space Space is critical because of the amount of data being stored.
32 This improves some. More improvements can be made
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34 GUI Ensuring database normalization will make it easy for programs like Microsoft Access to access the data. Access is a relatively simple interface that will enable engineers to create custom charts and graphs that will suit their needs
35 Risks, Timeline, Conclusion Hartman
36 Risks Previous team( ) was unable to get full system working. They were only able to get the interface between the daugterboard and the fpga operational We will need to test and debug their interface for full functionality
37 Risks The previous team was unable to get USB working properly We may still have significant issues with usb connections Hopefully using libusbdotnet will solve this
38 Risks We will need to complete quickly enough so that we can run tests on memory and determine failure patterns and rates
39 Implementation Timeline
40 Conclusion Using data generated by the FLAP it will be possible to: Find the best algorithms to correct errors How many spare blocks per chip are necessary Predict failure rates for specific use patterns (server vs. workstation use, etc)
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