PSoC 63 with BLE TRM. PSoC 63 with BLE Architecture Technical Reference Manual (TRM) PSoC 6 MCU. Document No Rev. *D October 4, 2017

Transcription

1 PSoC 63 with BLE TRM PSoC 6 MCU PSoC 63 with BLE Architecture Technical Reference Manual (TRM) Document No Rev. *D October 4, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA

2 Copyrights Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ( Cypress ). This document, including any software or firmware included or referenced in this document ( Software ), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ( Unintended Uses ). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 2 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

3 Contents Overview Section A: Overview Introduction Getting Started Document Construction Section B: CPU Subsystem CPU Subsystem (CPUSS) Inter-Processor Communication Fault Monitoring Interrupts Protection Units DMA Controller Cryptographic Function Block (Crypto) Program and Debug Interface Nonvolatile Memory Programming efuse Memory Chip Operational Modes Device Security Section C: System Resources Subsystem (SRSS) Power Supply and Monitoring Device Power Modes Backup System Clocking System Reset System I/O System Watchdog Timer Trigger Multiplexer Block Energy Profiler Section D: Digital Subsystem Serial Communications Block (SCB) Serial Memory Interface (SMIF) Timer, Counter, and PWM Inter-IC Sound Bus PDM-PCM Converter PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 3

4 30. Universal Serial Bus (USB) Device Mode Universal Serial Bus (USB) Host LCD Direct Drive Universal Digital Blocks (UDB) Section E: Analog Subsystem Analog Reference Block Low-Power Comparator Continuous Time Block mini (CTBm) Continuous Time DAC SAR ADC Temperature Sensor Analog Routing CapSense Section F: BLE Subsystem (BLESS) Bluetooth Low Energy Subsystem (BLESS) PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

5 Contents Section A: Overview 19 Document Revision History Introduction Top Level Architecture CPU Subsystem (CPUSS) CPU DMA Controllers Flash SRAM SROM OTP efuse Program and Debug System Resources Subsystem (SRSS) Power System Clocking System GPIO Analog Subsystem bit SAR ADC Temperature Sensor bit Digital-to-Analog Converter Continuous Time Block (CTBm) Low-Power Comparators CapSense Programmable Digital Smart I/O Universal Digital Blocks (UDBs) and Port Interfaces Digital Subsystem Timer/Counter/PWM Block Serial Communication Blocks (SCB) Serial Memory Interface (SMIF) Audio Subsystem BLE Subsystem (BLESS) Getting Started Support Product Upgrades Development Kits Application Notes Document Construction Major Sections Documentation Conventions...29 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 5

6 3.2.1 Register Conventions Numeric Naming Units of Measure Acronyms...30 Section B: CPU Subsystem 33 Top Level Architecture CPU Subsystem (CPUSS) Features Block Diagram How It Works Address and Memory Maps Registers Operating Modes and Privilege Levels Instruction Set Fault Reporting Inter-Processor Communication Features IPC Channel IPC Interrupt IPC Channels and Interrupts Implementing Locks Message Passing Fault Monitoring Features Block Diagram How It Works Fault Report Signaling Interface Monitoring Low-power Mode Operation Using a Fault Structure CPU Exceptions Versus Fault Monitoring Fault Sources Register List Interrupts Features How It Works Interrupts and Exceptions - Operation Interrupt/Exception Handling Level and Pulse Interrupts Exception Vector Table Exception Sources Reset Exception Non-Maskable Interrupt Exception HardFault Exception Memory Management Fault Exception Bus Fault Exception Usage Fault Exception Supervisor Call (SVCall) Exception PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

7 7.4.8 PendSupervisory (PendSV) Exception System Tick (SysTick) Exception Interrupt Sources Interrupt/Exception Priority Enabling and Disabling Interrupts Interrupt/Exception States Pending Interrupts/Exceptions Stack Usage for Interrupts/Exceptions Interrupts and Low-Power Modes Interrupt/Exception Initialization and Configuration Registers Protection Units Bus Master Attributes Protection Context Protection Context Protection Structure Protection Violation MPU SMPU PPU Protection of Protection Structures Protection Structure Types DMA Controller Description Channels Descriptors Address Configuration Transfer Size Descriptor Chaining DMA Controller Trigger Selection Pending Triggers Output Triggers Interrupts DMA Performance Cryptographic Function Block (Crypto) Architecture Definitions of Terms Crypto Block Functions Symmetric Key Functions Hash Functions Message Authentication Code (MAC) Functions Cyclic Redundancy Code (CRC) Random Number Generator (RNG) Module Configuration and Initialization Program and Debug Interface Features Functional Description Debug Access Port (DAP) ROM Tables...93 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 7

8 Trace Embedded Cross Triggering Serial Wire Debug (SWD) Interface SWD Timing Details ACK Details Turnaround (Trn) Period Details JTAG Interface Programming the PSoC 6 MCU SWD Port Acquisition SWD Programming Mode Entry SWD Programming Routines Executions Registers Nonvolatile Memory Programming Functional Description System Call Implementation System Call via CM0+ or CM System Call via DAP Exiting from a System Call SROM API Library System Calls Silicon ID Blow Fuse Bit Read Fuse Byte Write Row Program Row Erase All Checksum Compute Hash Erase Sector Soft Reset Erase Row Erase Sub Sector System Call Status efuse Memory Features Operating Principles Chip Operational Modes Boot User Trusted Debug Device Security Features How It Works Life Cycle Stages and Protection States Flash Security Hardware-Based Encryption Section C: System Resources Subsystem (SRSS) 123 Top Level Architecture PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

9 16. Power Supply and Monitoring Features Block Diagram How it Works Power Supply Regulators Summary Power Pins and Rails Power Sequencing Requirements Backup Domain Power Supply Sources Voltage Monitoring Power-On-Reset (POR) Brownout-Detect (BOD) Low-Voltage-Detect (LVD) Over-Voltage Protection (OVP) Register List Device Power Modes Features Device Power Modes Active and Sleep Modes Low-Power Active/Sleep Modes Deep-Sleep Mode Hibernate Mode Other Operation Modes Power Mode Transitions Power-up Transitions Low-power Mode Transitions Wakeup Transitions Summary Register List Backup System Features Block Diagram Power Supply Clocking WCO with External Clock/Sine Wave Input Calibration Reset Real-Time Clock Reading RTC User Registers Writing to RTC User Registers Alarm Feature PMIC Control Backup Registers Register List Clocking System Block Diagram Clock Sources Internal Main Oscillator (IMO) External Crystal Oscillator (ECO) PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 9

10 External Clock (EXTCLK) Alternate High-Frequency Clock (ALTHF) Internal Low-speed Oscillator (ILO) Precision Internal Low-speed Oscillator (PILO) Watch Crystal Oscillator (WCO) Clock Generation Phase-Locked Loop (PLL) Frequency Lock Loop (FLL) Clock Trees Path Clocks High-Frequency Root Clocks Low-Frequency Clock Timer Clock CTBm Alternate Pump Clock Group Clocks (clk_sys) CLK_HF[0] Distribution CLK_FAST CLK_PERI CLK_SLOW Peripheral Clock Dividers Fractional Clock Dividers Peripheral Clock Divider Configuration Clock Calibration Counters Reset System Reset Sources Power-on Reset Brownout Reset Watchdog Timer Reset Software Initiated Reset External Reset Logic Protection Fault Reset Clock-Supervision Logic Reset Hibernate Wakeup Reset Identifying Reset Sources Register List I/O System Features GPIO Interface Overview I/O Cell Architecture Digital Input Buffer Digital Output Driver High-Speed I/O Matrix I/O State on Power Up Behavior in Low-Power Modes Input and Output Synchronization Interrupt Peripheral Connections Firmware-Controlled GPIO Analog I/O LCD Drive CapSense PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

11 Serial Communication Block (SCB) Smart I/O Overview Block Components Routing Operation Registers Watchdog Timer Features Block Diagram Free-running WDT Overview Watchdog Reset Watchdog Interrupt Multi-Counter WDTs Overview How it Works Enabling and Disabling WDT Watchdog Cascade Options Watchdog Reset Watchdog Interrupt Reset Cause Detection Register List Trigger Multiplexer Block Features Description Trigger Multiplexer Architecture Trigger Multiplexer Group Trigger Multiplexer Block Architecture Trigger Multiplexer Routing Software Triggers PSoC 6 MCU Trigger Multiplexer Block Register List Energy Profiler Features Block Diagram Profiler Design Available Monitoring Sources Counter Value Weighting (Energy Coefficients) Reference Clocks Using the Profiler Enable or Disable the Profiler Configure and Enable a Counter Start and Stop Profiling Handle Counter Overflow Get the Results Exit Gracefully Section D: Digital Subsystem 219 Top Level Architecture PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 11

12 25. Serial Communications Block (SCB) Features Operation Modes Buffer Modes Clocking Modes Serial Peripheral Interface (SPI) Features General Description SPI Modes of Operation SPI Buffer Modes Clocking and Oversampling Enabling and Initializing SPI I/O Pad Connection SPI Registers UART Features General Description UART Modes of Operation Clocking and Oversampling Enabling and Initializing UART I/O Pad Connection UART Registers Inter Integrated Circuit (I2C) Features General Description Terms and Definitions I2C Modes of Operation I2C Buffer Modes Clocking and Oversampling Enabling and Initializing the I2C I/O Pad Connections I2C Registers SCB Interrupts SPI Interrupts UART Interrupts I2C Interrupts Serial Memory Interface (SMIF) Block Diagram TX and RX FIFOs MMIO Mode XIP Mode Cache Arbitration Cryptography Memory Device Signal Interface Specifying Memory Devices Connecting SPI Memory Devices SPI Data Transfer Example of Setting up SMIF Triggers Interrupts PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

13 27. Timer, Counter, and PWM Features Block Diagram Enabling and Disabling Counters in TCPWM Block Clocking Trigger Inputs Trigger Outputs Interrupts PWM Outputs Power Modes Operation Modes Timer Mode Capture Mode Quadrature Decoder Mode Pulse Width Modulation Mode Pulse Width Modulation with Dead Time Mode Pulse Width Modulation Pseudo-Random Mode (PWM_PR) TCPWM Registers Inter-IC Sound Bus Features Block Diagram Digital Audio Interface Formats Standard I2S Format Left Justified (LJ) Format Time Division Multiplexed (TDM) Format Clocking Polarity and Delay Options Interfacing with Audio Codecs Clocking Features FIFO Buffer and DMA Support Interrupt Support Watchdog Timer PDM-PCM Converter Features Block Diagram PDM-PCM Converter Features Enable/Disable Converter Clocking Features Over-Sampling Ratio Mono/Stereo Microphone Support Hardware FIFO Buffers and DMA Controller Support Interrupt Support Digital Volume Gain Smooth Gain Transition Soft Mute Word Length and Sign Bit Extension High-Pass Filter Enable/Disable Streaming Power Modes Operating Procedure Initial Configuration Interrupt Service Routine (ISR) Configuration PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 13

14 Enabling / Disabling Streaming Universal Serial Bus (USB) Device Mode Features Block Diagram USB Physical Layer (USB PHY) Serial Interface Engine (SIE) Arbiter How it Works Functions of USB PHY Endpoints Transfer Types Interrupt Sources DMA Support Logical Transfer Modes Manual Memory Management with No DMA Access Manual Memory Management with DMA Access Automatic DMA Mode Control Endpoint Logical Transfer USB Power Modes USB Device Registers Universal Serial Bus (USB) Host Features Block Diagram USB Physical Layer (USB PHY) Clock Control Block Interrupt Control Block Endpoint n (n=1, 2) DREQ Control USB Host Operations Detecting Device Connection Obtaining Transfer Speed of the USB Device USB Bus Reset USB Packets Retry Function Error Status End of Packet (EOP) Interrupt Sources DMA Transfer Function Suspend and Resume Operations Device Disconnection USB Host Registers LCD Direct Drive Features LCD Segment Drive Overview Drive Modes Recommended Usage of Drive Modes Digital Contrast Control Block Diagram How it Works High-Speed and Low-Speed Master Generators PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

15 Multiplexer and LCD Pin Logic Display Data Registers Register List Universal Digital Blocks (UDB) Features How It Works PLDs Datapath Status and Control Module Reset and Clock Control Module UDB Addressing System Bus Access Coherency Port Adapter Block PA Data Input Logic PA Port Pin Clock Multiplexer Logic PA Data Output Logic PA Output Enable Logic PA Clock Multiplexer PA Reset Multiplexer Section E: Analog Subsystem 425 Top Level Architecture Analog Reference Block Features Architecture Bandgap Reference Block Zero Dependency To Absolute Temperature Current Generator (IZTAT) Reference Selection Multiplexers Startup Modes Low-Power Modes Registers Low-Power Comparator Features Block Diagram How It Works Input Configuration Output and Interrupt Configuration Power Mode and Speed Configuration Hysteresis Wakeup from Low-Power Modes Comparator Clock Register Summary Continuous Time Block mini (CTBm) Features Block Diagram How It Works Power Mode and Output Strength Configuration Compensation Switching Matrix Sample and Hold PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 15

16 Comparator Mode Deep-Sleep Operation Register Summary Continuous Time DAC Features Block Diagram How it Works CTDAC Core CTDAC Control Interface Using CTDAC Register List SAR ADC Features Block Diagram How it Works SAR ADC Core SARMUX SARREF SARSEQ SAR Interrupts Trigger SAR ADC Status Registers Temperature Sensor Features How it Works Temperature Sensor Configuration Algorithm Registers Analog Routing Features Block Diagram How It Works AMUBUS Splitting Register Summary CapSense 479 Section F: BLE Subsystem (BLESS) Bluetooth Low Energy Subsystem (BLESS) Features Block Diagram How it Works Link Layer Controller Clocks Power States Bluetooth LE 4.2 Feature Data Length Extension Bluetooth LE 4.2 Feature Privacy PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

17 Multiple Connections External PA/LNA Support Register Details PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 17

18 18 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

19 Section A: Overview This section encompasses the following chapters: Introduction chapter on page 21 Getting Started chapter on page 27 Document Construction chapter on page 29 Document Revision History Revision Issue Date Origin of Change Description of Change *C August 18, 2017 NIDH Initial version for public release *D October 04, 2017 NIDH Updated CTDAC chapter diagrams. Minor update to the Backup System and USB Device Mode chapters PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 19

20 20 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

21 1. Introduction PSoC is a scalable and reconfigurable platform architecture that supports a family of programmable embedded system controllers with ARM Cortex CPUs (single and multi-core). The PSoC 63 with BLE product family is a combination of a dual-core microcontroller with a Bluetooth Low Energy (Bluetooth Smart) subsystem in a single package. It incorporates integrated low-power flash technology, digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, touch sensing, serial memory interface with encryption, and standard communication and timing peripherals. PSoC 6 MCUs have these characteristics: 32-bit dual core (ARM Cortex-M4 and ARM Cortex M0+) CPU subsystem Integrated (on-chip) flash memory Bluetooth Smart BT 4.2 subsystem Audio subsystem with I 2 S interface and two PDM channels Serial memory interface with on-the-fly encryption and decryption Low-power operation 1.7 V to 3.6 V Configurable digital blocks Programmable digital logic High-performance analog system Flexible and programmable interconnect Capacitive touch sensing (CapSense ) Energy profiler for software energy profiling and optimizing energy consumption Programmable GPIOs This document describes each function block of the PSoC 63 with BLE device in detail. In this document, PSoC 6 MCU refers to PSoC 63 with BLE unless explicitly mentioned otherwise. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 21

22 Introduction 1.1 Top Level Architecture Figure 1-1 shows the major components of the PSoC 63 with BLE architecture. There are five major subsystems: CPU subsystem, BLE subsystem, system resources, peripheral blocks, and I/O subsystem. CPU Subsystem Figure 1-1. PSoC 6 MCU Architecture Block Diagram System Resources Power Sleep Control POR BOD OVP LVD REF SWJ/ETM/ITM/CTI Cortex M4 FPU, NVIC, MPU, BB Cache FLASH FLASH Controller SRAM SRAM Controller ROM ROM Controller SWJ/MTB/CTI Cortex M0+ MUL, NVIC, MPU Cache DMA Initiator/MMIO System Interconnect (Multi Layer AHB, MPU/SMPU, IPC) CRYPTO DES/TDES, AES,SHA,CRC, TRNG,RSA/ECC Accelerator Initiator/MMIO PWRSYS-LP/ULP Buck Clock Clock Control ILO WDT IMO ECO FLL CSV PLL Reset Reset Control XRES Backup Backup Control BREG RTC WCO IOSS GPIO PCLK SAR ADC (12-bit) SARMUX Programmable Analog DAC (12-bit) CTBm Programmable Digital UDB... UDB Peripheral Interconnect (MMIO, PPU) LP Comparator CapSense TCPWM (TIMER,CTR,QD, PWM) Serial Comm (SCB) (I2C,SPI,UART,LIN,SMC) Port Interface & Digital System Interconnect (DSI) Serial Comm (SCB) (I2C,SPI, Deep Sleep) LCD Audio Subsystem I2S Master/Slave PDM/PCM Bluetooth Low Energy Subsystem BLE 4.2 Programmable Link Layer Digital Interface BLE 2 Mbps Radio Energy Profiler EFUSE Serial Memory I/F (QSPI with OTF Encryption/Decryption)) DMA MMIO USB-FS Host + Device Power Modes Active/Sleep LowePowerActive/Sleep DeepSleep Hibernate Backup IO Subsystem High Speed I/O Matrix, Smart I/O, Boundary Scan GPIO FS/LS PHY The block diagram shows the device subsystems and gives a simplified view of their interconnections. The color-code shows the lowest power mode where the particular block is still functional (for example, LP comparator is functional in Deep-Sleep mode). 1.2 CPU Subsystem (CPUSS) CPU The CPU subsystem in PSoC 6 MCUs consists of two ARM Cortex cores and their associated buses and memories: M4 with floating-point unit and memory protection units (FPU and MPU) and M0+ with an MPU. The Cortex M0+ provides a secure, uninterruptible boot function. This guarantees that post-boot, system integrity is checked and privileges enforced. Shared resources can be accessed through the normal ARM multi-layer bus arbitration. Exclusive accesses are supported by an inter-processor communication (IPC) scheme, which implements hardware semaphores and protection DMA Controllers PSoC 6 MCUs have DMA controllers that support independent access to peripherals using the AHB multilayer bus Flash PSoC 6 MCUs have a flash module with one block that can be used for EEPROM emulation for longer retention. It also has a block of flash that can be securely locked and is accessible only via a key lock that cannot be changed (onetime programmable). The flash block supports Read-While- Write (RWW) operation so that flash updates may be performed while the CPU is active SRAM PSoC 6 MCUs have an SRAM module, which can be retained in Deep-Sleep mode either fully or in increments of user-designated blocks SROM PSoC 6 MCUs have a supervisory ROM that contains boot and configuration routines. This ROM guarantees secure boot if authentication of user flash is required OTP efuse The OTP memory can provide a unique and unalterable identifier on a per-chip basis. This unalterable key can be used to access the secured flash Program and Debug PSoC 6 MCUs have extensive support for programming, testing, debugging, and tracing both hardware and firmware. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support 22 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

23 Introduction debug. The PSoC Creator integrated development environment (IDE) provides fully-integrated programming and debug support for PSoC 6 MCUs. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third-party probes. With the ability to disable debug features, with robust flash protection, and by allowing customerproprietary functionality to be implemented in on-chip programmable blocks, the PSoC 6 MCU family provides a high level of security. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. 1.3 System Resources Subsystem (SRSS) Power System The power system confirms that voltage levels meet the requirements for the respective mode and will either delay mode entry (on power-on reset, for example) until voltage levels meet requirements or generate resets (brownout detect) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels and the reset. There are no voltage sequencing requirements. The VDD core logic supply feeds an on-chip LDO, which produces the core logic supply. In addition, the device includes an on-chip buck regulator that can be used to power the core Clocking System The PSoC 6 MCU clock system provides clocks to subsystems that require clocks and switches between different clock sources without glitches. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC 6 MCU consists of the internal main oscillator (IMO), the internal low-speed oscillator (ILO), the precision internal low-speed oscillator (PILO), the external crystal oscillator, and the watch crystal oscillator (WCO). One phase-locked loop (PLL) and one frequency-locked loop (FLL) are used to generate high-speed clocks from either the IMO or the crystal oscillator or from an external clock supplied from a pin. The PLL and FLL enable independent clock frequencies for peripherals. Clocks may be buffered and brought out to a pin on a smart I/O port IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 6 MCU. It is trimmed during testing to achieve the specified accuracy. The IMO may be locked to a more accurate clock source to obtain higher accuracy ILO Clock Source The ILO is a very low-power oscillator, which may be used to generate clocks for peripheral operation in Deep-Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO. This allows watchdog operation during deep sleep and hibernate, and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register Clock Dividers Integer and fractional clock dividers are provided for peripheral use and timing purposes. The clock dividers are 16 and 24 bits in length to allow very fine clock control Reset PSoC 6 MCUs can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which allows the software to determine the cause of the reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration GPIO The GPIO pins are organized in logical entities called ports, which are eight bits in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it. Four GPIO pins are capable of overvoltage tolerant (OVT) operation where the input voltage may be higher than VDD (these may be used for I 2 C functionality to allow powering the chip off while maintaining physical connection to an operating I 2 C bus without affecting its functionality). GPIO pins can be ganged to sink 16 ma or higher values of sink current. GPIO pins may not be pulled up higher than 3.6 V. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 23

24 Introduction 1.4 Analog Subsystem bit SAR ADC PSoC 6 MCUs have a 12-bit SAR ADC. The SAR is connected to a fixed set of pins through an eight-input sequencer. The sequencer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth remains the same whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware-driven switching. The sequencer supports the buffering of each channel to reduce CPU interruptservice requirements. To accommodate signals with varying source impedances and frequencies, different sample times can be programmed for each channel. Also, the signal range specification through a pair of range registers (low- and high-range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other temperaturedependent functions. The SAR is not available in Deep- Sleep and Hibernate modes because it requires a highspeed clock Temperature Sensor The PSoC 6 MCU has an on-chip temperature sensor. This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value by using a Cypress-supplied software that includes calibration and linearization bit Digital-to-Analog Converter The PSoC 6 MCU has a 12-bit voltage mode DAC, which may be driven by the DMA controllers to generate userdefined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output Continuous Time Block (CTBm) This block consists of two opamps, which have their inputs and outputs connected to fixed pins and have three power modes and a comparator mode. The outputs of these opamps can be used as buffers for the SAR inputs. The noninverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware. The opamps can be set to one of the four power levels; the lowest level allowing operation in Deep-Sleep mode to preserve low performance continuous-time functionality in Deep-Sleep mode. The DAC output can be buffered through an opamp Low-Power Comparators PSoC 6 MCUs have a pair of low-power comparators, which can operate in Deep-Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels in Deep-Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator-switch event CapSense The CapSense system, used primarily for touch sensing, can measure the self-capacitance of an electrode or the mutual capacitance between a pair of electrodes. CapSense provides industry's best-in-class signal-to-noise ratio (SNR), high touch sensitivity, low-power operation, and superior EMI performance. CapSense touch sensing also supports liquid-tolerant operation using a driven shield signal. Any analog-capable GPIO can be used as a sensor or shield electrode. In addition to capacitive sensing, the CapSense system can function as an ADC to measure voltage on any GPIO pin that supports the CapSense functionality. Moreover, If the CapSense block is not used for touch sensing or ADC functionality, a CapSense comparator and the two 8-bit IDACs can be used as general-purpose analog blocks. 1.5 Programmable Digital Smart I/O The PSoC 6 MCU has two smart I/O blocks, which allow Boolean operations on signals going to the GPIO pins from the device subsystems or on signals coming into the device. Operation can be synchronous or asynchronous and the blocks operate in low-power modes, such as Deep-Sleep and Hibernate. This allows, for example, detection of logic conditions that can indicate that the CPU should wake up instead of waking up on general I/O interrupts, which consume more power and can generate spurious wakeups Universal Digital Blocks (UDBs) and Port Interfaces The PSoC 6 MCU supports custom programmable digital functions using UDBs, which also provide a switched digital system interconnect (DSI) fabric that allows signals from 24 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

25 Introduction peripherals and ports to be routed to and through the UDBs for communication and control. 1.6 Digital Subsystem Timer/Counter/PWM Block The timer/counter/pwm block consists of counters with user-programmable period length. It has a capture register, which records the count value of an event (such as an I/O event), a period register, which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals, which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs must be shut off immediately with no time for software intervention Serial Communication Blocks (SCB) PSoC 6 MCU SCBs can implement communication interfaces such as I 2 C, UART, or SPI I 2 C Mode The hardware I 2 C block implements a full multimaster and slave interface (it is capable of multimaster arbitration). This block has flexible buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C, which creates a mailbox address range in the PSoC 6 MCU memory and effectively reduces the I 2 C communication to reading from and writing to an array in the memory. In addition, the block supports an eight-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is useful in the absence of DMA. The I 2 C peripheral is compatible with I 2 C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I 2 C-bus specification and user manual (UM10204). The I 2 C bus I/O is implemented with GPIO in open-drain modes UART Mode This is a full-feature UART that supports automotive singlewire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An eight-deep FIFO tolerates much greater CPU service latencies SPI Mode The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI codecs), and National Microwire (halfduplex form of SPI). The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory Serial Memory Interface (SMIF) A serial memory interface has selectable 1-, 2-, or 4-bit widths. This block also supports on-the-fly encryption and decryption to support Execute-In-Place operation Audio Subsystem This subsystem consists of an I 2 S block and two PDM channels. The PDM channels interface to a PDM microphone's bit-stream output. 1.7 BLE Subsystem (BLESS) The PSoC 6 MCU incorporates a Bluetooth Smart subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian frequency shift keying (GFSK) packets at 1 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 4.2. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as human computer interface (HCI) and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50- antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. Key features of BLESS are as follows: Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 25

26 Introduction L2CAP connection-oriented channel (Bluetooth 4.1 feature) Broadcaster, Observer, Peripheral, and Central roles User-defined advertising data Multiple bond support GATT client and server Supports GATT sub-procedures 32-bit universally unique identifier (UUID) (Bluetooth 4.1 feature) Supports all SIG-adopted BLE profiles Security Manager (SM) Pairing methods: Just works, Passkey Entry, and Out of Band LE Secure Connection Pairing model Authenticated man-in-the-middle (MITM) protection and data signing 26 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

27 2. Getting Started 2.1 Support Free support for PSoC 6 MCUs is available online at Resources include training seminars, discussion forums, application notes, PSoC consultants, CRM technical support , knowledge base, and application support engineers. For application assistance, visit Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available at Critical updates to system documentation are also provided in the Documentation section. 2.3 Development Kits The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC projects. Visit the Cypress Online Store website at Under Products, click Programmable System-on-Chip to view a list of available items. Development kits are also available from Digi-Key, Avnet, Arrow, and Future. 2.4 Application Notes Refer to application note AN Getting Started with PSoC 6 MCU with BLE for additional information on PSoC 6 MCU capabilities and to quickly create a simple PSoC application using PSoC Creator and PSoC 6 MCU development kits. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 27

28 Getting Started 28 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D

29 3. Document Construction This document includes the following sections: Section B: CPU Subsystem on page 33 Section C: System Resources Subsystem (SRSS) on page 123 Section D: Digital Subsystem on page 219 Section E: Analog Subsystem on page 425 Section F: BLE Subsystem (BLESS) on page Major Sections For ease of use, information is organized into sections and chapters that are divided according to device functionality. Section Presents the top-level architecture, how to get started, and conventions and overview information of the product. Chapter Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementation and use information for some aspect of the integrated circuit. Glossary Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are presented in bold, italic font throughout. Registers Technical Reference Manual Supplies all device register details summarized in the technical reference manual. This is an additional document. 3.2 Documentation Conventions This document uses only four distinguishing font types, besides those found in the headings. The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this document. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples Register Conventions Register conventions are detailed in the PSoC 63 with BLE Registers TRM Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h (for example, 14h or 3Ah ) and hexadecimal numbers may also be represented by a 0x prefix, the C coding convention. Binary numbers have an appended lowercase b (for example, b or b ). Numbers not indicated by an h or b are decimal. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No Rev. *D 29