5th Generation Touchscreen Controller for Mobile Phones and Tablets. Hot Chips 2013 Milton Ribeiro John Carey August, 2013

Transcription

1 5th Generation Touchscreen Controller for Mobile Phones and Tablets Hot Chips 2013 Milton Ribeiro John Carey August, 2013

2 Design Goals Quick design of derivatives Platform-based design Scalable analog front-end (AFE) Scalable DSP datapath Flexible hardware platform Superior noise suppression performance Display noise: DCV com, AC Vcom, OLED Finger-couple noise (charger noise): > 40 Vpp Innovation acceleration thru flexible hardware Glove and hover support Robust water rejection and wet finger tracking Passive stylus support Active stylus support 2

3 Architectural Elements (I) CPU Cortex 48 MHz Support for flash memory (scalable) Support for SRAM (scalable) Support for ROM memory (scalable) Low-power microcontroller infrastructure Support for Hibernate, Deep-sleep, Sleep, Idle and Active modes On-chip power generation (LDO and voltage pump) Robust analog front-end (AFE) Large on-chip integration capacitors Signal attenuators in each channel Large charge handling capability: > 240 pcper cycle High-speed operation: up to 1 Msps 3

4 Architectural Elements (II) High-voltage signal generation On-chip charge pump for 10V generation Configurable DSP datapath Low-power linear and non-linear filtering FIR and window filters Median filtering Digital quadrature demodulation for active stylus Real-time noise-metrics 2D image processing algorithms: filtering, peak-search, etc. Table-driven sequencer Flexible timing generation enables advanced scanning modes Easy integration with DDI ASICs for incell and oncell integration 4

5 Gen5 Architecture Overview TSS To / From Panel RX / TX Mu ux + pads RX IDAC VREF RX Channels Infra (support, test) CE SEQ HW acceleration HW acceleration AHB I/F Registers ARM CM0, SRAM ROM Flash etc TX Shield Driver Slew Control TX Pump VCCTX ext or C ext VDDA 5

6 TSG5_L Touchscreen Controller TSG5-L ASSP M0S8 Architecture 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog CPU Subsystem SWD/TC Cortex M0 48 MHz FAST MUL NVIC, IRQMX Peripherals IOSS GPIO (2x ports) PCLK SPCIF FLASH 64 kb Read Accelerator SRAM 12 kb SRAM Controller System Interconnect (Single Layer AHB) Serial Comm 512B Peripheral Interconnect (MMIO) Capacitance Map TSS-G5 TSS-IF 21x RX Channels (incl. LX) ROM 8 kb ROM Controller Noise Map Sequencer Channel Engine, Deconvolution, Local Max TSTX (pump) ARM CM0 ARM Debug Low power CY S8 Process 130nm FLASH 10V capable Power Modes Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 4x GPIO, 2x SIO IO Subsystem 58x TXRX 6

7 TSG5 RX AFE Architecture Per-edge signal processing, 40V charger noise Per-channel H/W Baselining Single-edge Integrator Per-channel ADC Touch Sensor Atten. 8b SAR VX VX Vref 7

8 Gen5: Application of Flexible Timing Generation D67 = integrate for 2/3 of the period, or 67% duty cycle Removes 3 rd /6 th /9 th harmonics, e.g. for F TX =100kHz that s 300/600/900kHz Esp. effective for slow panels. 1.5x noise immunity for all the higher-freq noise Channel F TX =100kHz With D67 F TX 3F TX 5F TX 7F TX 9F TX Without Duracell Charger 8

9 Gen 4/5 Comparison Feature Gen 4 Gen 5 TX drive (square wave) V V,C ext or V TX MPTX 4 Full axis TX frequency 300kHz 500kHz Max RX sample rate 2 TX (sub-int) ½ TX (=per edge) HW Baseline Cal. Yes Yes, larger Max RX charge 8pC/edge pC/edge RX ADC 10b SAR, shared 8b SAR per ch. LX channel Yes Yes LCD sync Int/ext Int/ext Signal processing M0 CPU, 32b CPU or CE Noise metric CPU CPU or CE Autom. sequencing Yes Yes, table driven Self & Mutual Cap Yes Yes V DDD V V V CCA (core) 2.4V V 9

10 Current Status and Future Developments Smartphone and tablet devices available today TGS5_M: 36 I/Os and 11 channels, supporting phones up to 4.7 TSG5_L: 58 I/Os and 21 channels, supporting phones and tablets up to 9 Large tablet and notebook device available later in the year 10

11 Thank You 11