HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

Transcription

1 Features High-speed access Commercial: /25/35/55 (max.) Industrial: 25/55 (max.) Low-power operation IDT71321/IDT71421 ctive: 325mW (typ.) Standby: 5mW (typ.) IDT71321/421 ctive: 325mW (typ.) Standby: 1mW (typ.) Two INT flags for port-to-port communicatio Functional Block Diagram HIGH SPEED 2K X 8 DUL-PORT STTIC RM WITH INTERRUPTS IDT71321/ IDT71421/ MSTER IDT71321 easily expands data bus width to 16-ormore-bits using SVE IDT71421 On-chip port arbitration logic (IDT71321 only) BUSY output flag on IDT71321; BUSY input on IDT71421 Fully asynchronous operation from either port Battery backup operation 2V data retention ( only) TTL-compatible, single 5V ±1% power supply vailable in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP Industrial temperature range ( 4 C to +85 C) is available for selected speeds Green parts available, see ordering information OEL OER L R/WL R R/WR L- 7L Control Control R-7R BUSYL (1,2) (1,2) BUSYR 1L L ddress Decoder MEMORY RRY ddress Decoder 1R R L OEL R/WL RBITRTION and INTERRUPT LOGIC R OER R/WR INTL (2) 1. IDT71321 (MSTER): BUSY is open drain output and requires pullup resistor of 27Ω. IDT71421 (SVE): BUSY is input. 2. Open drain output: requires pullup resistor of 27Ω. INTR 2691 drw 1 (2) 8 Integrated Device Technology, Inc. 1 OCTOBER 8 DSC-2691/13

2 IDT71321/ and IDT71421/ Description The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static RMs with internal interrupt logic for interprocessor communicatio. The IDT71321 is designed to be used as a stand-alone 8-bit Dual- Port Static RM or as a "MSTER" Dual-Port Static RM together with the IDT71421 "SVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MSTER/SVE Dual-Port Static RM approach in 16-or-more-bit memory system applicatio results in full speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and pi that permit independent, asynchronous access for reads or writes to any location in memory. n automatic power down feature, controlled by, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power () versio offer battery backup data retention capability, with each Dual- Port typically couming µw from a 2V battery. The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs, 64-pin TQFPs, and 64-pin STQFPs. Pin Configuratio (1,2,3) EX L L 1L OE L INT BUSY R/W V R/W BUSY INT L L L CC R R R R 1R 1L 2L 3L 4L 5L 6L 7L 8L 9L L 1L 2L 3L IDT71321/421J 41 J52-1 (4) 4 PLCC 39 Top View (5) L 5L 6L 7L NC GND R 1R 2R 3R 4R 5R 6R OE R 1R 2R 3R 4R 5R 6R 7R 8R 9R NC R 7R 2691 drw 2, EX 1L INTL BUSYL R/WL L VCC VCC R R/WR BUSYR INTR 1R 1. ll VCC pi must be connected to power supply. 2. ll GND pi must be connected to ground supply. 3. J52-1 package body is approximately.75 in x.75 in x.17 in. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. PP64-1 package body is approximately 1mm x 1mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. OEL L 1L 2L 3L 4L 5L 6L 7L 8L 9L L 1L 2L L 4L 5L IDT71321/421PF or TF PN64-1 / PP64-1 (4) 64-Pin TQFP 64-Pin STQFP Top View (5) L 7L GND GND R 1R 2R 3R 4R 5R OER R 1R 2R 3R 4R 5R 6R 7R 8R 9R 7R 33 6R 2691 drw 3,

3 IDT71321/ and IDT71421/ Capacitance (1) (T = +25 C, f = 1.MHz) TQFP Only Symbol Parameter Conditio (2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pf COUT Output Capacitance VOUT = 3dV 1 pf 2691 tbl 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from V to 3V or from 3V to V. Recommended Operating Temperature and Supply Voltage (1,2) Grade mbient Temperature GND Vcc Commercial O C to +7 O C V 5.V + 1% Industrial -4 O C to +85 O C V 5.V + 1% 2691 tbl 2 1. This is the parameter T. This is the "itant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. bsolute Maximum Ratings (1) Symbol Rating Commercial ustrial VTERM (2) TBIS TSTG IOUT Terminal Voltage with Respect to GND Temp erature Under Bias Storage Temp erature DC Output Current Unit -.5 to +7. V -55 to +125 o C - to + o C 5 m Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage (2) V VIL Input Low Voltage -.5 (1).8 V 1. VIL (min.) = -1.5V for pulse width less than VTERM must not exceed Vcc + 1% tbl tbl 1 1. Stresses greater than those listed under BSOLUTE MXIMUM RTINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of the specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed VCC + 1% for more than 25% of the cycle time or 1 maximum, and is limited to < m for the period of VTERM > VCC + 1%

4 IDT71321/ and IDT71421/ DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1,4) (VCC = 5.V ± 1%) 71321X 71421X 71321X X25 Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit ICC ISB1 ISB2 ISB3 Dynamic Operating Current (Both Ports ctive) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) L and R = VIL, Outputs Disabled f = fmx (2) COM'L L and R = VIH COM'L f = fmx (2) "" = VIL and "B" = VIH (5) ctive Port Outputs Disabled, f=fmx (2) L and R > VCC -.2V, VIN > VCC -.2V or VIN <.2V, f = (3) COM'L COM'L m m m m ISB4 Full Standby Current (One Port - CMOS Level Inputs) "" <.2V and "B" > VCC -.2V (5) VIN > VCC -.2V or VIN <.2V ctive Port Outputs Disabled, f = fmx (2) COM'L m 2691 tbl 4a 71321X X X X55 Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit ICC Dynamic Operating Current (Both Ports ctive) L and R = VIL, Outputs Disabled f = fmx (2) COM'L m ISB1 Standby Current (Both Ports - TTL Level Inputs) L and R = VIH COM'L f = fmx (2) m ISB2 Standby Current (One Port - TTL Level Inputs) "" = VIL and "B" = VIH (5) ctive Port Outputs Disabled, f=fmx (2) COM'L m ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) L and R > VCC -.2V, VIN > VCC -.2V or VIN <.2V, f = (3) COM'L m ISB4 Full Standby Current (One Port - CMOS Level Inputs) "" <.2V and "B" > VCC -.2V (5) VIN > VCC -.2V or VIN <.2V ctive Port Outputs Disabled, f = fmx (2) COM'L m 2691 tbl 4b 1. 'X' in part numbers indicates power rating ( or ). 2. t f = fmx, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using C TEST CONDITIONS of input levels of GND to 3V. 3. f = mea no address or control lines change. pplies only to inputs at CMOS level standby. 4. Vcc = 5V, T=+25 C for Typ and is not production tested. Vcc DC = 1m (Typ) 5. Port "" may be either left or right port. Port "B" is opposite from port ""

5 IDT71321/ and IDT71421/ DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.V ± 1%) Symbol Parameter Test Conditio Min. Max. Min. Max. Unit ILI Input Leakage Current (1) VCC = 5.5V, VIN = V to VCC ILO Output Leakage Current (1) = VIH, VOUT = V to VCC, VCC - 5.5V 1 5 µ 1 5 µ VOL Output Low Voltage (-7) IOL = 4m.4.4 V VOL Open Drain Output Low Voltage (BUSY/INT) IOL = 16m.5.5 V VOH Output High Voltage IOH = -4m V NOTE: 1. t Vcc < 2.V leakages are undefined tbl 5 Data Retention Characteristics ( Version Only) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2. V ICCDR Data Retention Current VCC = 2.V, > VCC -.2V COM'L 1 µ VIN > VCC -.2V or VIN <.2V 1 4 µ tcdr (3) Chip Deselect to Data Retention Time tr (3) Operation Recovery Time trc (2) 1. VCC = 2V, T = +25 C, and is not production tested. 2. trc = Read Cycle Time 3. This parameter is guaranteed but not production tested tbl 6 Data Retention Waveform DT RETENTION MODE VCC 4.5V VDR 2.V 4.5V tcdr tr VIH VDR VIH 2691 drw 4,

6 IDT71321/ and IDT71421/ C Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.V 5 1.5V 1.5V Figures 1,2 and tbl 7 5V 5V 125Ω 125Ω DT OUT 775Ω 3pF* DT OUT 775Ω 5pF* *1pF for 55 versio Figure 1. C Output Test Load 5V Figure 2. Output Test Load (for thz, tlz, twz, and tow) * Including scope and jig. 27Ω BUSY or INT 2691 drw 5 3pF* *1pF for 55 versio Figure 3. BUSY and INT C Output Test Load

7 IDT71321/ and IDT71421/ C Electrical Characteristics Over the Operating Temperature Supply Voltage Range (2) 71321X 71421X 71321X X25 Symbol Parameter Min. Max. Min. Max. Unit RED CYCLE trc Read Cycle Time 25 t ddress ccess Time 25 t Chip Enable ccess Time 25 toe Output Enable ccess Time toh Output Hold from ddress Change 3 3 tlz Output Low-Z Time (1,3) thz Output High-Z Time (1,3) 1 1 tpu Chip Enable to Power Up Time (3) tpd Chip Disable to Power Down Time (3) tbl 8a 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit RED CYCLE trc Read Cycle Time t ddress ccess Time t Chip Enable ccess Time toe Output Enable ccess Time 25 toh Output Hold from ddress Change 3 3 tlz Output Low-Z Time (1,3) 5 thz Output High-Z Time (1,3) 25 tpu Chip Enable to Power Up Time (3) tpd Chip Disable to Power Down Time (3) Traition is measured mv from Low or High-impedance voltage Output Test Load (Figure 2). 2. 'X' in part numbers indicates power rating ( or ). 3. This parameter is guaranteed by device characterization, but is not production tested tbl 8b

8 IDT71321/ and IDT71421/ Timing Waveform of Read Cycle No. 1, Either Side (1) DDRESS trc t toh toh DTOUT BUSYOUT PREVIOUS DT VLID DT VLID tbddh (2,3) 2691 drw 6 1. R/W = VIH, = VIL, and is OE = VIL. ddress is valid prior to the coincidental with traition LOW. 2. tbdd delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operatio BUSY has no relatiohip to valid output data. 3. Start of valid data depends on which timing becomes effective last toe, t, t, and tbdd. Timing Waveform of Read Cycle No. 2, Either Side (3) t OE (4) toe (2) thz (1) (2) tlz thz DTOUT ICC CURRENT ISS tpu 5% (1) tlz VLID DT (4) tpd 5% 2691 drw 7 1. Timing depends on which signal is asserted last, OE or. 2. Timing depends on which signal is de-asserted first, OE or. 3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with traition LOW. 4. Start of valid data depends on which timing becomes effective last toe, t, t, and tbdd

9 IDT71321/ and IDT71421/ C Electrical Characteristics Over the Operating Temeprature and Supply Voltage Range (4) 71321X 71421X 71321X X25 Symbol Parameter Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time (2) 25 tew Chip Enable to End-of-Write tw ddress Valid to End-of-Write ts ddress Set-up Time twp Write Pulse Width (3) twr Write Recovery Time tdw Data Valid to End-of-Write 1 12 thz Output High-Z Time (1) 1 1 tdh Data Hold Time twz Write Enable to Output in High-Z (1) 1 1 tow Output ctive from End-of-Write (1) 2691 tbl 9a 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time (2) tew Chip Enable to End-of-Write 3 4 tw ddress Valid to End-of-Write 3 4 ts ddress Set-up Time twp Write Pulse Width (3) 25 3 twr Write Recovery Time tdw Data Valid to End-of-Write thz Output High-Z Time (1) 25 tdh Data Hold Time twz Write Enable to Output in High-Z (1) 3 tow Output ctive from End-of-Write (1) 2691 tbl 9b 1. Traition is measured mv from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. For Master/Slave combination, twc = tb + twp, since R/W = VIL must occur after tb. 3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the drivers to turn off data to be placed on the bus for the required tdw. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 4. 'X' in part numbers indicates power rating ( or )

10 IDT71321/ and IDT71421/ Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) (1,5,8) twc DDRESS thz (7) OE tw ts (6) twp (2) twr (3) thz (7) R/W twz (7) tow DT OUT (4) (4) tdw tdh DT IN 2691 drw 8 Timing Waveform of Write Cycle No. 2, ( Controlled Timing) (1,5) DDRESS R/W twc tw ts (6) tew (2) (3) twr tdw tdh DTIN 2691 drw 9 1. R/W or must be HIGH during all address traitio. 2. write occurs during the overlap (tew or twp) of = VIL and R/W= VIL. 3. twr is measured from the earlier of or R/W going HIGH to the end of the write cycle. 4. During this period, the l/o pi are in the output state and input signals must not be applied. 5. If the LOW traition occurs simultaneously with or after the R/W LOW traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Traition is measured mv from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the drivers to turn off data to be placed on the bus for the required tdw. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp

11 IDT71321/ and IDT71421/ C Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (6) 71321X 71421X 71321X X25 Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (For MSTER 71321) tb BUSY ccess Time from ddress tbd BUSY Disable Time from ddress tbc BUSY ccess Time from Chip Enable tbdc BUSY Disable Time from Chip Enable twh Write Hold fter BUSY (5) 12 twdd Write Pulse to Data Delay (1) 5 5 tddd Write Data Valid to Read Data Delay (1) tps rbitration Priority Set-up Time (2) 5 5 tbdd BUSY Disable to Valid Data (3) BUSY INPUT TIMING (For SVE 71421) twb Write to BUSY Input (4) twh Write Hold fter BUSY (5) 12 twdd Write Pulse to Data Delay (1) 4 5 tddd Write Data Valid to Read Data Delay (1) X X X X55 Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (For MSTER 71321) tb BUSY ccess Time from ddress 3 tbd BUSY Disable Time from ddress 3 tbc BUSY ccess Time from Chip Enable 3 tbdc BUSY Disable Time from Chip Enable 3 twh Write Hold fter BUSY (5) twdd Write Pulse to Data Delay (1) 6 8 tddd Write Data Valid to Read Data Delay (1) tps rbitration Priority Set-up Time (2) 5 5 tbdd BUSY Disable to Valid Data (3) 35 5 BUSY INPUT TIMING (For SVE 71421) twb Write to BUSY Input (4) twh Write Hold fter BUSY (5) twdd Write Pulse to Data Delay (1) 6 8 tddd Write Data Valid to Read Data Delay (1) tbl 1a 1. Port-to-port delay through RM cells from the writing port to the reading port, refer to Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To eure that the earlier of the two ports wi. 3. tbdd is a calculated parameter and is the greater of, twdd twp (actual) or tddd tdw (actual). 4. To eure that a write cycle is inhibited on port "B" during contention on port "". 5. To eure that a write cycle is completed on port "B" after contention on port "". 6. 'X' in part numbers indicates power rating ( or ) tbl 1b

12 IDT71321/ and IDT71421/ Timing Waveform of Write with Port-to-Port Read and BUSY (2,3,4) twc DDR"" MTCH twp R/W "" DTIN "" DDR"B" tps (1) tdw VLID MTCH tdh tb tbd tbdd BUSY"B" twdd DTOUT"B" VLID tddd 1. To eure that the earlier of the two ports wi. tps is ignored for Slave (IDT71421). 2. L = R = VIL 3. OE = VIL for the reading port. 4. ll timing is the same for the left and right ports. Port "" may be either the left or right port. Port "B" is opposite from port "" drw 1 Timing Waveform of Write with BUSY (4) twp R/W"" (3) twb BUSY"B" R/W"B" (2) (1) twh, 2691 drw twh must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. twb is only for the slave version (IDT71421). 4. ll timing is the same for the left and right ports. Port "" may be either the left or right port. Port "B" is opposite from port ""

13 IDT71321/ and IDT71421/ Timing Waveform of BUSY rbitration Controlled by Timing (1) DDR "" ND "B" DDRESSES MTCH "B" tps (2) "" BUSY"" tbc tbdc 2691 drw 12 Timing Waveform of BUSY rbritration Controlled by ddress Match Timing (1) trc or twc DDR"" DDR"B" tps (2) DDRESSES MTCH DDRESSES DO NOT MTCH BUSY"B" tb tbd 2691 drw ll timing is the same for left and right ports. Port may be either left or right port. Port B is the opposite from port. 2. If tps is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only). C Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) 71321X 71421X 71321X X25 Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING ts ddress Set-up Time twr Write Recovery Time tins Interrupt Set Time 25 tinr Interrupt Reset Time 'X' in part numbers indicates power rating ( or ) tbl 11a

14 IDT71321/ and IDT71421/ C Electrical Characteristics Over the Operating Temperature Supply Voltage Range (1) 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING ts ddress Set-up Time twr Write Recovery Time tins Interrupt Set Time tinr Interrupt Reset Time 'X' in part numbers indicates power rating ( or ) tbl 11b Timing Waveform of Interrupt Mode (1) SET INT DDR"" R/W"" INT"B" twc INTERRUPT DDRESS (3) ts (3) tins (2) (4) twr 2691 drw 14 CLER INT DDR"B" ts (3) trc INTERRUPT CLER DDRESS (2) OE"B" tinr (3) INT"B" 1. ll timing is the same for left and right ports. Port may be either left or right port. Port B is the opposite from port. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal ( or R/W) is asserted last. 4. Timing depends on which enable signal ( or R/W) is de-asserted first drw,

15 IDT71321/ and IDT71421/ Truth Tables Truth Table I. Non-Contention Read/Write Control (4) Left or Right Port (1) R/W OE D-7 Function X H X Z Port Disabled and in Power-Down Mode, ISB2 or ISB4 X H X Z R = L = VIH, Power-Down Mode, ISB1 or ISB3 L L X DTIN Data on Port Written Into Memory (2) H L L DTOUT Data in Memory Output on Port (3) H L H Z High Impedance Outputs 1. L 1L R 1R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see twdd and tddd timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON T CRE, 'Z' = HIGH IMPEDN 2691 tbl 12 Truth Table II. Interrupt Flag (1,4) Left Port Right Port R/WL L OEL 1L-L INTL R/WR R OER 1R-R INTR Function L L X 7FF X X X X X L (2) Set Right INTR Flag X X X X X X L L 7FF H (3) Reset Right INTR Flag X X X X L (3) L L X 7FE X Set Left INTL Flag X L L 7FE H (2) X X X X X Reset Left INTL Flag 1. ssumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON T CRE 2691 tbl 13 Truth Table III ddress BUSY rbitration Inputs Outputs L R L-1L R-1R BUSYL (1) BUSYR (1) Function X X NO MTCH H H Normal H X MTCH H H Normal X H MTCH H H Normal L L MTCH (2) (2) Write Inhibit (3) 2691 tbl Pi BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not pushpull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tps is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 6.42

16 IDT71321/ and IDT71421/ Functional Description The IDT71321/IDT71421 provides two ports with separate control, address and pi that permit independent access for reads or writes to any location in memory. The IDT71321/IDT71421 has an automatic power down feature controlled by. The controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the R = R/WR = VIL, per Truth Table II. The left port clears the interrupt by accessing address location 7FE when L = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRM location. If the interrupt function is not used, address locatio 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RM is Busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applicatio. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pi HIGH. If desired, unintended write operatio can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT71321 (Master) are open drain type outputs and require open drain resistors to operate. If these SRMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external ND gate. Width Expaion with Busy Logic Master/Slave rrays When expanding an SRM array in width while using BUSY logic, one master part is used to decide which side of the SRM array will receive a BUSY indication, and to output that indication. ny number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRMs the BUSY pin is an output if the part is Master (IDT71321), and the BUSY pin is an input if the part is a Slave (IDT71421) as shown in Figure 3. 27Ω 5V BUSYL MSTER Dual Port SRM BUSYL MSTER Dual Port SRM BUSYL BUSYR BUSYR SVE Dual Port SRM BUSYL SVE Dual Port SRM BUSYL BUSYR 2691 drw 16 Figure 3. Busy and chip enable routing for both width and depth expaion with IDT71321 (Master) and (Slave) IDT71421 SRMs. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operatio from one port for part of a word and inhibit the write operatio from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. BUSYR DECODER 5V BUSYR 27Ω

17 IDT71321/ and IDT71421/ Ordering Information XXXX Device Type 999 Power Speed Package Process/ Temperature Range BNK I (1) Commercial ( C to +7 C) Industrial (-4 C to +85 C) G (2) Green J PF TF pin PLCC (J52-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1) Commercial Only Commercial ustrial Commercial Only Commercial ustrial Speed in nanoseconds, Low Power Standard Power Contact your sales office for industrial temperature range availability in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 3/24/99: Initiated datasheet document history Converted to new format Cosmetic typographical correctio Pages 2 and 3 dded additional notes to pin configuratio 6/7/99: Changed drawing format 11/1/99: Replaced IDT logo 8/23/1: Page 3 Increased storage temperature parameters Clarified T parameter K (2K x 8-Bit) MSTER Dual-Port SRM w/ Interrupt 16K (2K x 8-Bit) SVE Dual-Port SRM w/ Interrupt 2691 drw 17 Page 4 DC Electrical parameters changed wording from "open" to "disabled" Page 16 Fixed part numbers in "Width Expaion" paragraph Changed ±5mV to mv in notes Page 4 Industrial temperature range offering added to DC Electrical Characteristisc for 25 and removed for 35 Page 7 and 9 Industrial temperature range added to C Electrical Characteristics for 25 Page 17 Industrial offering removed for 35 ordering information 1/17/6: Page 1 dded green availability to features Page 17 dded green indicator to ordering information Page 1 & 17 Replaced old IDTTM with new IDTTM logo 8/25/6: Page 14 Changed INT"" to INT"B" in the CLER INT drawing in the Timing Waveform of Interrupt Mode 1/29/8: Page 17 Removed "IDT" from orderable part number CORPORTE HEDQURTERS for LES: for Tech Support: 624 Silver Creek Valley Road or San Jose, C fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.