HIGH SPEED 64K (4K X 16 BIT) IDT70824S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )

Transcription

1 HIGH PEED 64K (4K X 16 BIT) IDT784/ EQUENTIA ACCE RANDOM ACCE MEMORY (ARAM ) Features High-speed access : /4 (max.) Commercial: ///4 (max.) ow-power operation IDT784 Active: 77mW (typ.) tandby: mw (typ.) IDT784 Active: 77mW (typ.) tandby: 1mW (typ.) 4K x 16 equential Access Random Access Memory (ARAM ) equential Access from one port and standard Random Access from the other port eparate upper-byte and lower-byte control of the Random Access Port High speed operation taa for random access port tcd for sequential port clock cycle time Architecture based on Dual-Port RAM cells Compatible with Intel BMIC and 84 PCI et Width and Depth Expandable equential side Address based flags for buffer control Pointer logic supports up to two internal buffers Battery backup operation - V data retention TT-compatible, single V (+%) power supply Available in 8-pin TQFP and 84-pin PGA product compliant to MI-PRF-8 QM Industrial temperature range ( 4 C to +8 C) is available for selected speeds Description The IDT784 is a high-speed 4K x 16-Bit equential Access Random Access Memory (ARAM). The ARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard RAM interface for the random (asynchronous) access port, and a clocked interface with counter se- Functional Block Diagram A-11 1 CE OE R/W B B MB UB CMD I/O- Random Access Port Controls 16 1 Data Addr 4KX16 Memory Array DataR AddrR 16 equential Access Port Controls Reg RT CK CNTEN OE TRT1 TRT CE R/W D I/O-, RT Pointer/ Counter tart Address for Buffer #1 End Address for Buffer #1 tart Address for Buffer # End Address for Buffer # Flow Control Buffer Flag tatus 1 COMPARATOR EOB1 EOB 99 drw 1 9 Integrated Device Technology, Inc JANUARY 9 DC-99/6

2 quencing for the sequential (synchronous) access port. Fabricated using CMO high-performance technology, this memory device typically operates on less than 77mW of power at maximum highspeed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT784 is packaged in a 8-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). grade product is manufactured in compliance with the latest revision of MI-PRF-8 QM, making it ideally suited to military temperature applicatio demanding the highest level of performance and reliability. Pin Configuratio (1,,) INDEX I/O1 I/O N/C CE R/W RT D TRT TRT1 CNTEN OE CK EOB EOB1 VCC I/O I/O IDT784PF PN8-1 (4) 11 8-Pin TQFP 1 Top View () 1 14 I/O VCC VCC VCC N/C A11 A A9 A8 A7 A6 A A4 A A VCC VCC A1 A CMD 16 CE 17 B 18 4 UB 19 4 R/W OE 99 drw I/O1 I/O4 I/O I/O6 I/O7 I/O I/O VCC I/O4 I/O I/O6 I/O7 I/O8 I/O9 I/O I/O11 I/O8 I/O9 I/O I/O11 I/O1 I/O1 I/O14 I/O I/O1 I/O1 I/O14 I/O, I/O1 VCC EOB1 CNTEN TRT R/W NC NC I/O NC I/O EOB OE RT D CE I/O I/O1 I/O I/O CK TRT1 I/O VCC I/O7 I/O6 IDT784G I/O8 I/O G84- (4) 1 6 I/O9 I/O I/O8 I/O9 I/O 84-Pin PGA I/O Top View () I/O4 VCC I/O4 I/O I/O I/O11 VCC I/O1 VCC I/O11 8 I/O1 I/O1 I/O14 I/O I/O14 NC CMD VCC A NC I/O I/O OE B A VCC A4 A7 A NC R/W UB CE A1 A A A6 A8 A9 A11 A B C D E F G H J K Pin 1 Designator 1. All VCC pi must be connected to power supply.. All pi must be connected to ground supply.. PN8-1 package body is approximately 14mm x 14mm x 1.4mm. G84- package body is approximately 1.1 in x 1.1 in x.16 in. 4. This package code is used to reference the package diagram.. This text does not indicate orientation of the actual part-marking drw,

3 Pin Descriptio: Random Access Port (1) YMBO NAME I/O DECRIPTION A-A11 Address ines I Address inputs to access the 496-word (16-Bit) memory array. I/O-I/O Inputs/Outputs I Random access data inputs/outputs for 16-Bit wide data. CE Chip Enable I When CE is OW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port CE and CMD may not be OW at the same time. CMD Control Register Enable I When CMD is OW, address lines A-A, R/W, and inputs and outputs I/O-I/O1, are used to access the control register, the flag register and the start and end of buffer registers. CMD and CE may not be OW at the same time. R/W Read/Write Enable I If CE is OW and CMD is HIGH, data is written into the array when R/W is OW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is OW, R/W is used to access the buffer command registers. CE and CMD may not be OW at the same time. OE Output Enable I When OE is OW and R/W is HIGH, I/O-I/O outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. B, UB ower Byte, Upper Byte Enables I When B is OW, I/O-I/O7 are accessible for read and write operatio. When B is HIGH, I/O-I/O7 are tristated and blocked during read and write operatio. UB controls access for I/O8-I/O in the same manner and is asynchronous from B. VCC Power upply I even + power supply pi. All VCC pi must be connected to the same +V VCC supply. Ground I Ten ground pi. All ground pi must be connected to the same ground supply. 99 tbl 1 Pin Descriptio: equential Access Port (1) YMBO NAME I/O DECRIPTION I/O- Inputs/Outputs I/O equential data inputs/outputs for 16-bit wide data. CK Clock I I/O-I/O,CE, R/W, and D are registered on the OW-to-HIGH traition of CK. Also, the sequential access port address pointer increments by 1 on each OW-TO-HIGH traition of CK when CNTEN is OW. CE Chip Enable I When CE is OW, the sequential access port is enabled on the OW-to-HIGH traition of CK. When CE is HIGH, the sequential access port is disabled into powered-down mode on the OW-to-HIGH traition of CK, and the I/O outputs are in the High-impedance state. All data is retained, unless altered by the random access port. CNTEN Counter Enable I When CNTEN is OW, the address pointer increments on the OW-to-HIGH traition of CK. This function is independent of CE. R/W Read/Write Enable I When R/W and CE are OW, a write cycle is initiated on the OW-to-HIGH traition of CK. When R/ W is HIGH, and CE and OE are OW, a read cycle is initiated on the OW-to-HIGH traition of CK. Termination of a write cycle is done on the OW-to-HIGH traition of CK if R/W or CE is HIGH. D Address Pointer oad Control I When D is sampled OW, there is an internal delay of one cycle before the address pointer changes. When D is OW, data on the inputs I/O-I/O11 is loaded into a data-in register on the OW-to-HIGH traition of CK. On the Cycle following D, the address pointer charges to the address location contained in the datain register. TRT1 and TRT may not be OW while D is OW or during the cycle following D. TRT1, TRT oad tart of Address Register I When TRT1 or TRT is OW, the start of address register #1 or # is loaded into the address pointer on the OW-to-HIGH traition of CK. The start addresses are stored in internal registers. TRT1 and TRT may not be OW while D is OW or during the cycle following D. EOB1, EOB End of Buffer Flag O EOB1 or EOB is output low when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RT OW or by writing zero into Bit and/or Bit 1 of the control registe r at address 1. EOB1 and EOB are dependent on separate internal registers, and therefore separate match addresses. OE Output Enable I OE controls the data outputs and is independent of CK. When OE is OW, output buffers and the sequentially addressed data is output. When OE is HIGH, the I/O output bus is in the High-impedance state. OE is asynchronous to CK. RT Reset I When RT is OW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB flags are set HIGH. RT is asynchronous to CK. NOTE: 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output. 99 tbl 6.4

4 Absolute Maximum Ratings (1) ymbol Rating Commercial & Industrial VTERM () TBIA TTG IOUT Terminal Voltage with Respect to Temperature Under Bias torage Temperature DC Output Current Unit -. to to +7. V - to +1-6 to +1 o C -6 to + -6 to + o C ma 99 tbl 1. tresses greater than those listed under ABOUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability.. VTERM must not exceed Vcc + % for more than % of the cycle time or maximum, and is limited to < ma for the period of VTERM > Vcc + %. Recommended Operating Temperature and upply Voltage Grade Ambient Temperature 99 tbl 4 1. This is the parameter TA. This is the "itant on" case temperature.. Industrial temperature: for specific speeds, packages and powers contact your sales office. Recommended DC Operating Conditio Vcc - O C to +1 O C V.V + % Commercial O C to +7 O C V.V + % Industrial -4 O C to +8 O C V.V + % ymbol Parameter Min. Typ. Max. Unit VCC upply Voltage 4... V Capacitance (TA = + C, f = 1.mhz, TQFP only) ymbol Parameter Conditio () Max. Unit CIN Input Capacitance VIN = dv 9 pf COUT Output Capacitance VOUT = dv pf Ground V VIH Input High Voltage. 6. () V VI Input ow Voltage -. (1).8 V 1. VI > -1.V for pulse width less than.. VTERM must not exceed Vcc + %. 99 tbl 1. This parameter is determined by device characterization, but is not production tested.. dv references the interpolated capacitance when the input and output signals switch from V to V or from V to V. 99 tbl 6 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (VCC =.V ± %) ymbol Parameter Test Conditio Min. Max. Min. Max. Unit II Input eakage Current VCC =.V, VIN = V to VCC IO Output eakage Current VOUT = V to VCC 1 µa 1 µa VO Output ow Voltage IO = +4mA.4.4 V VOH Output High Voltage IOH = -4mA.4.4 V 99 tbl 7 4

5 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,,8) (VCC =.V ± %) 784X 784X 784X 784X4 ymbol Parameter Test Condition Version Typ. () Max. Typ. () Max. Typ. () Max. Typ. () Max. Unit ICC IB1 IB IB IB4 Dynamic Operating Current (Both Ports Active) tandby Current (Both Ports - TT evel Inputs) tandby Current (One Port - TT evel Inputs) Full tandby Current (Both Ports - CMO evel Inputs) Full tandby Current (One Port - CMO evel Inputs) CE and CER = VI, Outputs Disabled CE = VI () f = fmax () CE and CE = VIH (7) CMD = VIH f = fmax () CE or CE = VIH Active Port Outputs Disabled, f=fmax () Both Ports CE and CE > VCC -.V (6) VIN > VCC -.V or VIN <. V, f = (4) One Port CE or CE > VCC -.V (6,7) Outputs Disabled (Active Port) f = fmax () VIN > VCC -.V or VIN <.V COM' MI & IND COM' MI & IND COM' MI & IND COM' MI & IND COM' MI & IND NOTE 1. 'X' in part number indicates power rating ( or ).. VCC = V, TA = + C; guaranteed by device characterization but not production tested.. At f = fmax, address, control lines (except Output Enable), and CK are cycling at the maximum frequency read cycle of 1/tRC. 4. f = mea no address or control lines change.. CE may traition, but is ow (CE=VI) when clocked in by CK. 6. CE may be -.V, after it is clocked in, since CK=VIH must be clocked in prior to powerdown. 7. If one port is enabled (either CE or CE = OW) then the other port is disabled (CE or CE = HIGH, respectively). CMO HIGH > Vcc -.V and OW <.V, and TT HIGH = VIH and OW = VI. 8. Industrial temperature: for specific speeds, packages and powers contact your sales office ma ma ma ma ma 99 tbl 8 Data Retention Characteristics Over All Temperature Ranges ( Version Only) (VC <.V, VHC > VCC -.V) ymbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention VCC = V. V ICCDR Data Retention Current CE = VHC VIN = VHC or = VC MI. & IND. 4 µa COM'. tcdr () Chip Deselect to Data Retention Time CE = VHC (4) when CK = u V tr ( ) Operation Recovery Time CMD > VHC trc () V NOTE : 1. TA = + C, VCC = V; guaranteed by device characterization but not production tested.. trc = Read Cycle Time. This parameter is guaranteed by device characterization, but is not production tested. 4. To initiate data retention, CE = VIH must be clocked in. 99 tbl 9 6.4

6 Data Retention Power Down/Up Waveform (Random and equential Port) (1,) DATA RETENTION MODE VCC 4.V VDR V 4.V tcdr tr CE VIH VDR VIH CK CE tpd tpu ICC IB NOTE : 1. CE is synchronized to the sequential clock input.. CMD > VCC -.V. IB 99 drw 4 V V 89Ω 89Ω DATAOUT DATAOUT 47Ω pf 47Ω pf* 99 drw 99 drw 6 Figure 1. AC Output Test oad Figure. Output Test oad (for tcz, tbz, toz, tchz, tbhz, tohz,z, tckhz, and tckz) (*Including scope and jig.) AC Test Conditio Input Pulse evels Input Rise/Fall Times Input Timing Reference evels Output Reference evels Output oad to.v Max. 1.V 1.V Figures 1, and 99 tbl taa/tcd/teb (Typical, ) pf is the I/O capacitance of this device, and pf is the AC Test oad capacitance CAPACITANCE (pf) 99 drw 7, Figure. umped Capacitance oad Typical Derating Curve 6

7 Truth Table I: Random Access Read and Write (1,) Inputs/Outputs CE CMD R/W OE B UB I/O-I/O7 I/O8-I/O MODE H H DATAOUT DATAOUT Read both Bytes. H H H DATAOUT High-Z Read lower Byte only. H H H High-Z DATAOUT Read upper Byte only. H H () DATAIN DATAIN Write to both Bytes. H H () H DATAIN High-Z Write to lower Byte only. H H () H High-Z DATAIN Write to upper Byte only. H H X X X X High-Z High-Z Both Bytes deselected and powered down. H H H X X High-Z High-Z Outputs disabled but not powered down. H X X H H High-Z High-Z Both Bytes deselected but not powered down. H H () (4) (4) DATAIN DATAIN Write I/O-I/O11 to the Buffer Command Register. H H (4) (4) DATAOUT DATAOUT Read contents of the Buffer Command Register via I/O-I/O1. 99 tbl H = VIH, = VI, X = Don't Care, and HIGH-Z = High-impedance.. RT, CE, CNTEN, R/W, D, TRT1, TRT, CK, I/O-I/O, EOB1, EOB, and OE are unrelated to the random access port control and operation.. If OE = VI during write, Z must be added to the twp or tcw write pulse width to allow the bus to float prior to being driven. 4. Byte operatio to control register using UB and B separately are also allowed. Truth Table II: equential Read (1,,,6,8) Inputs/Outputs CK CE CNTEN R/W EOB1 EOB OE I/O MODE H OW AT [EOB1] Counter Advanced equential Read with EOB1 reached. H H AT AT [EOB1-1] Non-Counter Advanced equential Read, without EOB1 reached H AT OW [EOB] Counter Advanced equential Read with EOB reched. H H AT AT [EOB - 1] Non-Counter Advanced equential Read without EOB reached H OW OW H High-Z Counter Advanced equential Non-Read with EOB1 and EOB reached Truth Table III: equential Write (1,,,4,,6,7,8) Inputs/Outputs 99 tbl 1 CK CE CNTEN R/W EOB1 EOB OE I/O MODE H AT AT H I/OIN Non-Counter Advanced equential Write, without EOB1 or EOB reached. OW OW H I/OIN Counter Advanced equential Write with EOB1 and EOB reached. H H X AT AT X High-Z No Write or Read due to equential port Deselect. No counter advance. H X NEXT NEXT X High-Z No Write or Read due to equential port Deselect. Counter does advance. 1. H = VIH, = VI, X = Don't Care, and HIGH-Z = High-impedance. OW = VO.. RT, D, TRT1, TRT are continuously HIGH during a sequential write access, other than pointer access operatio.. CE, OE, R/W, CMD, B, UB, and I/O-I/O are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. OE must be HIGH (OE=VIH) prior to write conditio only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock during the cycle in which R/W = VI.. I/OIN refers to I/O-I/O inputs. 6. "AT" refers to the previous value still being output, no change. 7. Termination of a write is done on the OW-to-HIGH traition of CK if R/W or CE is HIGH. 8. When CKEN=OW, the address is incremented on the next rising edge before any operation takes place. ee the diagrams called "equential Counter Enable Cycle after Reset, Read (and write) Cycle" tbl 1

8 Truth Table: equential Address Pointer Operatio (1,,,4,) Inputs/Outputs CK D TRT1 TRT1 OE MODE H H X Non-Counter Advanced equential Write, without EOB1 or EOB reached. H H X Counter Advanced equential Write with EOB1 and EOB reached. H H H (6) No Write or Read due to equential port Deselect. No counter advance. 1. H = VIH, = VI, X = Don't Care, and High-Z = High-impedance.. RT is continuously HIGH. The conditio of CE CNTEN, and R/W are unrelated to the sequential address pointer operatio.. CE, OE, R/W, B, UB, and I/O-I/O are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. Address pointer can also change when it reaches an end of buffer address. ee Flow Control Bits table.. When D is sampled OW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented during the two cycles. 6. OE may be OW with CE deselect or in the write mode using R/W. 99 tbl 14 Address Pointer oad Control (D) In D mode, there is an internal delay of one cycle before the address pointer changes in the cycle following D. When D is OW, data on the inputs I/O-I/O11 is loaded into a data-in register on the OW-to- HIGH traition of CK. On the cycle following D, the address pointer changes to the address location contained in the data-in register. TRT1, TRT may not be low while D is OW, or during the cycle following D. The TRT1 and TRT require only one clock cycle, since these addresses are pre-loaded in the registers already. D Mode (1) D CK (1) A B C I/O-11 ADDRIN DATAOUT TRT(1 or ) 99 drw 8 NOTE: 1. At CK edge (A), I/O-I/O11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address pointer changes). At CK edge (A), TRT1 and TRT must be HIGH to eure for proper sequential address pointer loading. At CK edge (B), D and TRT1, must be HIGH to eure for proper sequential address pointer loading. For TRT1 or TRT, the data to be read will be ready for edge (B), while data will not be ready at edge (B) when D is used, but will be ready at edge (C). equential oad of Address into Pointer/Counter (1) MB H 14 1 H H Address oaded into Pointer B I/O BIT NOTE: 1. "H" = VIH and "" = VI for the I/O intput state. 99 drw 9 8

9 Reset (RT) etting RT OW resets the control state of the ARAM. RT functio asynchronously of CK (i.e. not registered). The default states after a reset operation are displayed in the adjacent chart. Register Contents Address EOB Flags Buffer Flow Mode Cleared to HIGH state BUFFER CHAINING tart Address Buffer #1 (1) End Address Buffer #1 tart Address Buffer # (1) End Address Buffer # (1) Registered tate 49 (4K) Cleared (set at invalid points) Cleared (set at invalid points) CE = VIH, R/W = VI 99 tbl NOTE: 1. tart address and End of address for Buffer # and the Flow Control for both Buffer #1 and #, must be programmed as described in the "Buffer Command Mode" section. Buffer Command Mode (CMD) Buffer Command Mode (CMD) allows the random access port to control the state of the two buffers. Address pi A-A and I/O pi I/O- I/O11 are used to access the start of buffer and the end of buffer addresses and to set the flow control mode of each buffer. The Buffer Command Mode also allows reading and clearing the status of the EOB flags. even different CMD cases are available depending on the conditio of A-A and R/ W. Address bits A-A11 and data I/O bits I/O1-I/O are not used during this operation. Random Access Port CMD Mode (1) Case # A-A R/W DECRIPTION 1 (1) Write (read) the start address of Buffer #1 through I/O-I/O11. 1 (1) Write (read) the end address of Buffer #1 through I/O-I/O11. (1) Write (read) the start address of Buffer # through I/O-I/O (1) Write (read) the end address of Buffer # through I/O-I/O11. (1) Write (read) flow control register. 6 1 Write only - clear EOB1 and/or EOB flag Read only - flag status register. 8 1/111 (X) (Reserved) NOTE: 1. R/W input "(1)" indicates a write() or read(1) occurring with the same address input. 99 tbl 16 Cases 1 through 4: tart and End of Buffer Register Description (1,) MB H 14 1 H H Address oaded into Buffer B I/O BIT 99 drw 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "" = VI for I/O in the input state.. A write into the buffer occurs when R/W = VI and a read when R/W = VIH. EOB1/OB1 and EOB/OB are chosen through address A-A while CMD = VI and CE = VIH. Case : Buffer Flow Modes Within the ARAM, the user can designate one of two buffer flow modes for each buffer. Each buffer flow mode defines a unique set of actio for the sequential port address pointer and EOB flags. In BUFFER CHAIN- ING mode, after the address pointer reaches the end of the buffer, it sets the corresponding EOB flag and continues from the start address of the other buffer. In TOP mode, the address pointer stops incrementing after it reaches the end of the buffer. There is no linear or mask mode available

10 Flow Control Register Description (1,) MB H H H H H H H H H H H 4 1 B I/O BIT Counter Release (TOP Mode Only) Buffer #1 flow control Buffer # flow control 99 drw "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.. Writing a into bit 4 releases the address pointer after it is stopped due to the TOP mode and allows sequential write operatio to resume. This occurs asynchronously of CK, and therefore caution should be taken. The pointer will be at address EOB+ on the next rising edge of CK that is enabled by CNTEN. The pointer is also released by RT, D, TRT1 and TRT operatio. Flow Control Bits () Flow Control Bit 1 & Bit (Bit & Bit ) Mode Functional Description BUFFER CHAINING EOB1 (EOB) is asserted (Active OW output) when the pointer matches the end address of Buffer #1 (Buffer #). The pointer value is changed to the start address of Buffer # (Buffer #1) (1,) 1 TOP EOB1 (EOB) is asserted when the pointer matches the end address of Butler #1 (Butler #). The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is OW on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. equential write operatio are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,,4) 1. EOB1 and EOB may be asserted (set) at the same time, if both end addresses have been loaded with the same value.. CMD flow control bits are unchanged, the count does not continue advancement.. If EOB1 and EOB are equal, then the pointer will jump to the start of Buffer #1. 4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be OW on the next rising edge of CK; otherwise the flow control will remain in the stop mode.. Flow Control Bit settings of '' and '11' are reserved. 6. tart address and End of address for Buffer # and the Flow Control for both Buffer #1 and #, must be programmed as described in the "Buffer Command Mode" section. RT conditio are not set to valid addresses. Cases 6 and 7: Flag tatus Register Bit Description (1) MB H H H H H H H H H H H H H H 1 B I/OBIT 99 tbl 17 NOTE: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. Cases 6: Flag tatus Register Write Conditio (1) Flag tatus Bit, (Bit 1) Functional Description Clears Buffer Flag EOB1, (EOB). 1 No chang e to the Buffer Flag. () 99 tbl Either bit or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone, or both may be cleared.. Remai as it was prior to the CMD operation, either HIGH (1) or OW (). End of buffer flag for Buffer #1 End of buffer flag for Buffer # 99 drw 1 Case 7: Flag tatus Register Read Conditio Flag tatus Bit, (Bit 1) Functional Description EOB1 (EOB) flag has not been set, the Pointer has not reached the End of the Buffer. 1 EOB1 (EOB) flag has been set, the Pointer has reached the end of the Buffer. Cases 8 and 9: (Reserved) Illegal operatio. All outputs will be HIGH on the I/O bus during a READ. 99 tbl 19

11 Random Access Port: AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (,4,) 784X 784X 784X 784X4 ymbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. READ CYCE Unit trc Read Cycle Time 4 taa Address Access Time 4 tace Chip Enable Access Time 4 tbe Byte Enable Access Time 4 toe Output Enable Access Time toh Output Hold from Address Change tcz Chip elect ow-z Time (1) tbz Byte elect ow-z Time (1) toz Output Enable ow-z Time (1) tchz Chip elect High-Z Time (1). 1 tbhz Byte elect High-Z Time (1) 1 tohz Output elect High-Z Time (1) 9 11 tpu Chip elect Power-Up Time tpd Chip elect Power-Down Time 4 Random Access Port: AC Electrical Characteristics Over the Operating Temperature and upply Voltage (,4,) ymbol Parameter 784X 784X 784X 784X4 Min. Max. Min. Max. Min. Max. Min. Max. 99 tbl Unit WRITE CYCE twc Write Cycle Time 4 tcw Chip Enable to End-of-Write taw Address Valid to End-of-Write () ta Address et-up Time twp Write Pulse Width () 1 tbp Byte Enable Pulse Width () twr Write Recovery Time Z Write Enable Output High-Z Time (1) 1 tdw Data et-up Time 1 Data Hold Time tow Output Active from End-of-Write 1. Traition measured at mv from steady state. This parameter is guaranteed with the AC Output Test oad (Figure 1) by device characterization, but is not production tested.. 'X' in part number indicates power rating ( or ).. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is OW, twp must be greater or equal to Z + tdw to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tdw. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp. For the CE controlled write cycle, OE may be OW with no degradation to tcw timing. 4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VI) or (CMD = VIH when CE = VI).. Industrial temperature: for specific speeds, packages and powers contact your sales office tbl 1

12 Waveform of Read Cycles: Random Access Port (1,) trc ADDR taa toh CE () tac tcz tchz B, UB tbe tbhz tbz OE toz toe tohz I/OOUT Valid Data Out 99 drw 1 1. R/W is HIGH for read cycle.. Address valid prior to or coincident with CE traition OW; otherwise taa is the limiting parameter. Waveform of Read Cycles: Buffer Command Mode ADDR trc CMD (1) taa tac toh tcz tchz B, UB tbe tbhz OE tbz I/OOUT toz toe Valid Data Out tohz 99 drw 14 NOTE: 1. CE = VIH when CMD = VI. 1

13 Waveform of Write Cycle No.1 (R/W Controlled Timing) Random Access Port (1,6) ADDR twc taw R/W CE, B, UB (8) ta () () () twp twr I/OIN tdw Valid Data In OE tohz I/OOUT Z Data Out (4) (4) Data Out tac tbe tow 99 drw Waveform of Write Cycle No. (CE, B, and/or UB Controlled Timing) Random Access Port (1,6,7) ADDR twc taw CE, B, UB (8) () R/W ta twr tcw () () tbp () tdw I/OIN Valid Data 99 drw R/W, CE, or B and UB must be inactive during all address traitio.. A write occurs during the overlap of R/W = VI, CE = VI and B = VI and/or UB = VI.. twr is measured from the earlier of CE (and B and/or UB) or R/W going HIGH to the end of the write cycle. 4. During this period, I/O pi are in the output state and the input signals must not be applied.. If the CE OW traition occurs simultaneously with or after the R/W OW traition, the outputs remain in the High-impedance state. 6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is OW, twp must be greater or equal to Z + tdw to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tdw. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp. For the CE controlled write cycle, OE may be OW with no degregation to tcw timing. 7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. CMD access follows the standard CE access described above. If CMD = VI, then CE must = VIH or, when CE = VI, CMD must = VIH

14 equential Port: AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,) 784X 784X 784X 784X4 ymbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. READ CYCE tcyc equential Clock Cycle Time 4 tch Clock Pulse HIGH 1 18 tc Clock Pulse OW 1 18 Count Enab le and Address Pointer et-up Time 6 6 Count Enable and Address Pointer Hold Time toe Output Enable to Data Valid 8 toz Output Enable ow-z Time () tohz Output Enable High-Z Time () 9 11 tcd Clock to Valid Data 4 tckhz Clock High-Z Time () tckz Clock ow-z Time () teb Clock to EOB 1 18 Unit 99 tbl equential Port: AC Electrical Characteristics Over the Operating Temperature and upply Voltage (1,) ymbol Parameter 784X 784X 784X 784X4 Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCE tcyc equential Clock Cycle Time 4 tf Flow Restart Time 1 Chip elect and Read/Write et-up Time 6 6 Chip elect and Read/Write Hold Time td Input Data et-up Time 6 6 Input Data Hold Time 99 tbl 1. 'X' in part number indicates power rating ( or ).. Traition measured at mv from steady state. This parameter is guaranteed with the AC Output Test oad (Figure 1) by device characterization, but is not production tested.. Industrial temperature: for specific speeds, packages and powers contact your sales office. 14

15 equential Port: AC Electrical Characteristics Over the Operating Temperature and upply Voltage (1,) ymbol WRITE CYCE Parameter 784X 784X 784X 784X4 Min. Max. Min. Max. Min. Max. Min. Max. trpw Reset Pulse Width 1 twer Write Enable HIGH to Reset HIGH trrc Reset HIGH to Write Enable OW trfv Re set HIGH to Flag Valid Unit 1. 'X' in part numbers indicates power rating ( or ).. Industrial temperature: for specific speeds, packages and powers contact your sales office. 99 tbl 4 equential Port: Write, Pointer oad Non-Incrementing Read tcyc tch tc CK CNTEN () () D (1) I/OIN Dx td A HIGH IMPEDANCE R/W CE tcd tcz tckhz OE toe toz tohz I/OOUT D D D tckz 99 drw If D = VI, then address will be clocked in on the CK's rising edge.. If CNTEN = VIH for the CK's rising edge, the internal address counter will not advance.. Pointer is not incremented on cycle immediately following D even if CNTEN is OW. 6.4

16 equential Port: Write, Pointer oad, Burst Read CK CNTEN D I/OIN Dx tch tcyc tc td A (1) () HIGH IMPEDANCE td () D R/W CE td OE top I/OOUT tckz 1. If D = VI, then address will be clocked in on the CK's rising edge.. If CNTEN = VIH for the CK's rising edge, the internal address counter will not advance.. Pointer is not incremented on cycle immediately following D even if CNTEN is OW. toz D D1 tohz () 99 drw 18 Read TRT/EOB Flag Timing - equential Port CK tcyc tch tc CNTEN (4) () TRT1/ (1) I/OIN Dx HIGH IMPEDANCE td D R/W CE () OE I/OOUT EOB1/ toz toe () tcd tckz D 16 D1 teb D tohz () 99 drw19 (Also used in Figure "Read TRT/EOB Flag Timing") 1. If TRT1 or TRT = VI, then address will be clocked in on the CK's rising edge.. If CNTEN = VIH for the CK's rising edge, the internal address counter will not advance.. OE will control the output and should be HIGH on power-up. If CE = VI and is clocked in while R/W = VIH, the data addressed will be read out within that cycle. If CE = VI and is clocked in while R/W = VI, the data addressed will be written to if the last cycle was a read. OE may be used to control the bus contention and permit a write on this cycle. 4. Unlike D case, CNTEN is not disabled on cycle immediately following TRT.. If R/W = VI, data would be written to D again since CNTEN = VIH. 6. OE = VI makes no difference at this point since the R/W = VI disables the output until R/W = VIH is clocked in on the next rising clock edge.

17 Waveform of Write Cycles: equential Port CK tcyc tch tc (4) CNTEN () D (1) I/OIN Dx td A td D HIGH IMPEDANCE td D1 R/W (4) CE tcd tckhz OE () I/OOUT tckz D tohz HIGH IMPEDANCE 99 drw Waveform of Burst Write Cycles: equential Port CK tcyc tch tc CNTEN () () D (1) td td I/OIN Dx A D D1 D R/W () CE OE () tckz I/OOUT HIGH IMPEDANCE tcd D 1. If D = VI, then address will be clocked in on the CK's rising edge.. If CNTEN = VIH for the CK's rising edge, the internal address counter will not advance.. Pointer is not incrementing on cycle immediately following D even if CNTEN is OW. 4. If R/W = VI, data would be written to D again since CNTEN = VIH.. OE = VI makes no difference at this point since the R/W = VI disables the output until R/W = VIH is clocked in on the next rising clock edge. 99 drw

18 Waveform of Write Cycles: equential Port (TRT/EOB Flag Timing) CK tch tc CNTEN (4) () TRT1/ (1) I/OIN Dx D td D1 D D HIGH IMPEDANCE R/W () CE () OE (6) tckz I/OOUT HIGH IMPEDANCE tcd D EOB1/ teb 99 drw (Also used in Figure "Read TRT/EOB Flag Timing") 1. If TRT1 or TRT = VI, then address will be clocked in on the CK's rising edge.. If CNTEN = VIH for the CK's rising edge, the internal address counter will not advance.. OE will control the output and should be HIGH on power-up. If CE = VI and is clocked in while R/W = VIH, the data addressed will be read out within that cycle. If CE = VI and is clocked in while R/W = VI, the data addressed will be written to if the last cycle was a read. OE may be used to control the bus contention and permit a write on this cycle. 4. Unlike D case, CNTEN is not disabled on cycle immediately following TRT.. If R/W = VI, data would be written to D again since CNTEN = VIH. 6. OE = VI makes no difference at this point since the R/W = VI disables the output until R/W = VIH is clocked in on the next rising clock edge. 18

19 equential Counter Enable Cycle After Reset, Write Cycle (1,4,6) CK RT CNTEN () I/OIN D D1 D D D4 99 drw equential Counter Enable Cycle After Reset, Read Cycle (1,4) CK RT R/W () CNTEN () I/OOUT D () D1 D D 99 drw 4 1. 'D' represents data input for Address =, 'D1' represents data input for Address = 1, etc.. If CNTEN = VI then 'D1' would be written into 'A1' at this point.. Data output is available at a tcd after the R/W = VIH is clocked. The RT sets R/W = OW internally and therefore disables the output until the next clock. 4. CE = VI throughout all cycles.. If CNTEN=VI then 'D1' would be clocked out (read) at this point. 6. R/W = VI

20 Random Access Port - Reset Timing trpw RT trrc R/W,R/WCMD or (UB + B) (4) twer trfv EOB(1 or ) Flag Valid 99 drw Random Access Port Restart Timing of equential Port (1). x tcyc tf CK R/W () CR Block () (Internal ignal) 99 drw 6 1. The sequential port is in the TOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case ).. "" is written to Bit 4 from the random port at address [A - A] =, when CMD = VI and CE = VIH. The device is in the Buffer Command Mode (see Case ).. CR is an internal signal only and is shown for reference only. 4. equential port must also prohibit R/W or CE from being OW for twer and trrc periods or CK must not toggle from OW-to-HIGH until after trrc.

21 Ordering Information 784 Device Type X Power XX peed X Package X Process/ Temperature Range Blank I (1) B G PF Commercial ( C to +7 C) Industrial (-4 C to+8 C) ( C to +1 C) Compliant to MI-PRF-8 QM 84-pin PGA (G84-) 8-pin TQFP (PN8-1) 4 Commercial Only Commercial Only Commercial & Commercial & tandard Power ow Power peed in nanoseconds 784 NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For specific speeds, packages and powers contact your sales office. 64K (4K x 16) equential Access Random Access Memory 99 drw 7, Datasheet Document History /8/99: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Page Added additional notes to pin configuratio 6/4/99: Changed drawing format 11//99: Replaced IDT logo 4/18/: Page Added "Outputs" in equential pin description table Changed ±mv to mv in notes //: Page 4 Increased storage temperature parameter Clarified TA parameter Page DC Electrical parameters changed wording from "open" to "disabled" 1/9/9: Page 1 Removed "IDT" from orderable part number CORPORATE HEADQUARTER for AE: for Tech upport: 64 ilver Creek Valley Road or an Jose, CA 918 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc