128Mx72 bits PC133 SDRAM Registered DIMM with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K Refresh

Transcription

1 128Mx72 bits PC133 SDAM egistered DIMM with PLL, based on 64Mx4 SDAM with LVTTL, 4 banks & 8K efresh DSCIPTION The HYM72V12C736K4 Series are 128Mx72bits CC Synchronous DAM Modules. The modules are composed of thirty six 64Mx4bits CMOS Synchronous DAMs in 400mil 54pin TSOP-II stack package, one 2Kbit POM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one uF decoupling capacitors per each SDAM are mounted on the PCB. The HYM72V12C736K4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The HYM72V12C736K4 Series are fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FATUS PC133MHz support 168pin SDAM egistered DIMM Serial Presence Detect with POM 1.7 (43.18mm) Height PCB with double sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface Data mask function by SDAM internal banks : four banks Module bank : two physical banks Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4 or 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks ODING INFOMATION Part No. Clock Frequency Internal Bank ef. Power SDAM Package Plating HYM72V12C736K4-H HYM72V12C736LK4-H 133MHz 4 Banks 8K Normal L-Part TSOP-II Gold This document is a general product description and is subject to change without notice. Hyundai lectronics does not assume any responsibility for use of circuits described. No patent licenses are implied. ev. 1.1/Dec. 2002

2 PIN DSCIPTION PIN PIN NAM DSCIPTION CK0 CK0 Clock Inputs Clock nable The system clock input. All other inputs are registered to the SDAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDAM will be one of the states among power down, suspend or self refresh /S0 ~ /S3 Chip Select nables or disables all inputs except CK, CK and BA0, BA1 A0 ~ A12 /AS, /CAS, /W G SDAM Bank Address Address ow Address Strobe, Column Address Strobe, Write nable egister nable Selects bank to be activated during /AS activity Selects bank to be read/written during /CAS activity ow Address : A0 ~ A12, Column Address : CA0 ~ CA9, CA11 Auto-precharge flag : A10 /AS, /CAS and /W define the operation efer function truth table for details egister nable pin which permits the DIMM to operateion in Buffered Mode when G input is Low, in egistered Mode when G input is High 0 ~ 7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode ~ DQ63 Data Input/Output Multiplexed data input / output pin VCC Power Supply (3.3V) Power supply for internal circuits and input buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~2 SPD Address Input Serial Presence Detect Address Input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM ID1~3 Identification Detect Commend Interval, ead Precharge Timing, Power Detect NC No Connection No connection ev. 1.1/Dec

3 PIN ASSIGNMNTS FONT SID BACK SID FONT SID BACK SID PIN NO. NAM PIN NO. NAM PIN NO. NAM PIN NO. NAM 1 VSS 85 VSS 41 VCC 125 NC CK0 126 A VSS 127 VSS NC 128 CK /S2 129 /S3 6 VCC 90 VCC DQ DQ NC 132 NC 9 DQ VCC 133 VCC 10 DQ NC 134 NC Architecture Key 51 NC 135 NC 52 CB2 136 CB6 11 DQ8 95 DQ40 53 CB3 137 CB7 12 VSS 96 VSS 54 VSS 138 VSS 13 DQ9 97 DQ DQ DQ DQ DQ DQ DQ DQ DQ45 59 VCC 143 VCC 18 VCC 102 VCC DQ DQ46 61 NC 145 NC DQ47 62 NC 146 NC 21 CB0 105 CB4 63 NC 147 G 22 CB1 106 CB5 64 VSS 148 VSS 23 VSS 107 VSS DQ53 24 NC 108 NC DQ54 25 NC 109 NC DQ55 26 VCC 110 VCC 68 VCC 152 VCC 27 /W 111 /CAS DQ DQ DQ58 30 /S0 114 /S DQ59 31 NC 115 /AS 73 VCC 157 VCC 32 VSS 116 VSS DQ60 33 A0 117 A DQ61 34 A2 118 A DQ62 35 A4 119 A DQ63 36 A6 120 A7 78 VSS 162 VSS 37 A8 121 A9 79 CK2 163 *CK3 38 A10/AP 122 BA0 80 NC 164 NC 39 BA1 123 A11 81 WP 165 SA0 40 VCC 124 VCC 82 SDA 166 SA1 Voltage Key 83 SCL 167 SA2 84 VCC 168 VCC ev. 1.1/Dec

4 ev. 1.1/Dec BLOCK DIAGAM U0 U1 U2 U3 U4 DQ4 DQ5 DQ6 DQ7 DQ8 DQ S0 U18 U19 U20 U21 U22 S1 U9 U10 U11 U12 U DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U27 U28 U29 U30 U31 U5 U6 U7 U U23 U24 U25 U26 U14 U15 U16 U17 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U32 U33 U34 U35 VCC VSS Bypass Capacitor A0 A1 A2 SA2 Serial PD SDA SCL WP SA0 SA1 S0~S3 BA0,BA1 G I S T A0 ~ A11 AS CAS CK0 W S0~S3 G PLL CLK * When necessary two couples of the signals are created by double loading the register inputs. CK0 PLL +3.3 V 3.3 V DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 CK1,2,3 U0 U1 U2 U3 U4 DQ4 DQ5 DQ6 DQ7 DQ8 DQ S0 U18 U19 U20 U21 U22 S1 U9 U10 U11 U12 U DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U27 U28 U29 U30 U31 U5 U6 U7 U U23 U24 U25 U26 U14 U15 U16 U17 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U32 U33 U34 U35 VCC VSS Bypass Capacitor A0 A1 A2 SA2 Serial PD SDA SCL WP SA0 SA1 BA0,BA1 G I S T A0 ~ A11 AS CAS CK0 W G PLL CLK * When necessary two couples of the signals are created by double loading the register inputs. CK0 PLL +3.3 V 3.3 V DQ64 DQ6 5DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 CK1,2,3 S2 S3 U0 U1 U2 U3 U4 DQ4 DQ5 DQ6 DQ7 DQ8 DQ S0 U18 U19 U20 U21 U22 S1 U9 U10 U11 U12 U DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U27 U28 U29 U30 U31 U5 U6 U7 U U23 U24 U25 U26 U14 U15 U16 U17 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U32 U33 U34 U35 VCC VSS Bypass Capacitor A0 A1 A2 SA2 Serial PD SDA SCL WP SA0 SA1 S0~S3 BA0,BA1 G I S T A0 ~ A11 AS CAS CK0 W S0~S3 G PLL CLK * When necessary two couples of the signals are created by double loading the register inputs. CK0 PLL +3.3 V 3.3 V DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 CK1,2,3 U0 U1 U2 U3 U4 DQ4 DQ5 DQ6 DQ7 DQ8 DQ S0 U18 U19 U20 U21 U22 S1 U9 U10 U11 U12 U DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U27 U28 U29 U30 U31 U5 U6 U7 U U23 U24 U25 U26 U14 U15 U16 U17 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U32 U33 U34 U35 VCC VSS Bypass Capacitor A0 A1 A2 SA2 Serial PD SDA SCL WP SA0 SA1 BA0,BA1 G I S T A0 ~ A11 AS CAS CK0 W G PLL CLK * When necessary two couples of the signals are created by double loading the register inputs. CK0 PLL +3.3 V 3.3 V DQ64 DQ6 5DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 CK1,2,3 S2 S3

5 SIAL PSNC DTCT BYT NUMB DSCIPTION VALU -H -H BYT0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYT1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYT2 Fundamental Memory Type SDAM 04h BYT3 # of ow Addresses on This Assembly 13 0Dh 1 BYT4 # of Column Addresses on This Assembly 11 0Bh BYT5 # of Module Banks on This Assembly 2 Bank 02h BYT6 Data Width of This Assembly 72 Bits 48h BYT7 Data Width of This Assembly (Continued) - 00h BYT8 Voltage Interface Standard of This Assembly LVTTL 01h BYT9 SDAM Cycle Latency= h BYT10 Access Time from Latency= h BYT11 DIMM Configuration Type CC 02h BYT12 efresh ate/type us / Self efresh Supported 82h BYT13 Primary SDAM Width x4 04h BYT14 rror Checking SDAM Width x4 04h BYT15 Minimum Clock Delay Back to Back andom Column Address tccd = 1 CLK 01h BYT16 Burst Lenth Supported 1,2,4,8,Full Page 8Fh 2 BYT17 # of Banks on ach SDAM Device 4 Banks 04h BYT18 SDAM Device Attributes, /CAS Lataency /CAS Latency=3 04h BYT19 SDAM Device Attributes, / Lataency / Latency=0 01h BYT20 SDAM Device Attributes, /W Lataency /W Latency=0 01h BYT21 SDAM Module Attributes egistered/buffered inputs, with PLL 1Fh BYT22 SDAM Device Attributes, General +/- 10% voltage tolerence, Burst ead Single Bit Write, Precharge All, Auto 0h Precharge, arly AS Precharge BYT23 SDAM Cycle Latency=2-00h BYT24 Access Time from Latency=2-00h BYT25 SDAM Cycle Latency=1-00h BYT26 Access Time from Latency=1-00h BYT27 Minimum ow Precharge Time (tp) 20ns 14h BYT28 Minimum ow Active to ow Active Delay (td) 15ns 0Fh BYT29 Minimum /AS to /CAS Delay (tcd) 20ns 14h BYT30 Minimum /AS Pulse Width (tas) 45ns 2Dh BYT31 Module Bank Density 512MB 80h BYT32 Command and Address Signal Input Setup Time 1.5ns 15h BYT33 Command and Address Signal Input Hold Time 0.8ns 08h BYT34 Data Signal Input Setup Time 1.5ns 15h BYT35 Data Signal Input Hold Time 0.8ns 08h BYT36 ~61 Superset Information (may be used in future) - 00h BYT62 SPD evision Intel SPD 1.2B 12h 3, 8 BYT63 Checksum for Byte 0~62-39h BYT64 Manufacturer JDC ID Code Hynix JDD ID ADh BYT65 ~71...Manufacturer JDC ID Code Unused FFh NOT ev. 1.1/Dec

6 BYT NUMB DSCIPTION VALU -H -H NOT BYT72 Manufacturing Location Hynix (Korea Area) HSA (United States Area) HS (urope Area) HJ (Japan Area) ASIA Area 0*h 1*h 2*h 3*h 4*h 9

7 BYT NUMB DSCIPTION PC133 SDAM egistered DIMM Continued VALU NOT -H -H BYT73 Manufacturer s Part Number (Component) 7 (SDAM) 37h 4, 5 BYT74 Manufacturer s Part Number (256Mb based) 2 32h 4, 5 BYT75 Manufacturer s Part Number (Voltage Interface) V (3.3V, LVTTL) 56h 4, 5 BYT76 Manufacturer s Part Number (Memory Width) 1 31h 4, 5 BYT77...Manufacturer s Part Number (Memory Width) 2 32h 4, 5 BYT78 Manufacturer s Part Number (Module Type) C 43h 4, 5 BYT79 Manufacturer s Part Number (Data Width) 7 37h 4, 5 BYT80...Manufacturer s Part Number (Data Width) 3 33h 4, 5 BYT81 Manufacturer s Part Number (efresh, SDAM Bank) 6 (8K efresh, 4Banks) 36h 4, 5 BYT82 Manufacturer s Part Number (Package Type) K 4Bh 4, 5 BYT83 Manufacturer s Part Number (Component Configuration) 4 (x4 based) 34h 4, 5 BYT84 Manufacturer s Part Number (Hyphent) - (Hyphen) 2Dh 4, 5 BYT85 Manufacturer s Part Number (Min. Cycle Time) H 48h 4, 5 BYT86 ~90 Manufacturer s Part Number Blanks 20h 4, 5 BYT91 evision Code (for Component) Process Code - 4, 6 BYT92...evision Code (for PCB) Process Code - 4, 6 BYT93 Manufacturing Date Work Week - 3, 6 BYT94...Manufacturing Date Year - 3, 6 BYT95 ~98 BYT99 ~125 Assembly Serial Number Serial Number - 6 Manufacturer Specific Data (may be used in future) None 00h BYT126 System Frequency Support refer to note 7 64h 7, 8 BYT127 Intel Specification Details for 100MHz Support efer to Note7 85h 7, 8 BYT128 ~256 Unused Storage Locations - 00h 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for HYM in Byte 73~90 to use the limited 18 bytes from byte 73 to byte Not fixed but dependent 7. CK0 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. efer to Intel SPD Specification 1.2B 9. efer to Hynix web site Byte 82~ 86 for L-Part BYT NUMB DSCIPTION VALU -H -H NOT BYT82 Manufacturer s Part Number (Power) L 4Ch 4, 5 BYT83 Manufacturer s Part Number (Package Type) K 4Bh 4, 5 BYT84 Manufacturer s Part Number (Component Configuration) 4 (x4 based) 34h 4, 5 BYT85 Manufacturer s Part Number (Hyphent) - (Hyphen) 2Dh 4, 5 BYT86 Manufacturer s Part Number (Min. Cycle Time) H 48h 4, 5 ev. 1.1/Dec

8 ABSOLUT MAIMUM ATINGS Parameter Symbol ating Unit Ambient Temperature TA 0 ~ 70 C Storage Temperature TSTG -55 ~ 125 C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 ma Power Dissipation PD 1 W Soldering Temperature Time TSOLD C Sec Operation at above absolute maximum rating can adversely affect device reliability. DC OPATING CONDITION (TA=0 to 70 C) Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ V 1 Input High voltage VIH VDDQ V 1,2 Input Low voltage VIL V 1,3 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration. AC OPATING TST CONDITION (TA=0 to 70 C, VDD=3.3±0.3V, VSS=0V) Parameter Symbol Value Unit Note AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Input Timing Measurement eference Level Voltage Vtrip 1.4 V Input ise / Fall Time t / tf 1 ns Output Timing Measurement eference Level Voltage Voutref 1.4 V Output Load Capacitance for Access Time Measurement CL 50 pf 1 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit ev. 1.1/Dec

9 CAPACITANC (TA=25 C, f=1mhz) Parameter Pin Symbol Min -H Max Unit CK0 CI1-20 pf CK0 CI2-20 pf Input Capacitance /S0, /S1, /S2, /S3 CI3-20 pf A0~12, BA0, BA1 CI4-20 pf /AS, /CAS, /W CI5-20 pf 0~7 CI6-20 pf Data Input / Output Capacitance ~ DQ63 CI/O - 20 pf OUTPUT LOAD CICUIT Vtt=1.4V T=250 Ω Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit ev. 1.1/Dec

10 DC CHAACTISTI I (TA=0 to 70 C, VDD=3.3±0.3V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI ua 1 Output Leakage Current ILO -1 1 ua 2 Output High Voltage VOH V IOH = -4mA Output Low Voltage VOL V IOL = +4mA 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6 DC CHAACTISTI II Parameter Symbol Test Condition Speed -H Unit Note Operating Current IDD1 Burst length=1, One bank active tc tc(min), IOL=0mA 2760 ma 1 Precharge Standby Current in Power Down Mode IDD2P CK VIL(max), tck = min 420 IDD2PS CK VIL(max), tck = 76 ma Precharge Standby Current in Non Power Down Mode IDD2N IDD2NS CK VIH(min), VIH(min), tck = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CK VIH(min), tck = Input signals are stable ma Active Standby Current in Power Down Mode IDD3P CK VIL(max), tck = min 282 IDD3PS CK VIL(max), tck = 108 ma Active Standby Current in Non Power Down Mode IDD3N IDD3NS CK VIH(min), VIH(min), tck = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CK VIH(min), tck = Input signals are stable ma Burst Mode Operating Current IDD4 tck tck(min), IOL=0mA All banks active CL= ma 1 Auto efresh Current IDD5 tc tc(min), All banks active 4800 ma 2 Self efresh Current IDD6 CK 0.2V Normal 550 ma 3 L-part 156 ma 4 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tc (efresh AS cycle time) is shown at AC CHAACTISTI II 3. HYM72V12C736K4-H 4. HYM72V12C736LK4-H ev. 1.1/Dec

11 AC CHAACTISTI I (AC operating conditions unless otherwise noted) Parameter Symbol Min -H Max Unit Note System Clock Cycle Time CAS Latency = 3 tck ns 1 Clock High Pulse Width tchw ns 2 Clock Low Pulse Width tclw ns 2 Access Time From Clock CAS Latency = 3 tac3-5.4 ns 3 Data-Out Hold Time toh ns Data-Input Setup Time tds ns 2 Data-Input Hold Time tdh ns 2 Address Setup Time tas ns 2 Address Hold Time tah ns 2 CK Setup Time tcks ns 2 CK Hold Time tckh ns 2 Command Setup Time t ns 2 Command Hold Time tch ns 2 CLK to Data Output in Low-Z Time tolz 1 - ns CLK to Data Output in High-Z Time CAS Latency = 3 tohz ns 1. In egistered DIMM, data is delayed an additional clock cycle due to the register (this is, Device CL + 1 = DIMM CL) 2.Assume t / tf (input rise and fall time ) is 1ns, If t & tf > 1ns, then [(t+tf)/2-1]ns should be added to the parameter 3.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If t > 1ns, then (t/2-0.5)ns should be added to the parameter ev. 1.1/Dec

12 AC CHAACTISTI II Parameter Symbol Min -H Max Unit Note AS Cycle Time Operation tc 65 - ns Auto efresh tc 65 - ns AS to CAS Delay tcd 20 - ns AS Active Time tas K ns AS Precharge Time tp 20 - ns AS to AS Bank Active Delay td 15 - ns CAS to CAS Delay tccd 1 - CLK Write Command to Data-In Delay twtl 0 - CLK Data-In to Precharge Command tdpl 2 - CLK Data-In to Active Command tdal 5 - CLK to Data-Out Hi-Z tdqz 2 - CLK to Data-In Mask t 0 - CLK MS to New Command tmd 2 - CLK Precharge to Data Output Hi-Z CAS Latency = 3 tpoz3 4 - CLK Power Down xit Time tpd 1 - CLK Self efresh xit Time ts 1 - CLK 1 efresh Time tf - 64 ms 1. Timing delay due to the register is considered in a registered DIMM 2. A new command can be given tc after self refresh exit ev. 1.1/Dec

13 DVIC OPATING OPTION TABL HYM72V12C736(L)K4-H CAS Latency tcd tas tc tp tac toh 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns DIMM/CAS Latency = Device CL + 1 (egistered Mode) ev. 1.1/Dec

14 COMMAND TUTH TABL Command CKn-1 CKn AS CAS W ADD A10/ AP BA Note Mode egister Set H L L L L OP code No Operation H H L H H H Bank Active H L L H H A V ead ead with Autoprecharge H L H L H CA L H V Write Write with Autoprecharge H L H L L CA L H V Precharge All Banks H H L L H L Precharge selected Bank L V Burst Stop H L H H L H V Auto efresh H H L L L H Burst-ead-Single- WIT H L L L H ntry H L L L L H A9 Pin High (Other Pins OP code) Self efresh 1 xit L H H L H H H Precharge power down ntry H L xit L H H L H H H H L H H H Clock Suspend H ntry H L L V V V xit L H 1. xiting Self efresh occurs by asynchronously bringing CK from low to high 2. = Don t care, H = Logic High, L = Logic Low. BA =Bank Address, A = ow Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation ev. 1.1/Dec

15 PACKAG DMNSION 6.5 Max 1.27 ev. 1.1/Dec