Analog and Telecommunication Electronics

Transcription

1 Politecnico di Torino - ICT School Analog and Telecommunication Electronics F2 Active power devices»mos»bjt» IGBT, TRIAC» Safe Operating Area» Thermal analysis 23/05/ ATLCE - F DDC 2014 DDC 1

2 Lesson F2: active power devices Device structure, models, parameters MOS BJT Other devices: IGBT, SCR, TRIAC Operating limits Safe Operating Area Power dissipation Thermal analysis References: Any text on electronic devices and basic circuits 23/05/ ATLCE - F DDC 2014 DDC 2

3 Power BJT devices Fundamental relation: Ic= β Ib Most relevant parameters for power applications: Vcebr C-E breakdown voltage Icmax max collector current β current gain (lower with high currents) Vcesat C-E voltage drop in saturation I c Thermal parameters» Max power, Thermal resistance Use vertical technology More current in the same area (higher density) I b V be V ce 23/05/ ATLCE - F DDC 2014 DDC 3

4 Vertical power BJT structure Low doping in base region Wide depletion layer, high brk voltage Low current gain (5 20) High transit time Ft < 10 MHz B E n p 10^16 n 10^14 Primary breakdown Avalanche in the BC junction Secondary breakdown High current in small area (same problem as diodes)» Multiple small devices with current sharing Critical region is near saturation: High current, voltage drop high power dissipation Need to get deep saturation (problem: low β) n+ 10^19 C 23/05/ ATLCE - F DDC 2014 DDC 4

5 BJT models Ebers-Moll model for BJT Simplified models (active region) BE diode + Ic source Ic = β Ib Linear models» Hybrid»Gm» 23/05/ ATLCE - F DDC 2014 DDC 5

6 Switch or amplifier? Use as amplifier Active region Use as switch ON Saturation Use as switch OFF Cutoff 23/05/ ATLCE - F DDC 2014 DDC 6

7 BJT as a switch Operating points are on the load line 23/05/ ATLCE - F DDC 2014 DDC 7

8 BJT operation The current gain β decreases for high currents Need significant driving power Operation is based on minority carriers Slowdynamic behavior Temperature dependence To increase BVceo, base region long and lightly doped Higher ε Reduced E field Higher recombination probability Lower current gain High voltage devices have low current gain 23/05/ ATLCE - F DDC 2014 DDC 8

9 Saturation model for BJT V source Vcesat (0.1 V) Series resistor Rcesat (few ohms) Lower Vcesat with C-E inversion (lower β) 23/05/ ATLCE - F DDC 2014 DDC 9

10 Critical saturation parameters Low current gain (5 20) Critical region: Near saturation, high Ic, residual Vce High power dissipation Design solution Guarantee deep saturation (high Ib drive) Use Darlington (or similar) connections» Higher current gain (and Vbe!)» Single integrated structure» Npn-npn» Npn-pnp 23/05/ ATLCE - F DDC 2014 DDC 10

11 Cutoff model for BJT Ib = 0 Ic = 0 (ideal) BC junction leakage current: Icbo If base open, enters as Ib, causing Iceo = β Icbo Iceo causes power dissipation Temperature rise higher leakage current further temperature rise Thermal runaway Steer Icbo away from Base R to GND Reverse bias BE (without breakdown!) Avoid high current density areas (hot spot) Multiple devices, with current partition 23/05/ ATLCE - F DDC 2014 DDC 11

12 Power MOS-FET Planar structure Low power devices Current and breakdown voltage ratings function of the channel W & L. Curr. flow Vertical structure Voltage rating function of doping and thickness of N-epitaxial layer (vertical) Current rating is a function of the channel W & L A vertical structure can sustain both high V & I 23/05/ ATLCE - F DDC 2014 DDC 12

13 MOS-FET parasitics The vertical structure creates a pn junction from body (S) to substrate (D) S G D Current can always flow from S to D A 1-quadrant switch 4-quadrant requires at least two MOS 23/05/ ATLCE - F DDC 2014 DDC 13

14 MOS-FET parasitics The vertical structure creates also a parasitic BJT D G S 23/05/ ATLCE - F DDC 2014 DDC 14

15 MOS-FET parameters Basic parameters: Vdsbr D-S Breakdown voltage Idmax Max Drain current Vgsth Threshold voltage Rdson ON equivalent resistance Qg total charge injected into the Gate (for a given Vgs) Pd max power dissipation A power transistor may consist of several cells (thousands) Power MOS DMOS,. (double-diffused metal oxide semiconductor) Power MOSFETs are made using this technology 23/05/ ATLCE - F DDC 2014 DDC 15

16 MOS-FET model Model depends on operating point Low Vgs (subthreshold):» Exponential Medium Vgs:» Square law High Vgs:» linear Figure Typical i D v GS characteristic for a power MOSFET. 23/05/ ATLCE - F DDC 2014 DDC 16

17 MOS-FET output characteristic Warning! Saturation in MOS has a different meaning (called active region in BJT) 23/05/ ATLCE - F DDC 2014 DDC 17

18 MOS-FET switching models ON: Equivalent resistance Ron OFF: Leakage current Ioff Dynamic GS capacitance DS capacitance Parasitic towards substrate 23/05/ ATLCE - F DDC 2014 DDC 18

19 MOS-FET gate charge Before threshold (Vth): Id = 0 Charge Cgs Active region Id > 0 Voltage gain G to D Miller effect on Cgd capacitance multiply Saturation Charge Cgd Verify in lab experiment 23/05/ ATLCE - F DDC 2014 DDC 19

20 MOS-FET vs BJT MOS-FET use majority carriers High switching speed Reduced temperature dependence MOSFET use simpler driving circuit The Gate represents a plate of a capacitor (towards GND); no current after first charging step, but Fast switching circuits able to drive a high-capacitance load ON state BJT modeled as Vcesat (+Ron) MOS modeled as Ron OFF state: both modeled as current source (leakage) 23/05/ ATLCE - F DDC 2014 DDC 20

21 Four-layer devices Transistors have limitations in switching high currents at high voltages Other devices are specifically designed for such applications: four-layer devices Specific physical structure Can be used only as switches (not for linear amplifiers) A great deal in common with bipolar transistors SCR/Tyristor TRIAC/DIAC 23/05/ ATLCE - F DDC 2014 DDC 21

22 4-layer device operation Circuit with two interconnected BJTs Turning on T2 provides Ic2 as Ib1 to T1, and Ic1 as Ib2. Both devices conducts until the current goes to zero. The two BJTs can be built as a single 4-layer device Tyristor or Silicon Controlled Rectifier (SCR) 23/05/ ATLCE - F DDC 2014 DDC 22

23 SCR in CMOS logic circuits SCR structure intrinsic in CMOS ICs Responsible for latch up Triggered by Input levels out of GND-Vcc range High energy particles pmosfet nmosfet V G DD G S D D S V SS p+ p+ n+ n+ n+ p+ n-substrate T1 p-well T2 23/05/ ATLCE - F DDC 2014 DDC 23

24 The thyristor Four-layer device with a pnpn structure Three terminals: anode, cathode and gate Gate is the control input. Power flow between Anode and Cathode 23/05/ ATLCE - F DDC 2014 DDC 24

25 Thyristor in AC power control Triggered ON by a pulse on the Gate Stays ON as long as V > 0 (remainder of the half cycle) Returns OFF when V = 0 Varying firing time changes output power Single-wave allows control from 0 50% of full power 23/05/ ATLCE - F DDC 2014 DDC 25

26 The Triac and the Diac A bidirectional thyristor Allows full-wave control using a single device Often used with a diac: bidirectional trigger diode to produce the gate drive pulses The DIAC breaks down at a particular voltage and fires the triac 23/05/ ATLCE - F DDC 2014 DDC 26

27 A simple lamp-dimmer using a triac Current pulse to fire the Triac Phase shift network. Provides trigger voltage for Diac 23/05/ ATLCE - F DDC 2014 DDC 27

28 IGBT The Insulated Gate Bipolar Transistor or IGBT combines bipolar and MOS devices MOSFET gate-drive + high Ic and low Vcesat of BJT isolated gate FET for the control input, bipolar power transistor as a switch, in a single device combines high efficiency and fast switching. Used in medium- to high-power applications switching power supply, motor control, induction heating, Large IGBT modules (many devices in parallel), can handle» high current k 100 A» High voltages k 1000 V. 23/05/ ATLCE - F DDC 2014 DDC 28

29 IGBT structure 23/05/ ATLCE - F DDC 2014 DDC 29

30 IGBT characteristic 23/05/ ATLCE - F DDC 2014 DDC 30

31 Lesson F2: active power devices Device structure, models, parameters MOS BJT Operating regions Other devices: IGBT, SCR, TRIAC Operating limits Safe Operating Area Power dissipation Thermal model 23/05/ ATLCE - F DDC 2014 DDC 31

32 Operating limits (any device) Breakdown voltage If higher, insulating layers are broken Max current If higher, wires or conducting paths can melt Max power Power dissipation causes temperature rise (see max temp.) Max temperature Doping distribution is modified changes in parameters Silicon or metal can melt Special application parameters Radiation in space,. 23/05/ ATLCE - F DDC 2014 DDC 32

33 Safe Operating Area Any electronic devices can handle limited power, voltage, current For active devices, the region of acceptable V,I is the Safe Operating Area (SOA), defined by Powerlimit (V x I > Pdmax)» Excess power cause temperature rise, with melting» Secondary breakdown: local heating and thermal runaway Voltage (V < Vbrk)» Excess voltage causes breakdown and insulator perforation Current (I < Imax)» Excess current cause heating and metal evaporation 23/05/ ATLCE - F DDC 2014 DDC 33

34 Safe Operating Area boundaries (BJT) Too high current Too high V x I (power) - not uniform current flow - high local power dissipation Active & Safe Operating Area (SOA) Too high voltage 23/05/ ATLCE - F DDC 2014 DDC 34

35 SOA for BJT (TIP31) Includes dynamic behavior Pdmax depends on pulse Duty Cycle Log axis I x V = K (straight line) V CE = 5V Saturation not in this diagram 23/05/ ATLCE - F DDC 2014 DDC 35

36 SOA for MOS (IRF640) Dynamic behavior Log axis No secondary breakdown Id limited by Rds 23/05/ ATLCE - F DDC 2014 DDC 36

37 Power dissipation All electric devices dissipate a power Pd = V I Power dissipation increases temperature Any device has temperature limits, therefore power limits The effects of power dissipation can be modeled using thermal equivalent circuits Power current Temperature node voltage Heat conduction capability thermal resistance θr ( /W) Diode/MOS/BJT power dissipated on the junctions Heat must be brought outside, through a path including» Junction-case defined by manufacturer» Case-ambient controlled using heat sinks 23/05/ ATLCE - F DDC 2014 DDC 37

38 Power derating Manufacturers specify Max power dissipation Pdmax Max junction operating temperature Tjmax Power dissipation causes temperature rise Allowed power dissipation decreases with Ta Ta = Tjmax Pd = 0 23/05/ ATLCE - F DDC 2014 DDC 38

39 Evaluation of temperature rise Electric network model for thermal behaviour Thermal parameter electric model Power Pd current source Temperature T node voltage Heat conduction θ thermal resistance θr ( /W) Electric equivalent circuit Tj Ta = Pd θja 23/05/ ATLCE - F DDC 2014 DDC 39

40 From junction to ambient The thermal path from junctin to ambient consists of: Junction-Case: θ JC» Thermal resistance defined by the package Case-heatsink: θ CS» Case and fixture Heatsink-ambient: θ SA» Heatsink and operating condition (air flow) Designer can control θ CS and θ SA, and select θ JC 23/05/ ATLCE - F DDC 2014 DDC 40

41 Thermal specification Power devices specified for No heatsink, Ta specified, Tc? infinite heatsink, Tc = Ta Example datasheet TIP31 23/05/ ATLCE - F DDC 2014 DDC 41

42 Power BJT datasheet (TIP31) 23/05/ ATLCE - F DDC 2014 DDC 42

43 Power MOS datasheet IRF640 23/05/ ATLCE - F DDC 2014 DDC 43

44 Heatsink datasheet example 23/05/ ATLCE - F DDC 2014 DDC 44

45 Dynamic thermal response 23/05/ ATLCE - F DDC 2014 DDC 45

46 Lesson F2: summary Describe the structure of BJT and MOS power transistors. Plot output V(I) characteristic of a MOS or BJT power device, and identify the different operating regions. What is secondary breakdown? Draw a model for power BJT. Describe differences between low and high power MOS-FETs. Which parameters defines the boundary of SOA? How can we evaluate the actual temperature of a power semiconductor junction? Define the infinite heatsink concept. 23/05/ ATLCE - F DDC 2014 DDC 46