Analog and Telecommunication Electronics

Transcription

1 Politecnico di Torino - ICT School Analog and Telecommunication Electronics C1 - PLL linear analysis» PLL basics» Application examples» Linear analysis» Phase error 26/03/ ATLCE - C DDC 2014 DDC 1

2 Lesson C1: PLL linear analysis PLL basics How the PLL works, application examples Block diagram of the PLL PLL linear model PLL transfer function Parameters and transfer function Loop filter (RC, RRC, active, charge pump) Loop gain Phase error, transient and steady state References: D. Del Corso: Elettronica per Telecomunicazioni: 3.1, 3.2 S. Franco: Design with OA and Analog IC: /03/ ATLCE - C DDC 2014 DDC 2

3 Phase Lock Loops PLL working principle (lesson B1) Block diagram, phase error, parameters, capture/lock range PLL circuits (lesson B2) Analysis of PLLs (lesson B3 and B4) Applications (lessons B5, B6, B7) AM, FM, FSK, PSK demodulators Integer and fractional synthesizer, DDS data recovery and clock synchronization Lab 1: VCO, digital applications Lab 2: tone decoder, analog applications 26/03/ ATLCE - C DDC 2014 DDC 3

4 PLL: where? Several PLLs are used in a radio system (cell phone) A: local oscillator for TX frequency translation B: local oscillator for RX frequency translation C: I/Q reference signal for RX D: I/Q reference signals for TX E: clock multipliers and data synchronizer 26/03/ ATLCE - C DDC 2014 DDC 4

5 PLLs in the TX-RX system Frequency synthesizers Generate reference signals Synchronizers and clock multipliers. 26/03/ ATLCE - C DDC 2014 DDC 5

6 A real equipment B C D E A 26/03/ ATLCE - C DDC 2014 DDC 6

7 Inside a P-RX All local oscillator signals generated from a unique reference by a PLL synthesizer 26/03/ ATLCE - C DDC 2014 DDC 7

8 PLL applications Generate signals (phase) locked to a reference AM and FM coherent demodulators TV synchronization Frequency synthesizers Resynchronization Clock/Data recovery and separation (CDR) Bandpass filter with tunable parameters Center frequency Bandwidth and Q 26/03/ ATLCE - C DDC 2014 DDC 8

9 Phase synchronization examples Angular frequency ω is the derivative of phase θ. Same frequency constant phase difference θe All oscillators exhibit tolerance and drift example 1 Separate oscillators cannot provide the same frequency example 2 PLL: generate a signal locked to a reference Constant θe same frequency 26/03/ ATLCE - C DDC 2014 DDC 9

10 Phase Lock Loop block diagram Vi: input signal Vi(t) = Vi sin(ω i t+ θ i ) PD: Phase Demodulator V I PD V D F: loop filter VCO: Voltage Controlled Oscillator V O VCO F V C Vo: output signal (from VCO) Vo(t) = Vo cos(ω o t+ θ o ) 26/03/ ATLCE - C DDC 2014 DDC 10

11 PLL parameters θe = θi -θo Vd = F(θe) Linear model: Vd = Kd θe PD gain: Kd Vc = Vd F(s) DC filter gain: F(0) Passive: linear, active: limited range ω = G(Vc) Linear model: ω o = Ko Vc VCO gain: Ko If Vc = Vco ω o = ω or (not always Vco = 0) Loop gain : DC loop gain: Kd Ko F(s) Kd Ko F(0) 26/03/ ATLCE - C DDC 2014 DDC 11

12 Linearity: where? Any real circuit has a limited linearity range The above relations assume linearity in: Phase detector: Vd = Kd θe Some PD have intrinsic nonlinear transfer function VCO gain: ω = Ko Vc Most VCO have nonlinear ω(vc) Loop filter: F(s) Passive; saturation if active 26/03/ ATLCE - C DDC 2014 DDC 12

13 Lesson B1: PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state 26/03/ ATLCE - C DDC 2014 DDC 13

14 PLL transfer function - 1 A PLL handles phases Angular frequency ω = derivative of phase θ Using L-transform 26/03/ ATLCE - C DDC 2014 DDC 14

15 PLL transfer function - 2 Phase detector: Loop filter: VCO: Overall fdt: 26/03/ ATLCE - C DDC 2014 DDC 15

16 PLL transfer function - 3 Loop equation PLL transfer function: = 26/03/ ATLCE - C DDC 2014 DDC 16

17 Lock behavior The PLL senses and handles the phase The lock condition means ω o = ω i Starting state: ω o = ω i» With constant input frequency the phase difference, and therefore Vd do not change As ω i, changes, also θe and Vd are modified» The changes in Vd, filtered through F(s), shift the VCO» As long as ω o ω i, θe and Vd change continuously The only steady state condition is ω o =ω i (constant θe) This is the lock keeping mechanism 26/03/ ATLCE - C DDC 2014 DDC 17

18 Phase error The phase error is defined as: θ e = θ i - θ o θ o = θ i H(s); θ e = θ i - θ o = θ i (1 - H(s)) Same denominator as H(s) Same parameters for time & frequency responses: for II-order damping e resonant frequency n 26/03/ ATLCE - C DDC 2014 DDC 18

19 PLL math & parameters summary v i = V i sin (ω i t+ θ i ); v o = V o cos (ω o t+ θ o ) H(s) = θ o (s)/θ i (s) θ e = θ i θ o = θ i (1 - H(s)) Vd = Kd θe Vc = Vd F(s) ω or = ω o for Vc = Vco ω = Ko Vc Loop gain DC loop gain PD gain: Kd DC filter gain: F(0) VCO gain: Ko G L (s) = Kd Ko F(s) G L (0) = Kd Ko F(0) 26/03/ ATLCE - C DDC 2014 DDC 19

20 Choices for the loop filter F(s) Direct wire RC cell (lowpass) R-R-C cell V I PD V D II order cell Finite-gain amplifier F Infinite-gain amplifier V O VCO V C Charge pump circuits 26/03/ ATLCE - C DDC 2014 DDC 20

21 Direct wire F(s) = 1 Vc = Vd F(s) order 0; PLL H(s) order 1 Only a first example, no real application! 26/03/ ATLCE - C DDC 2014 DDC 21

22 H(s) order 1 frequency response H(s) = 1, o = i H(s) < 1, o i 26/03/ ATLCE - C DDC 2014 DDC 22

23 RC cell filter F(s) order 1 H(s) order 2 Widely used simple filter 26/03/ ATLCE - C DDC 2014 DDC 23

24 H(s) in a PLL with RC filter Response depends on ω n,, H(0) parameters Three parameters Two degrees of freedom: Ko*Kd, R*C Not possible to get independent ω n,, H(0) 26/03/ ATLCE - C DDC 2014 DDC 24

25 R-RC filter F(s) order 1 H(s) order 2 Three degrees of freedom Independent control of ω n,, H(0) Most used filter 26/03/ ATLCE - C DDC 2014 DDC 25

26 Filter with gain Needs active element Example: Op.Amp. amplifier Frequency response F(s) order 1 H(s) order 2, with 2 parameters (R2/R1, R2*C) 26/03/ ATLCE - C DDC 2014 DDC 26

27 PLL order PLL order H(s) order H(s) order = F(s) order + 1 H(s) order 1 H(s) order 2 All cases parameter ω o parameters ω o and DC gain (F(0)) 26/03/ ATLCE - C DDC 2014 DDC 27

28 Infinite gain In steady state Vc = Vd F(0) To change ωo, Vc and θe - must change The ratio between phase error θe and control signal Vc depends from Kd and F(0) Infinite gain (F(0) ), Vc 0 even for Vd = 0. For an infinite-gain locked PLL, the phase error e = 0 Two ways to get infinite gain High gain amplifier Charge pump 26/03/ ATLCE - C DDC 2014 DDC 28

29 Infinite gain with amplifier Active integrator, based on Op Amp DC gain = open loop Op Amp gain 26/03/ ATLCE - C DDC 2014 DDC 29

30 Charge pump circuit A closes on Vi edge, opens on Vo edge B closes on Vo edge, opens on Vi edge Capacitor C charged or discharged through A or B Similar circuit with 3-S output and RC cell A,B Vc steady if Phase error = 0 (edges occur at the same time) V C Infinite gain (equivalent!) 26/03/ ATLCE - C DDC 2014 DDC 30

31 Infinite gain with charge pump Ideal integrator built with C + SW 2 SW or 3-S output Similar behavior as open loop Op. Amp. Can be seen as a chopped Op Amp No need for amplifier Used with CMOS circuit needs high input impedance VCO Limited range (0 V DD, or bipolar) 26/03/ ATLCE - C DDC 2014 DDC 31

32 Lesson B1: PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state 26/03/ ATLCE - C DDC 2014 DDC 32

33 Steady state phase error Defined as Computed as Depends on: Input signal i DC loop gain: Ko Kd F(0) Steady state phase error θ er 26/03/ ATLCE - C DDC 2014 DDC 33

34 Phase error analysis Phase error depends from Signals Loop tytpe and parameters Signal: Phase step Frequency step, phase ramp Frequency ramp, parabolic phase Loop parameters loop filter F(s) Finite DC gain Infinite DC gain 26/03/ ATLCE - C DDC 2014 DDC 34

35 Input signal: phase step ω O θ O No need to change the VCO frequency Steady state error with finite loop gain: Always 0 Steady state error with infinite loop gain: Always 0 Signals in: PSK, phase modulations 26/03/ ATLCE - C DDC 2014 DDC 35

36 Input signal: linear phase ramp ω O The VCO frequency must be modified Steady state error with finite loop gain: Constant Steady state error with infinite loop gain: Always 0 FSK, doppler with fixed relative speed 26/03/ ATLCE - C DDC 2014 DDC 36

37 Input signal: quadratic phase ramp ω O The VCO frequency must be modified Steady state error with finite loop gain: Unbounded Steady state error with infinite loop gain: Constant Doppler with fixed acceleration 26/03/ ATLCE - C DDC 2014 DDC 37

38 Summary for steady state phase error Input signal 26/03/ ATLCE - C DDC 2014 DDC 38

39 Lesson B1 tests Mention some applications of PLLs. Draw the block diagram of a PLL. How are defined the parameters Kd, Ko, F(0)? Define the PLL transfer function H(s). Which is the relation between F(s) and H(s)? List the approximations of the PLL linear model. How to compute the steady state phase error? Evaluate θer value for linear phase ramp input to a PLL using phase detectors with finite/infinite gain Kd 26/03/ ATLCE - C DDC 2014 DDC 39