PowerPC 405CR Embedded Processor Data Sheet

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1 Features IBM PowerPC bit RISC processor core operating up to 266MHz - Memory Management Unit - 6KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers Synchronous DRAM (SDRAM) interface operating up to 33MHz - 32-bit interface for non-ecc applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 6-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 0 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering Two serial ports (6550 compatible UART) One IIC interface General Purpose I/O (GPIO) available Supports JTAG for board level testing Internal Processor Local Bus (PLB) runs at SDRAM interface frequency Description The IBM PowerPC 405CR (PPC405CR) is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while providing a base for custom chip designs. The controller is powered by a PPC405 embedded core. This core tightly couples a 266 MHz CPU, MMU, instruction and data caches, and debug logic. Fine-tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and improves performance. The PPC405CR employs the IBM CoreConnect bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 33-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB). High-performance peripherals attach to the PLB and less performancecritical peripherals attach to the OPB. Technology: IBM CMOS SA-2E 0.25 µm (0.8 µm L eff ) Package: 27mm, 36-ball enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 0.9W, Maximum 2.0W at 200MHz. 6/8/03

2 Contents PowerPC 405CR Embedded Processor Data Sheet Ordering, PVR, and JTAG Information Address Map Support SDRAM Memory Controller External Peripheral Bus Controller (EBC) DMA Controller UART IIC Bus Interface General Purpose IO (GPIO) Controller Universal Interrupt Controller (UIC) JTAG Pin Lists Signal Descriptions Spread Spectrum Clocking Strapping Figures PPC405CR Embedded Controller Functional Block Diagram mm, 36-Ball E-PBGA Package Timing Waveform V-Tolerant I/O Input Current Input Setup and Hold Waveform Output Delay and Float Timing Waveform /8/03

3 Tables System Memory Address Map DCR Address Map Signals Listed Alphabetically Signals Listed by Ball Assignment Pin Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended DC Operating Conditions Input Capacitance DC Electrical Characteristics Clocking Specifications Peripheral Interface Clock Timings I/O Specifications All speeds I/O Specifications 33 and 200MHz I/O Specifications 266MHz Strapping Pin Assignments /8/03 3

4 Ordering, PVR, and JTAG Information PowerPC 405CR Embedded Processor Data Sheet Product Name Order Part Number Processor Frequency Package Rev Level PVR Value JTAG ID PPC405CR IBM25PPC405CR-3BC33C 33MHz 27mm, 36 E-PBGA C 0x x PPC405CR IBM25PPC405CR-3BC33CZ 33MHz 27mm, 36 E-PBGA C 0x x PPC405CR IBM25PPC405CR-3BC200C 200MHz 27mm, 36 E-PBGA C 0x x PPC405CR IBM25PPC405CR-3BC200CZ 200MHz 27mm, 36 E-PBGA C 0x x PPC405CR IBM25PPC405CR-3BC266C 266MHz 27mm, 36 E-PBGA C 0x x PPC405CR IBM25PPC405CR-3BC266CZ 266MHz 27mm, 36 E-PBGA C 0x x Note : Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local IBM sales office. Each part number contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PPC405CR Embedded Processor User s Manual for details on the register content. IBM Part Number Key IBM Part Number Grade 3 Reliability Package (E-PBGA) IBM25PPC405CR-3BC200Cx Shipping Package Blank = Tray Z = Tape and reel Operational Case Temperature Range (-40 C to +85 C) Processor Speed 33MHz 200MHz 266MHz Revision Level 4 6/8/03

5 PPC405CR Embedded Controller Functional Block Diagram Universal Interrupt Controller Clock Control Reset Power Mgmt Timers DCRs MMU PPC405 Processor Core DCR Bus GPIO IIC UART UART 8KB D-Cache JTAG DCU Trace ICU 6KB I-Cache Arb On-chip Peripheral Bus (OPB) DMA Controller (4-Channel) OPB Bridge Arb Processor Local Bus (PLB) Code Decompression (CodePack ) SDRAM Controller External Bus Controller External Bus Master Controller 3-bit addr 32-bit data 32-bit addr 32-bit data The PPC405CR is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture. 6/8/03 5

6 Address Map Support PowerPC 405CR Embedded Processor Data Sheet The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr and mfdcr instructions. System Memory Address Map 4GB System Memory Function Subfunction Start Address End Address Size SDRAM and External Peripherals 0x xEF5FFFFF 3830MB General Use Note: Any of the address ranges listed at right may be use for any of the above 0xF xFFFFFFFF 256MB functions. Boot-up Peripheral Bus Boot 0xFFE xFFFFFFFF 2MB UART0 0xEF xEF B UART 0xEF xEF B Internal Peripherals IIC0 0xEF xEF6005F 32B OPB Arbiter 0xEF xEF60063F 64B GPIO Controller Registers 0xEF xEF60077F 28B Notes:. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory region for other uses. 3. All address ranges not listed above are reserved. DCR Address Map 4KB Device Configuration Register Function Start Address End Address Size Total DCR Address Space 0x000 0x3FF KW (4KB) Reserved 0x000 0x00F 6W Memory Controller Registers 0x00 0x0 2W External Bus Controller Registers 0x02 0x03 2W Decompression Controller Registers 0x04 0x05 2W Reserved 0x06 0x07F 06W PLB Registers 0x080 0x08F 6W Reserved 0x090 0x09F 6W OPB Bridge Out Registers 0x0A0 0x0A7 8W Reserved 0x0A8 0x0AF 8W Clock, Control, and Reset 0x0B0 0x0B7 8W Power Management 0x0B8 0x0BF 8W Interrupt Controller 0x0C0 0x0CF 6W Reserved 0x0D0 0x0FF 48W DMA Controller Registers 0x00 0x3F 64W Reserved 0x40 0x3FF 704W Notes:. DCR address space is addressable with up to 0 bits (024 or K unique addresses). Each unique address represents a single 32-bit (word) register, or kiloword (KW) (which equals 4 KB). 6 6/8/03

7 SDRAM Memory Controller The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB per bank are supported, up to a maximum of GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: x8 to 3x addressing for SDRAM (2- and 4-bank) 32-bit memory interface support Programmable address compare for each bank of memory Industry standard 68-pin DIMMS are supported (some configurations) 4MB to 256MB per bank Programmable address mapping and timing Auto refresh Page mode accesses with up to 4 open pages Power Management (self-refresh) Error Checking and Correction (ECC) support - Standard SEC/DED coverage - Aligned nibble error detect - Address error logging External Peripheral Bus Controller (EBC) Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O Up to 66MHz operation Burst and non-burst devices 8-, 6-, 32-bit byte-addressable data bus width support Programmable 2K clock time-out counter with disable for Ready Programmable access timing per device wait states for non-burst devices burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS Programmable address mapping Peripheral device pacing with external Ready External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-ebc PLB slaves - External master can control EBC slaves for own access and control 6/8/03 7

8 DMA Controller Supports the following transfers: PowerPC 405CR Embedded Processor Data Sheet - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers Four channels Scatter/Gather capability for programming multiple DMA operations 8-, 6-, 32-bit peripheral support (OPB and external) 32-bit addressing Address increment or decrement Internal 32-byte data buffering capability Supports internal and external peripherals Support for memory mapped peripherals Support for peripherals running on slower frequency buses UART One 8-pin UART and one 4-pin UART interface provided Selectable internal or external serial clock to allow wide range of baud rates Register compatibility with NS6550 register set Complete status reporting capability Transmitter and receiver are each buffered with 6-byte FIFOs when in FIFO mode Fully programmable serial-interface characteristics Supports DMA using internal DMA engine IIC Bus Interface Compliant with Phillips Semiconductors I 2 C Specification, dated 995 Operation at 00kHz or 400kHz 8-bit data 0- or 7-bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed V DD IIC interface Two independent 4 x byte data buffers Twelve memory-mapped, fully programmable configuration registers One programmable interrupt request signal Provides full management of all IIC bus protocol Programmable error recovery 8 6/8/03

9 General Purpose IO (GPIO) Controller Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects. - All seven external interrupts. - All nine instruction trace pins. Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero or open circuit). Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: Supports 7 external and 0 internal interrupts Edge triggered or level-sensitive Positive or negative active Non-critical or critical interrupt to PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector for faster vector processing JTAG IEEE 49. test access port IBM RISCWatch debugger support JTAG Boundary Scan Description Language (BSDL) 6/8/03 9

10 27mm, 36-Ball E-PBGA Package PowerPC 405CR Embedded Processor Data Sheet Top View Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded Gold Gate Release Corresponds to A Ball Location 5.0 TYP 27.0 REF 7.5 TYP 27.0 Note: All dimensions are in mm. C 0.20 C Bottom View A 0.25 C 0.35 C 27.0 Y W V U T R P N M L K J H G F E D C B A Thermal Balls.27 TYP PCB Substrate Mold Compound B ± MAX 0.75 ± 0.5 SOLDERBALL x M C A B 0.5 M C 0 6/8/03

11 Pin Lists In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. The page number listed gives the page in Signal Functional Description on page 23 where the signals in the indicated interface group begin. Signals Listed Alphabetically (Part of 7) Signal Name Ball Interface Group Page AV DD E20 Power 28 BA0 BA BankSel0 BankSel BankSel2 BankSel3 J7 H8 L9 N7 P7 U9 SDRAM 23 SDRAM 23 BusReq P2 External Master Peripheral 25 CAS K7 SDRAM 23 ClkEn0 ClkEn DMAAck0 DMAAck DMAAck2 DMAAck3 DMAReq0 DMAReq DMAReq2 DMAReq3 DQM0 DQM DQM2 DQM3 J9 G20 C6 B7 B6 A4 A9 C5 B5 A8 U8 W4 Y0 U8 SDRAM 23 External Slave Peripheral 23 External Slave Peripheral 23 SDRAM 23 DQMCB V9 SDRAM 23 DrvrInh DrvrInh2 ECC0 ECC ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOT0/TC0 EOT/TC EOT2/TC2 EOT3/TC3 F7 C9 V7 Y8 U4 V3 Y3 V2 W V G4 F2 W Y2 System 27 SDRAM 23 External Slave Peripheral 23 6/8/03

12 Signals Listed Alphabetically (Part 2 of 7) ExtAck ExtReq ExtReset GND Signal Name Ball Interface Group Page U5 Y3 P4 A A6 A0 A5 A20 B2 B9 C3 C8 D4 D7 E5 E0 E E6 F F20 J9 J0 J J2 K5 K9 K0 K K2 K6 K20 L L5 L9 L0 L L2 L6 M9 M0 M M2 R R20 External Master Peripheral 25 Power Note: J9 J2, K9 K2, L9 L2, and M9 M2 are also thermal balls /8/03

13 Signals Listed Alphabetically (Part 3 of 7) GND (cont) GPIO[TSE] GPIO2[TS2E] GPIO3[TSO] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] T5 T0 T T6 U4 U7 V3 V8 W2 W9 Y Y6 Y Y5 Y20 B8 D6 C7 P8 T7 W8 Y9 W3 V6 Power 28 System 27 Halt E9 System 27 HoldAck HoldPri HoldReq T4 T3 V2 External Master Peripheral 25 IICSCL U5 Internal Peripheral 25 IICSDA W7 Internal Peripheral 25 IRQ0[GPIO7] IRQ[GPIO8] IRQ2[GPIO9] IRQ3[GPIO20] IRQ4[GPIO2] IRQ5[GPIO22] IRQ6[GPIO23] MemAddr0 MemAddr MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr0 MemAddr MemAddr2 Signal Name Ball Interface Group Page D8 C20 E8 D20 G7 F8 W20 Y7 W7 V8 U7 Y4 U6 W4 V5 W3 V4 U3 V T2 Interrupts 26 SDRAM Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this bus. 23 6/8/03 3

14 Signals Listed Alphabetically (Part 4 of 7) MemClkOut0 MemClkOut MemData0 MemData MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData0 MemData MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData20 MemData2 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData3 OV DD PowerPC 405CR Embedded Processor Data Sheet Signal Name Ball Interface Group Page H20 G8 J8 K9 L20 M20 M9 L8 L7 N20 N9 M8 M7 P20 P9 N8 U20 T8 W6 Y7 Y6 V4 Y4 U2 W2 Y2 Y9 W9 V0 U0 Y8 W8 V9 U9 F5 G5 P5 R5 T6 T7 T4 T5 F6 G6 P6 R6 E6 E7 E4 E5 SDRAM 23 SDRAM Note: MemData0 is the most significant bit (msb) on this bus. 23 Power /8/03

15 Signals Listed Alphabetically (Part 5 of 7) PerAddr0 PerAddr PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr0 PerAddr PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr20 PerAddr2 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr3 A3 A4 B6 D7 C6 B7 D8 C7 B8 A7 D9 C8 B9 D0 C9 A9 B A B2 D A3 B3 C2 D2 B4 C3 D3 A6 C4 D4 A7 D5 External Slave Peripheral Note: PerAddr0 is the most significant bit (msb) on this bus. PerBLast E2 External Slave Peripheral 23 PerClk D3 External Master Peripheral 25 PerCS0 PerCS[GPIO0] PerCS2[GPIO] PerCS3[GPIO2] PerCS4[GPIO3] PerCS5[GPIO4] PerCS6[GPIO5] PerCS7[GPIO6] Signal Name Ball Interface Group Page D6 B5 C5 A5 B0 C0 A2 C External Slave Peripheral /8/03 5

16 Signals Listed Alphabetically (Part 6 of 7) PerData0 PerData PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData0 PerData PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData20 PerData2 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData3 PowerPC 405CR Embedded Processor Data Sheet U2 R4 U R2 R3 T N4 P3 N2 P M4 N3 M2 N L4 M3 L2 M K2 L3 K J J2 K3 K4 H H2 J3 J4 G G2 H3 External Slave Peripheral Note: PerData0 is the most significant bit (msb) on this bus. PerErr B External Master Peripheral 25 PerOE E4 External Slave Peripheral 23 PerPar0 PerPar PerPar2 PerPar3 C2 G3 E H4 External Slave Peripheral 23 PerReady E3 External Slave Peripheral 23 PerR/W C External Slave Peripheral 23 PerWBE0 PerWBE PerWBE2 PerWBE3 Signal Name Ball Interface Group Page D2 F4 F3 D External Slave Peripheral 23 PerWE C4 External Slave Peripheral 23 RAS K8 SDRAM 23 RcvrInh E7 System /8/03

17 Signals Listed Alphabetically (Part 7 of 7) Reserved SysClk SysErr SysReset TCK TDI TDO J20 G9 R7 T20 V6 H7 A8 D9 B4 A2 D5 Other pins Notes:. Connect G9 to ground. 2. Other reserved pins are not connected internally within the chip and should not have signals, voltage, or ground applied to them. System 27 JTAG 26 TestEn F9 System 27 TmrClk B20 System 27 TMS B3 JTAG 26 TRST H9 JTAG 26 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART_DSR[UART_CTS] UART_RTS[UART_DTR] UART_Rx UART_Tx W0 R8 U6 U3 V5 V20 T9 W5 V7 W6 W5 Y5 Internal Peripheral 25 Internal Peripheral 25 UARTSerClk R9 Internal Peripheral 25 V DD Signal Name Ball Interface Group Page E8 E9 E2 E3 H5 H6 J5 J6 M5 M6 N5 N6 T8 T9 T2 T3 Power 28 WE U SDRAM /8/03 7

18 Signals Listed by Ball Assignment (Part of 3) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A GND B0 PerCS4[GPIO3] C9 DrvrInh2 E8 V DD A2 TDI B PerAddr6 C20 IRQ[GPIO8] E9 V DD A3 PerAddr0 B2 PerAddr8 D PerWBE3 E0 GND A4 PerAddr B3 PerAddr2 D2 PerWBE0 E GND A5 PerCS3[GPIO2] B4 PerAddr24 D3 PerClk E2 V DD A6 Gnd B5 DMAReq2 D4 GND E3 V DD A7 PerAddr9 B6 DMAAck2 D5 TDO E4 OV DD A8 DMAReq3 B7 DMAAck D6 PerCS0 E5 OV DD A9 PerAddr5 B8 GPIO[TSE] D7 PerAddr3 E6 GND A0 GND B9 GND D8 PerAddr6 E7 Rcrvinh A PerAddr7 B20 TmrClk D9 PerAddr0 E8 IRQ2[GPIO9] A2 PerCS6[GPIO5] C PerR/W D0 PerAddr3 E9 Halt A3 PerAddr20 C2 PerPar0 D PerAddr9 E20 AV DD A4 DMAAck3 C3 GND D2 PerAddr23 F GND A5 GND C4 PerWE D3 PerAdd26 F2 EOT/TC A6 PerAddr27 C5 PerCS2[GPIO] D4 PerAddr29 F3 PerWBE2 A7 PerAddr30 C6 PerAddr4 D5 PerAddr3 F4 PerWBE A8 SysErr C7 PerAddr7 D6 GPIO2[TS2E] F5 OV DD A9 DMAReq0 C8 PerAddr D7 GND F6 OV DD A20 GND C9 PerAddr4 D8 IRQ0[GPIO7] F7 DrvrInh B PerErr C0 PerCS5[GPIO4] D9 SysReset F8 IRQ5[GPIO22] B2 GND C PerCS7[GPIO6] D20 IRQ3[GPIO20] F9 TestEn B3 TMS C2 PerAddr22 E PerPar2 F20 GND B4 TCK C3 PerAddr25 E2 PerBLast G PerData29 B5 PerCS[GPIO0] C4 PerAddr28 E3 PerReady G2 PerData30 B6 PerAddr2 C5 DMAReq E4 PerOE G3 PerPar B7 PerAddr5 C6 DMAAck0 E5 GND G4 EOT0/TC0 B8 PerAddr8 C7 GPIO3[TSO] E6 OV DD G5 OV DD B9 PerAddr2 C8 GND E7 OV DD G6 OV DD 8 6/8/03

19 Signals Listed by Ball Assignment (Part 2 of 3) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name G7 IRQ4[GPIO2] K2 PerData8 M3 PerData5 P8 GPIO4[TS2O] G8 MemClkOut K3 PerData23 M4 PerData0 P9 MemData2 G9 Reserved K4 PerData24 M5 V DD P20 MemData G20 ClkEn K5 GND M9 Thermal Ball R GND H PerData25 K9 Thermal Ball M0 Thermal Ball R2 PerData3 H2 PerData26 K0 Thermal Ball M Thermal Ball R3 PerData4 H3 PerData3 K Thermal Ball M2 Thermal Ball R4 PerData H4 PerPar3 K2 Thermal Ball M6 V DD R5 OV DD H5 V DD K6 GND M7 MemData0 R6 OV DD H6 V DD K7 CAS M8 MemData9 R7 Reserved H7 SysClk K8 RAS M9 MemData4 R8 UART0_DCD H8 BA K9 MemData M20 MemData3 R9 UARTSerClk H9 TRST K20 GND N PerData3 R20 GND H20 MemClkOut0 L GND N2 PerData8 T PerData5 J PerData2 L2 PerData6 N3 PerData T2 MemAddr2 J2 PerData22 L3 PerData9 N4 PerData6 T3 HoldPri J3 PerData27 L4 PerData4 N5 V DD T4 HoldAck J4 PerData28 L5 GND N6 V DD T5 GND J5 V DD L9 Thermal Ball N7 BankSel T6 OV DD J9 Thermal Ball L0 Thermal Ball N8 MemData3 T7 OV DD J0 Thermal Ball L Thermal Ball N9 MemData8 T8 V DD J Thermal Ball L2 Thermal Ball N20 MemData7 T9 V DD J2 Thermal Ball L6 GND P PerData9 T0 GND J6 V DD L7 MemData6 P2 BusReq T GND J7 BA0 L8 MemData5 P3 PerData7 T2 V DD J8 MemData0 L9 BankSel0 P4 ExtReset T3 V DD J9 ClkEn0 L20 MemData2 P5 OV DD T4 OV DD J20 Reserved M PerData7 P6 OV DD T5 OV DD K PerData20 M2 PerData2 P7 BankSel2 T6 GND 6/8/03 9

20 Signals Listed by Ball Assignment (Part 3 of 3) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name T7 GPIO5[TS3] U8 DQM0 V9 DQMCB W20 IRQ6[GPIO23] T8 MemData5 U9 BankSel3 V20 UART0_RTS Y GND T9 UART0_RX U20 MemData4 W EOT2/TC2 Y2 EOT3/TC3 T20 Reserved V MemAddr W2 GND Y3 ExtReq U PerData2 V2 HoldReq W3 MemAddr8 Y4 MemAddr4 U2 PerData0 V3 GND W4 MemAddr6 Y5 UART_TX U3 MemAddr0 V4 MemAddr9 W5 UART_RX Y6 GND U4 GND V5 MemAddr7 W6 UART_RTS [UART_DTR] Y7 MemAddr0 U5 ExtAck V6 GPIO9[TrcClk] W7 MemAddr Y8 MemData28 U6 MemAddr5 V7 UART_DSR [UART_CTS] W8 MemData29 Y9 MemData24 U7 MemAddr3 V8 MemAddr2 W9 MemData25 Y0 DQM2 U8 DQM3 V9 MemData30 W0 UART0_CTS Y GND U9 MemData3 V0 MemData26 W ECC6 Y2 MemData23 U0 MemData27 V ECC7 W2 MemData22 Y3 ECC4 U WE V2 ECC5 W3 GPIO8[TS6] Y4 MemData20 U2 MemData2 V3 ECC3 W4 DQM Y5 GND U3 UART0_DTR V4 MemData9 W5 UART0_TX Y6 MemData8 U4 ECC2 V5 UART0_RI W6 MemData6 Y7 MemData7 U5 IICSCL V6 Reserved W7 IICSDA Y8 ECC U6 UART0_DSR V7 ECC0 W8 GPIO6[TS4] Y9 GPIO7[TS5] U7 GND V8 GND W9 GND Y20 GND 20 6/8/03

21 Signal Descriptions The PPC405CR embedded controller is packaged in a 36-ball enhanced plastic ball grid array (E-PBGA). The following table provides a summary of the number of package pins associated with each functional interface group. Multiplexed Pins In the table Signal Functional Description on page 23, each I/O signal is listed along with a short description of the signal function. Some signals are multiplexed onto the same package pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, GPIO[TSE]). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address pins are used as outputs by the PPC405CR to broadcast an address to external slave devices when the PPC405CR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405CR. Intialization Strapping Pin Summary Group No. of Pins SDRAM 7 External Peripheral 97 External Master 9 Internal Peripheral 5 Interrupts 7 JTAG 5 System 8 Total Signal Pins 222 AV DD OV DD 6 V DD 6 Gnd 40 Thermal (and Gnd) 6 Reserved 5 Total Pins 36 One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see Strapping on page 40). Note that these are not multiplexed pins since the function of the pins is not programmable. 6/8/03 2

22 Pull-Up and Pull-Down Resistors PowerPC 405CR Embedded Processor Data Sheet Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3kΩ to +3.3V (0kΩ to +5V can be used on 5V tolerant I/Os) and pull-down value of kω to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405CR. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405CR requires only the pull-up and pull-down terminations as specified in the Signal Functional Description on page 23, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and SDRAM buses should be configured and terminated as follows: Peripheral interface PerAddr0:3, PerData0:3, and all of the control signals are driven by default. Terminate PerReady high and PerError low. SDRAM Program SDRAM0_CFG[EMDULR]= and SDRAM0_CFG[DCE]=. This causes the PPC405CR to actively drive all of the SDRAM address, data, and control signals. External Bus Control Signals All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405CR Embedded Processor User s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405CR. Please refer to Signals Listed Alphabetically on page for the pin number to which each signal is assigned. 22 6/8/03

23 Signal Functional Description (Part of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes SDRAM Interface MemData0:3 MemAddr2:0 Memory Data bus. Notes:. MemData0 is the most significant bit (msb). 2. MemData3 is the least significant bit (lsb). Memory Address bus. Notes:. MemAddr2 is the most significant bit (msb). 2. MemAddr0 is the least significant bit (lsb). I/O O BA0: Bank Address supporting up to four internal banks. O RAS Row Address Strobe. O CAS Column Address Strobe. O DQM0:3 DQM for byte lanes 0 (MemData0:7), (MemData8:5), 2 (MemData6:23), and 3 (MemData24:3). O DQMCB DQM for ECC check bits. O ECC0:7 ECC check bits 0:7. I/O BankSel0:3 Select up to four external SDRAM banks. O WE Write Enable. O ClkEn0: SDRAM Clock Enable. O MemClkOut0: External Slave Peripheral Interface PerData0:3 PerAddr0:3 Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer. Peripheral data bus used by PPC405CR when not in external master mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405CR when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. PerPar0:3 Peripheral byte parity signals. I/O O I/O I/O 6/8/03 23

24 Signal Functional Description (Part 2 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes PerWBE0:3 As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either peripheral controller or the DMA controller depending upon the type of transfer involved. Used as inputs when external bus master owns the external interface. I/O, 7 PerWE Peripheral write enable. Active when any of the four PerWBE0:3 signals are active. PerCS0 Peripheral chip select bank 0. O PerCS:7[GPIO0:6] PerOE PerR/W Seven additional peripheral chip selects or General Purpose I/O. To access this function, software must toggle a DCR register bit. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC405CR is the bus master, it enables the selected device to drive the bus. Used by the PPC405CR when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. PerReady Used by a peripheral slave to indicate it is ready to transfer data. I PerBLast DMAReq0:3 DMAAck0:3 Used by the PPC405CR when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405CR to indicate that data transfers have occurred. EOT0:3/TC0:3 End Of Transfer/Terminal Count. I/O O O[I/O] O I/O I/O I O 7, 7 7, /8/03

25 Signal Functional Description (Part 3 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes External Master Peripheral Interface PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Internal Peripheral Interface UARTSerClk Peripheral clock to be used by an external master and by synchronous peripheral slaves. Peripheral reset to be used by an external master and by synchronous peripheral slaves. Hold Request, used by an external master to request ownership of the peripheral bus. Hold Acknowledge, used by the PPC405CR to transfer ownership of peripheral bus to an external master. ExtReq is used by an external master to indicate it is prepared to transfer data. ExtAck is used by the PPC405CR to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external master tenure. Used when the PPC405CR needs to regain control of the peripheral interface from an external master. Used as an input to indicate that an external slave peripheral error has occurred. Serial clock. Used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0_Rx UART0 Receive (serial data in). I UART0_Tx UART0 Transmit (serial data out). O UART0_DCD UART0 Data Carrier Detect. I UART0_DSR UART0 Data Set Ready. I UART0_CTS UART0 Clear To Send. I UART0_DTR UART0 Data Terminal Ready. O UART0_RTS UART0 Request To Send. O UART0_RI UART0 Ring Indicator. I O O I O I O I O I I, 5 6 6, /8/03 25

26 Signal Functional Description (Part 4 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes UART_Rx UART Receive (serial data in). I UART_Tx UART Transmit (serial data out). O UART_DSR/ [UART_CTS] UART_RTS/ [UART_DTR] UART Data Set Ready or UART Clear To Send. To access this function, software must toggle a DCR register bit. UART Request To Send or UART Data Terminal Ready. To access this function, software must toggle a DCR register bit. IICSCL IIC serial clock. I/O IICSDA IIC serial data. I/O Interrupts Interface IRQ0:6[GPIO7:23] JTAG Interface Interrupt requests or General Purpose I/O. To access this function, software must toggle a DCR register bit. TDI Test data in. I TMS JTAG test mode select. I TDO Test data out. O TCK TRST JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405CR. I O I[I/O] I I 6 6, 2, 2, 4, 4, /8/03

27 Signal Functional Description (Part 5 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes System Interface SysClk Main system clock input. I SysReset Main system reset. External logic can drive this bidirectional pin low (minimum of 6 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states, 0 or open circuit). SysErr Set to when a Machine Check is generated. O Halt Halt from external debugger. I GPIO[TSE] GPIO2[TS2E] GPIO3[TSO] GPIO4[TS2O] GPIO5:8[TS3:6] GPIO9[TrcClk] General Purpose I/O or Even Trace execution status. To access this function, software must toggle a DCR register bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR register bit. General Purpose I/O Trace status. To access this function, software must toggle a DCR register bit. General Purpose I/O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR register bit. TestEn Test Enable. I RcvrInh DrvrInh:2 TmrClk Receiver Inhibit. Used only for manufacturing tests. Pull up for normal operation. Driver Inhibit and 2. Used only for manufacturing tests. Pull up for normal operation. An external clock input than can be used as an alternative to SysClk to run the CPU core. Which clock input is used is determined by software settings. I/O I/O[O] I/O[O] I/O[O] I/O[O] I I I 2.5V CMOS w/pull-down, 2, 2, 6, /8/03 27

28 Power GND AV DD PowerPC 405CR Embedded Processor Data Sheet Signal Functional Description (Part 6 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes:. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 22 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See External Bus Control Signals on page 22. Signal Name Description I/O Type Notes Ground Note: Pins J9 J2, K9 K2, L9 L2, and M9 M2 are also thermal balls. Filtered voltage input for PLL (analog) circuits OV DD V DD Other pins Reserved Output driver voltage 3.3V Logic voltage 2.5V Connect G9 to GND. Do not connect signals, voltage, or ground to any other reserved pins. 28 6/8/03

29 Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device Characteristic Symbol Value Unit Supply Voltage (Internal Logic) V DD 0 to +2.7 V Supply Voltage (I/O Interface) OV DD 0 to +3.6 V PLL Supply Voltage AV DD 0 to +2.7 V Input Voltage (2.5V CMOS receivers) V IN -0.6 to V DD +0.6 V Input Voltage ( receivers) V IN -0.6 to OV DD +0.6 V Input Voltage (5.0V LVTTL receivers) V IN -0.6 to OV DD +2.4 V Storage Temperature Range T STG -55 to +50 C Case temperature under bias T C -40 to +20 C Note: All specified voltages are with respect to GND. Package Thermal Specifications The PPC405CR is designed to operate within a case temperature range of -40 C to +85 C. Thermal resistance values for the E-PBGA package in a convection environment are as follows: Thermal Resistance Symbol Airflow ft/min (m/sec) Unit 0 (0) 00 (0.5) 200 (.02) Junction-to-case θ JC C/W Case-to-ambient θ CA C/W Notes:. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, T C, is measured at top center of case surface with device soldered to circuit board. b. T A = T C P θ CA, where T A is ambient temperature and P is power consumption. c. T CMax = T JMax P θ JC, where T JMax is maximum junction temperature and P is power consumption. 6/8/03 29

30 Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Symbol Minimum Typical Maximum Unit Notes Logic Supply Voltage V DD V I/O Supply Voltage OV DD V PLL Supply Voltage AV DD V Input Logic High (2.5V CMOS receivers) Input Logic High ( receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low (2.5V CMOS receivers) Input Logic Low (3.3/5.0V LVTTL receivers) V IH +.7 V DD V V IH +2.0 OV DD V V IH V V IL V V IL V Output Logic High V OH +2.4 OV DD V Output Logic Low V OL V 3.3V I/O Input Current (no pull-up or pull-down) I IL ±0 µa Input Current (with internal pull-down) I IL2 ±0 (@ 0V) +400 (@ V DD ) µa 5V Tolerant I/O Input Current I IL4 ±0-650 µa Input Max Allowable Overshoot (2.5V CMOS receivers) Input Max Allowable Overshoot ( receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) V IMAO25 V DD V V IMAO3 OV DD V V IMAO V Input Max Allowable Undershoot V IMAU -0.6 V Output Max Allowable Overshoot V OMAO OV DD V Output Max Allowable Undershoot V OMAU3-0.6 V Case Temperature T C C Notes:. See 5V-Tolerant I/O Input Current on page /8/03

31 5V-Tolerant I/O Input Current Input Current (µa) Input Voltage (V) Input Capacitance Parameter Symbol Maximum Unit Notes I/O C IN 5.4 pf LVTTL I/O C IN2 4.4 pf RX only pins C IN4 3.4 pf 6/8/03 3

32 DC Electrical Characteristics Parameter Symbol Minimum Typical Maximum Unit Active Operating Current (V DD ) 33MHz I DD TBD TBD ma Active Operating Current (OV DD ) 33MHz I ODD TBD TBD ma Active Operating Current (V DD ) 200MHz I DD ma Active Operating Current (OV DD ) 200MHz I ODD ma Active Operating Current (V DD ) 266MHz I DD TBD TBD ma Active Operating Current (OV DD ) 266MHz I ODD TBD TBD ma PLL V DD Input current I PLL 6 23 ma Note:. Maximum power is characterized at V DD = 2.7V, OV DD = 3.6V, T C = 85 C, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. The specification at 200MHz corresponds to CPU = 200 MHz, PLB = 00MHz, OPB = EBC = 50MHz. The 266MHz maximum power was measured with CPU = 266.6MHz, PLB =33.3MHz, OPB = EBC = 66.6MHz. 2. AV DD should be derived from V DD using the following circuit: V DD Test Conditions L + C C2 C3 GND AV DD AGND Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table Recommended DC Operating Conditions. AC specifications are characterized at OV DD = 3V and T J = +85 C with the 50pF test load shown in the figure at right. L 2.2µH SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM3A700S) C 3.3 µf SMT tantalum C2 0.µF SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 0.0µF SMT monolithic ceramic capacitor with X7R dielectric or equivalent Output Pin 50pF 32 6/8/03

33 Clocking Specifications Symbol Parameter Min Max Units CPU PF C Processor clock frequency 33.33/200/ MHz PT C Processor clock period 7.5/5/3.75 ns SysClk Input SCF C Clock input frequency MHz SCT C Clock period 5 40 ns SCT CS Clock edge stability (phase jitter, cycle to cycle) ± 0.5 ns SCT CH Clock input high time 40% of nominal period 60% of nominal period ns SCT CL Clock input low time 40% of nominal period 60% of nominal period ns Note: Input slew rate > 2V/ns MemClkOut Output MCOF C Clock output PF C = 33MHz MHz MCOT C Clock PF C = 33MHz 5 ns MCOF C Clock output PF C = 200MHz 00 MHz MCOT C Clock PF C = 200MHz 0 ns MCOF C Clock output PF C = 266MHz MHz MCOT C Clock PF C = 266MHz 7.5 ns MCOT CS Clock edge stability (phase jitter, cycle to cycle) ± 0.2 ns MCOT CH Clock output high time 45% of nominal period 55% of nominal period ns MCOT CL Clock output low time 45% of nominal period 55% of nominal period ns Other Clocks VCOF C VCO frequency MHz PLBF C PLB PF C = 33MHz MHz PLBF C PLB PF C = 200MHz 00 MHz PLBF C PLB PF C = 266MHz MHz OPBF C OPB PF C = 33MHz MHz OPBF C OPB PF C = 200MHz 50 MHz OPBF C OPB PF C = 266MHz MHz Timing Waveform 2.0V.5V 0.8V T CH T CL TC 6/8/03 33

34 Spread Spectrum Clocking PowerPC 405CR Embedded Processor Data Sheet Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405CR the following conditions must be met: The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. The maximum frequency deviation cannot exceed 3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note ). Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. Use the SDRAM MemClkOut since it also tracks the modulation. Notes:. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately.5% on baud rate before framing errors begin to occur. The.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation. 2. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the above requirements and does not adversely affect other aspects of the system. 34 6/8/03

35 Peripheral Interface Clock Timings Parameter Min Max Units PerClk output frequency 33MHz MHz PerClk period 33MHz 30 ns PerClk output frequency 200MHz 50 MHz PerClk period 200MHz 20 ns PerClk output frequency 266MHz MHz PerClk period 266MHz 5 ns PerClk output high time 45% of nominal period 55% of nominal period ns PerClk output low time 45% of nominal period 55% of nominal period ns PerClk clock edge stability (phase jitter, cycle to cycle) ± 0.3 ns UARTSerClk input frequency (Note ) 000/(2T OPB +2ns) MHz UARTSerClk period 2T OPB +2 ns UARTSerClk input high time T OPB + ns UARTSerClk input low time T OPB + ns TmrClk input frequency 33MHz MHz TmrClk period 33MHz 30 ns TmrClk input frequency 200MHz 50 MHz TmrClk period 200MHz 20 ns TmrClk input frequency 266MHz MHz TmrClk period 266MHz 5 ns TmrClk input high time 40% of nominal period 60% of nominal period ns TmrClk input low time 40% of nominal period 60% of nominal period ns Notes:. T OPB is the period in ns of the OPB clock. The internal OPB clock runs at /2 the frequency of the PLB clock. The maximum OPB clock frequency is 50MHz for 200MHz parts and 66.66MHz.for 266MHz parts. 6/8/03 35

36 Input Setup and Hold Waveform PowerPC 405CR Embedded Processor Data Sheet Clock T IS min TIH min Inputs Valid Output Delay and Float Timing Waveform Clock T OV max T OV max T OV max Outputs T OH min T OH min T OH min High (Drive) Float (High-Z) Low (Drive) Valid Valid 36 6/8/03

37 Notes:. In all of the following I/O Specifications tables a timing value of na means not applicable and dc means don t care. 2. See Test Conditions on page 32 for output capacitive loading. 3. I/O H is specified at 2.4V; I/O L is specified at 0.4V I/O Specifications All speeds Signal Setup Time (T IS min) Internal Peripheral Interface Input (ns) Output (ns) Output Current (ma) Hold Time (T IH min) Valid Delay (T OV max) Hold Time (T OH min) IICSCL n/a n/a n/a n/a 9 2 IICSDA n/a n/a n/a n/a 9 2 UART0_CTS n/a n/a 2 8 UART0_DCD n/a n/a 2 8 UART0_DSR n/a n/a 2 8 UART0_DTR 2 8 UART0_RI n/a n/a 2 8 UART0_RTS n/a n/a 2 8 UART0_Rx n/a n/a 2 8 UART0_Tx n/a n/a 2 8 UART_RTS [UART_DTR] n/a n/a 2 8 UART_DSR [UART_CTS] n/a n/a n/a n/a UART_Rx n/a n/a n/a n/a UART_Tx n/a n/a 2 8 UARTSerClk n/a n/a n/a n/a Interrupts Interface IRQ0:6[GPIO7:23] 2 8 JTAG Interface TCK n/a n/a async TDI n/a n/a async TDO 2 8 async TMS n/a n/a async TRST n/a n/a async System Interface DrvrInh:2 dc dc n/a n/a n/a n/a GPIO[TSE] GPIO2[TS2E] GPIO3[TSO] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] 2 8 Halt dc dc n/a n/a n/a n/a async RcvrInh dc dc n/a n/a n/a n/a SysClk n/a n/a n/a n/a SysErr n/a n/a 2 8 async SysReset async TestEn dc dc n/a n/a n/a n/a async TmrClk dc dc n/a n/a n/a n/a async I/O H (min) I/O L (min) Clock Notes 6/8/03 37