ECE 4510/5530 Microcontroller Applications Chapter 7

Transcription

1 ECE 450/5530 Microcontroller Applications Chapter 7 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Chapter 7: Parallel Ports I/O Addressing Modes Input data from switches Output data to LEDs Data transfer ECE 450 2

3 Overview of HCS2 Parallel Ports HCS2 device may have from 48 to 44 pins arranged in 3 to 2 I/O ports and packaged in a quad flat pack (QFP) or low profile quad flat pack (LQFP). A QFP or Quad Flat Package is an integrated circuit package with leads extending from each of the four sides. It is used for surface mounting (SMD) only, socketing or hole mounting is not possible. There are versions having from 32 to over 200 pins with a pitch ranging from 0.4 to.0 mm. Special cases include LQFP (Low profile QFP) and TQFP (Thin QFP). ECE 450 3

4 Basic Concepts of I/O I/O devices are also called peripheral devices. For microcontrollers, they are usually part of the IC For microprocessors, they are usually separate ICs I/O devices are consist of circuitry (logic or a device) that exchange data with a computer processing unit (CPU). Examples data includes: switches, light-emitting diodes, cathoderay tube screens, printers, modems, keyboards, and disk drives. ECE 450

5 Interface (Peripheral) Logic/IC ( of 2) Logic/IC whose function is to synchronize data transfer between the CPU and I/O devices Consists of control registers, status registers, data direction latches, and control circuitry Has pins that are connected to the CPU and I/O port pins that are connected to the I/O devices Each interface chip has a chip enable signal input or inputs, when asserted, allow the interface chip to react to the data transfer request. Data transfer between an I/O device and the CPU can be proceeded bitby-bit or in multiple bits (parallel). For embedded devices, this is the peripheral register address! ECE 450

6 Interface (Peripheral) Chip (2 of 2) Address decoder makes sure that each time one and only one peripheral device responds to the CPU s I/O request. Address Decoder from input device I/O pins to output device CE CE Interface chip Interface chip Microprocessor Data Bus ECE 450 Figure 7. Interface chip, I/O devices, and microprocessor

7 Adapt9S2DP52 I/O Pins ECE 450 7

8 DP52CPU Pins and Peripherals (No internal Busses Shown) ECE 450 8

9 HCS2 Parallel Ports The number of pins available in each I/O port for HCS2 are (see mc9s2dp52.s and mc9s2dp52.h for names): PORTA 8 pins PA7 PA0 PORTB 8 pins PB7 PB0 PORTE 8 pins PE7 PE0 PTH 8 pins PH7 PH0 PTJ 4 pins PJ7, PJ6, PJ, PJ0 PORTK 7 pins PK7, PK5 PK0 PTM 8 pins PM7 PM0 PTP 8 pins PP7 PP0 PTS 8 pins PS7 PS0 PTT 8 pins PT7 PT0 PORTAD, PORTAD0 6 pins PAD5 PAD0 ECE 450 9

10 HCS2 Parallel Ports ( of 3) All I/O pins serve multiple functions. When a peripheral function is enabled, its associated pins cannot be used as general purpose I/O pins. Each I/O port has several registers to support its operation. Registers related to I/O ports have been assigned a mnemonic name and the user can use these names to refer to them (see mc9s2dp52.s and mc9s2dp52.h): movb #$FF, PortA ; output $FF to Port A ECE 450

11 HCS2 Parallel Ports (2 of 3) All I/O ports (except PORTAD0 and PORTAD) have an associated data direction register and a data register. The name of the data direction register is formed by adding the letters DDR as the prefix to the port name. For example, DDRA, DDRB, and DDRT. To configure a pin for output, write a to the associated bit in the data direction register. To configure a pin for input, write a 0 to the associated bit in the data direction register. movb #$FF,DDRA movb #0,DDRA bset DDRA,$8 ; configure port A for output ; configure port A for input ; configure Port A pin 7 and 0 for output ECE 450

12 HCS2 Parallel Ports (3 of 3) We use PORT as the prefix to the port name for ports A, B, E, and K. For the other ports, the register name is formed by adding letters PT as the prefix to the port name. For example, PTH, PTJ, PTM, PTP, PTS, and PTT. Output a value to a port is done by storing that value to the port data register. movb #$FF,DDRH movb #$37,PTH ; configure Port H for output ; output the hex value 37 to port H Input a value from an input port is done by loading from the port data register. movb #0,DDRH ; configure Port H for input ldaa PTH ; read data from port H into A ECE 450 2

13 References to Parallel Ports Better way is to use the = directive (in assembly language) to equate a symbolic name to the address of a given register This allows to use the symbolic name to access it Ex: PORTA = $0000 PTH = $0260 PORTB = $000 DDRH = $0262 DDRA = $0002 PTT = $0240 DDRB = $0003 DDRT = $0242 LDAA #$FF ; Configure Port A for output STAA DDRA LDAA #$FF ; Write to Port A STAA PORTA ECE 450 3

14 Port B Code Example Example writing to port B:.area prog(abs) PORTB = $000 DDRB = $0003.text _main:: Ldaa #$FF Staa DDRB ; configures PB7 PB0 as output pins Ldaa #$A5 Staa PORTB ; write data $A5 on the PORTB ECE 450 4

15 ICC2 Parallel Ports Names The naming of the port data registers is not uniform The names of some of the port data registers are formed by adding PORT as the prefix of the port name or by adding the prefix PT only Port Name Data register Name A PORTA B PORTB E PORTE K PORTK H PTH J PTJ M PTM P PTP S PTS T PTT ECE 450 5

16 Basic Concepts of I/O () The speed and electrical characteristics of I/O devices may be very different from those of CPU These different characteristics makes it difficult to connect them directly to the CPU Interface chips may be used to resolve the differences between the microprocessor and I/O devices A major function of the interface circuitry is to synchronize data transfer between the CPU and I/O devices Interface circuits (on or off CPU) consists of control registers, data registers, status registers, data direction registers and control circuitry ECE 450 6

17 Basic Concepts of I/O (2) Interface devices have data pins that are connected to the microprocessor data bus and I/O port pins that are connected to the I/O devices Only one device is allowed to drive data to the data bus at a time Otherwise, data bus contention can result and the system may be damaged Address Decoder Insures that one and only one device is allowed to drive data to the data bus or accept data from the data bus at a time A Chip Enable or CE is driven by the address decoder to enable a peripheral device (typically active low) Additional address bits may be used for internal I/O register selection ECE 450 7

18 Basic Concepts of I/O (3) Control Registers Allows to set up parameters for the desired I/O operations Data direction registers Allows to select the data transfer direction for each I/O pin Status Registers Reports the progress and status of the I/O operation Data Registers Holds the data to be sent to the output device or the new data placed by the input device ECE 450 8

19 Basic Concepts of I/O (4) Interface devices is allowed to respond to the data transfer request from the microprocessor only when its chip enable (CE) is enabled In most devices the chip enable (CE) signal is active low by nature Otherwise the interface chip is electrically isolated from the data bus Data transfer between the I/O device and the interface devices can proceed bit-by-bit (serial) or in multiple bits (parallel) Data are transferred serially in low-speed devices such as modems and low-speed printers Parallel data transfer is mainly used by high-speed I/O devices ECE 450 9

20 Parallel I/O and the HC2 Memory-mapped I/O scheme (HC2) The microprocessor uses the same instruction set to perform memory accesses and I/O operations. The I/O devices and memory components are resident in the same memory space. A mechanism should be available to make sure: Data is valid when the microprocessor reads data To make sure output device is ready to accept data when the microprocessor outputs data For the HC2 parallel ports, this does not exist! Brute-Force Synchronization (is OK if timing of data not important) : The HC2 parallel ports have no inherent synchronization For input-- The microprocessor reads the interface chip and the interface chip returns the voltage levels on the input port pins to the microprocessor. For output --The interface chip places the data that it received from the microprocessor directly on the output port pins. ECE

21 HC2 Parallel I/O Synchronization Handshake Method: Interlocked handshake Use two I/O pins from another port, one input, one output: Write I/O First output level to assert data First input level to show when data has been read Output return to remove data Input return to complete cycle Read I/O First output level to request data First input level to show when data is available Output return to acknowledge read of data Input return to remove data ECE 450 2

22 Input/Read Handshaking Step. Step 2. Step 3. The HC2 output pin asserts H to indicate its intention to input data. The input device puts data on the data port pins and also asserts the handshake signal H2. The HC2 output pin reads the data and de-asserts H. After some delay, the input device also deasserts H2. H Data Valid Data H2 ECE 450 (a) Interlocked 22

23 Output/Write Handshaking Step. The HC2 places data on the port pins and asserts H to indicate that it has valid data to be output. Step 2. The output device latches the data and asserts H2 to acknowledge the receipt of data. Step 3. The HC2 output pin de-asserts H following the assertion of H2. The output device then de-asserts H2. H Data Valid Data H2 ECE 450 (a) Interlocked 23

24 Electrical Characteristic Consideration for I/O Interfacing Most systems require the use of logic chips and/or peripheral devices apart from the microcontroller to perform their function These chips may use different types of Integrated Circuit (IC) technologies. If so, there is a concern that the resultant system may not function properly The ICs must be electrically compatible Two issues involve Voltage-level compatibility Current drive capacity ECE

25 Voltage and Current Voltage-level compatibility High output level of an IC chip high enough to be considered as a high for the input of another chip Low output level of an IC chip low enough to be considered as a low for the input of another chip Current drive capability Output of an IC chip have enough current to drive its load Can the output circuit of an IC chip sink the current of its load Signal timing is also an important factor for making sure that the digital circuit functions properly The main concern about timing is whether the signal from one chip becomes valid enough to be used by another IC chip in a timely (clock based?) manner ECE

26 Voltage Level compatibility Voltage level compatibility issue arises because IC technologies differ in the following four voltages: Input High Voltage (VIH) Input Low voltage (VIL) treated as logic when applied as input to the digital circuit treated as logic 0 when applied as input to the digital circuit Output High Voltage (VOH) voltage level when digital circuit outputs a logic Output Low Voltage (VOL) voltage level when digital circuit outputs a logic 0 ECE

27 Voltage Level compatibility (2) In order for the digital circuit X to be able to drive circuit Y, the following conditions must be satisfied The output high voltage of device X (VOHX) must be higher than the input high voltage of device Y (VIHY). The output low voltage of device X (VOLX) must be lower than the input low voltage of device Y (VILY). ECE

28 Logic Family Voltage Levels Logic Family V CC V IH V OL V IL V OL HCS2 3 5 V 3.25 V 4.2 V.75 V 0.8 V S 4 5 V 2.0 V V 0.8 V V 2 LS 4 5 V 2.0 V V 0.8 V V 2 AS 4 5 V 2.0 V V 0.8 V 0.35 V F 4 5 V 2.0 V 3.4 V 0.8 V 0.3 V HC 3 5 V 3.5 V 4.9 V.5 V 0. V HCT 3 5 V 3.5 V 4.9 V.5 V 0. V ACT 3 5 V 2.0 V 4.9 V 0.8 V 0. V ABT 3 5 V 2.0 V 3.0 V 0.8 V 0.52 V BCT 5 5 V 2.0 V 3.3 V 0.8 V 0.42 V FCT 5 5 V 2.0 V 2.4 V 0.8 V 0.55 V. V OH value will get lower when output current is larger. 2. V OL value will get higher when output current is larger. The V OL values of different logic gates are slightly different 3. HCS2, HC, HCT, ACT are based on CMOS technology. 4. S, LS, AS, and F are based on bipolar technology. 5. ABT, BCT, and FCT are based on bi-cmos technology. ECE

29 HC2 Compatibility 5 Volt technology compatibility CMOS is compatible LS TTL is not compatible ECE

30 Voltage Level compatibility (3) Summarizing Voltage Level Compatibilities: HCS2 cannot be driven by a bipolar device (S, LS, AS, F). HCS2 can be driven by CMOS devices (HC, HCT) HCS2 may not work with ACT CMOS devices, VIL=VOL HCS2 will likely have problems with Bi-CMOS, VIL=VOL and VOH <= VIH(HC2) (ABT, BCT, FCT) ECE

31 Current Drive Capability Microcontrollers needs to drive other peripheral I/O devices in an embedded system Other issue is whether the microcontroller can source (when the output voltage is high) or sink (when the output voltage is low) the current needed by the I/O device that it interfaces with Need to make sure the following two requirements Each I/O pin can supply and sink the current needed by the I/O device that it interfaces with Total current required to drive I/O devices does not exceed the maximum current rating of the microcontroller ECE 450 3

32 Current Considerations Each logic chip has the following four currents that are involved in the current drive calculations Input high current (IIH) Input low current (IIL) Input current (flowing into the input pin) when the input voltage is high Input current (flowing out of the input pin) when the input voltage is low Output high current (IOH) Output low current (IOL) Output current (flowing out of the output pin) when the output voltage is high Output current (flowing into the output pin) when the output voltage is low ECE

33 Terms: Fan-out and Fan-in Fan-in: Fan-out: how many devices driven an integrated circuit to perform its function. Usually applied to logic gates how many devices can be driven by a circuits output. Often done based on a technology family or typical input current IOH I Fanout min, I IH I Note: Driving analog circuits or LEDs can rapidly change the output current required. Note2: A digital output should never drive both analog and digital inputs! OL IL ECE

34 Logic Family Current Levels Logic Family V CC I IH I IL I OH I OL HCS V 2.5 ua 2.5 ua 25 ma 25 ma S 5 V 50 ua.0 ma ma 20 ma LS 5 V 20 ua 0.2 ma 5 ma 24 ma AS 5 V 20 ua 0.5 ma 5 ma 64 ma F 5 V 20 ua 0.2 ma ma 20 ma HC 3 5 V ua ua 25 ma 25 ma HCT 3 5 V ua ua 25 ma 25 ma ACT 3 5 V ua ua 24 ma 24 ma ABT 3 5 V ua ua 32 ma 64 ma BCT 5 V 20 ua ma 5 ma 64 ma FCT 3 5 V ua ua 5 ma 64 ma. Values are based on the 74XX244 devices of Texas Instruments.. 2. The total HCS supply current is 65 ma. 3. The values of I IH and I IL are input leakage currents. ECE

35 Current Source and Sink To determine whether a pin can supply or sink currents to all peripheral pins that it drives correctly, designer needs to check the two requirements The IOH of an output pin must be equal to or larger than the total current flowing into all the peripheral pins that are connected to this pin. The IOL of an output pin must be equal to or larger than the total current flowing out from all the peripheral pins that are connected to this pin Also need to make sure that the total current needed to drive the peripheral signal pins do not exceed the total current the microcontroller can supply ECE

36 Fan-Out HC2* to HC2s Fan out 2.5mA 2.5mA min,, uA 2.5uA HC2* to LS TTL Fan out 2.5mA 2.5mA min, 20uA 0.2mA 2.5 HC2* to HC/HCT Fan out 2.5mA 2.5mA min, ua ua 2,500 LS TTL to HC2 Fan out 5mA 24mA min, 2.5uA 2.5uA 6,000 HC/HCT to HC2 Fan out 25mA 25mA min, 2.5uA 2.5uA 0,000 * 2.5 ma vs. 25 ma due to spec sheet ECE

37 HC2 I/O P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. ECE MC9S2DP256B Device User Guide V02.5, Doc. No. 9S2DP256BDGV2/D, Original Release Date: 29 Mar 200, Revised: Jan, 2005, Motorola, Inc

38 Timing Compatibility Timing compatibility needs to be taken into consideration if the I/O pin is driving a flip-flop or a latch Latch or flip-flop has a control signal or clock signal to control the latching of an input signal D Q D t su t hd CLK Q CLK (a) (b) Figure 7.28 D flip-flop and its latching timing requirement ECE

39 Timing Compatibility (2) Main timing consideration is the setup and hold time requirements for all flip-flop and latches Setup and hold time needs to be addressed in order for the system to work properly If the signal passes through several intermediate devices before it reaches latches or flip-flops, time delays of all intermediate devices needs to be taken into account D Q D t su t hd CLK Q CLK (a) (b) ECE 450 Figure 7.28 D flip-flop and its latching timing requirement 39

40 Timing Compatibility (3) Setup and hold times describe the timing requirement on the input of the flip-flop with respect to the clock input Setup time is the time that the input must be valid before the flipflop samples Hold time is the time that the input must be maintained valid after the flip flop samples Setup and hold time define a window of time during which the input must be valid and stable in order to get the valid data on the output D Q D t su t hd CLK Q CLK (a) (b) ECE Figure 7.28 D flip-flop and its latching timing requirement

41 Interfacing with Output Devices Many embedded devices only require interfacing with simple input and output devices such as switches, light emitting devices, keypads, seven segment displays etc Interfacing with LED s: LED s are often used to indicate the system operation mode Whether the system is turned on Whether the system operation is normal Whether the system is in error mode etc An LED can illuminate when it is forward biased and has sufficient current following through it The current required to light an LED is nominally around 0mA The 7-segfment displays want 20 ma. ECE 450 4

42 Interfacing with LEDs Three methods for interfacing with LED s Method A and B are recommended for use with LED s that need only to 2mA to produce enough brightness The circuit C is required for use with LED s that need larger current to light and the ECE 450/5530 labs Circuit C Resistor value can be between 330 ohm and Kohm Port pin R (a) positive direct drive Port pin 74HC04 ECE 450 Figure 7.29 An LED connected to a CMOS inverter through a current- limiting resistor. 42 R2 (b) inverse direct drive V CC Port pin V CC (c) buffered drive R3

43 Lab LED and Light Bar Connections Buffer the HC2 port Inverting buffer 540 Non-inverting buffer 54 Provide current sinking for the LED Resistor between +5 and LED If you short the LED while probing, the resistor provides current limiting Resistor Value LED needs ~.2 to.8 V drop LED wants ~ 0 ma 5V.8V R 320 0mA 5V.2V R 380 0mA ECE

44 Interfacing with Seven Segment Displays Seven segment displays are often used when the embedded products needs to display only a few digits Seven segment displays are mainly used to display decimal digits and a small subset of letters Although HCS2 devices have enough current to drive a seven segment display, it is not advisable to do when a HCS2 based embedded product needs to drive many other I/O devices Best way is to use a buffer chip 74HC244 between microcontroller and seven segment display 74HC244 provides 5v and using a 330 ohm resistor between 74HC244 and seven segment display provides a current of 0mA, sufficient to illuminate an LED ECE

45 Lab 7-Segment Displays Single Digit, Red, Common Anode Display,6 a b c d e f g dp a Data Sheet Values: Forward Voltage V at I=0 ma f e g b c ECE d dp

46 Driving a Common Anode Display Forward Voltage V at I=0 ma R 5V 2.V to 2.6V 0mA 240 R 290 HC2 Pin,6 a b c d e f g dp Inverting Buffer HC2 Pin HC2 Pin HC2 Pin HC2 Pin HC2 Pin HC2 Pin ECE HC2 Pin

47 ECE BCD to 7-Segment Decoder BCD digit a b c d e f g Segments Corresponding Hex Number $7E $30 $6D $79 $33 $5B $5F $70 $7F $7B Table 7.5 BCD to seven-segment decoder a b c d e f g dp

48 Multiple Displays, Common Cathode Some applications needs to display multiple BCD digits, then time multiplexing technique will be used Seven segment displays consists of either a common anode or common cathode which plays a key role in turning on and off the seven segment display Common Cathode (Note: The lab uses common Anode) Common cathode of the seven segment display is connected to the collector of an NPN transistor When a high voltage is applied to the base of the NPN transistor, it is driven to saturation The common cathode of the display will then be driven low allowing the display to be lighted By turning the NPN transistors ON and OFF many times in a second, multiple digits can be displayed ECE

49 Multiple 7-Segment Displays, Common Cathode 74HC a b g #5 #4 #0 a a b b... g g PB6 PB5 PB0 PK5 PK4 PK0 R... 2N2222 R common cathode 2N2222 R common cathode common cathode I MAX = 70 ma 2N2222 HCS2 Figure 7.32 Port B and Port K together drive six seven-segment displays (MC9S2DP256) ECE

50 Multiple Displays, Common Anode Some applications needs to display multiple BCD digits, then time multiplexing technique will be used Seven segment displays consists of either a common anode or common cathode which plays a key role in turning on and off the seven segment display Common Anode Common anode of the seven segment display is connected to the collector of a PNP transistor When a low voltage is applied to the base of the PNP transistor, it is driven to saturation The common anode of the display will then be driven high allowing the display to be lighted By turning the PNO transistors ON and OFF many times in a second, multiple digits can be displayed ECE

51 Example 7.4 Example 7.4 Write a sequence of instructions to display 4 on the seven-segment display #4 in Figure Solution: To display the digit 4 on the display #4, we need to: Output the hex value $33 to port B Set the PK4 pin to Clear pins PK5 and PK3...P0 to 0 #include <hcs2.inc> four equ $33 ; seven-segment pattern of digit 4 movb #$3F,DDRK ; configure PORT K for output movb #$FF,DDRB ; configure PORT B for output bset PTK,$0 ; turn on seven-segment display #4 bclr PTK,$2F ; turn off seven-segment displays #5, #3 #0 movb #four,ptb ; output the seven-segment pattern to PORTP In C language: DDRK = 0x3F; DDRB = 0xFF; ECE 450 PTK = 0x0; PTB = 0x33; 5

52 Example 7.5 Example 7.5 Write a program to display on the six sevensegment displays shown in Figure Solution: Display on display #5, #4, #3, #2, #, and #0, respectively. The values to be output to Port B and Port K to display one digit at a time is shown in Table 7.6. Table 7.6 Table of display patterns for Example 7.5 seven-segment display #5 #4 #3 #2 # #0 displayed BCD digit Port B $30 $6D $79 $33 $5B $5F Port K ECE $20 $0 $08 $04 $02 $0

53 Time Multiplexing 7-Segment Displays Start X address of display table Output the byte at [X] to port B Output the byte at [X]+ to Port K Increment X by 2 Wait for ms no X = display + 2? yes Figure 7.33 Time-multiplexed seven-segment display algorithm ECE

54 Code Example #include "c:\miniide\hcs2.inc" pat_port = PTB ; Port that drives the segment pattern pat_dir = DDRB ; direction register of the segment pattern sel_port = PTK ; Port that selects the digit sel_dir = DDRK ; data direction register of the digit select port.text _main:: movb #$FF,pat_dir ; configure pattern port for output movb #$3F,sel_dir ; configure digit select port for output forever: ldx #disp_tab ; use X as the pointer loop: movb,x+,pat_port ; output digit pattern and move the pointer movb,x+,sel_port ; output digit select value and move the pointer ldy # ; wait for ms jsr delaybyms ; cpx #disp_tab+2 ; reach the end of the table bne loop bra forever #include "c:\miniide\delay.asm" disp_tab.byte $30,$20 ; seven-segment display table.byte $6D,$0.byte $79,$08.byte $33,$04 ECE 450.byte $5B,$02.byte $5F,$0 54

55 DIP Switches Switch is probably the simplest input device available To make input more efficient, a set of eight switches organized as a Dual inline package (DIP) is often used A DIP package can be connected to any input port with eight pins such as PortA, PortB etc When a switch is closed, the associated port input is 0, otherwise the associated port input is Each port input is pulled up high via a 330 ohm or Kohm resistor when the associated switch is open ECE

56 Connecting DIP Switches V CC SW DIP-8 0K PA0 PA PA2 PA3 PA4 PA5 PA6 PA7 HCS2 Figure 7.39 Connecting a set of eight DIP switches to Port A of the HCS2 ECE

57 Buffering Dip Switches For the ECE 450 Lab, all dip switches should be buffered. One possible buffering configuration is shown here ECE

58 Reading DIP Switches Steps Ex: Instruction to read data from DIP switches on PortA Step: Define the corresponding Data Direction Register and Data Register of PortA Step2: Set the Data Direction Register of PortA to configure port as an input port Step3: Read the data from the Data register of PortA according to the requirements of the program. Data from the DIP switches is always available in the Data Register of the corresponding port with which it s interfaced to ECE

59 Code Example.area prog(abs) PORTA = $00 DDRA = $02.text _main:: Ldaa #$00 Staa DDRA Loop: Ldaa PORTA Staa result jsr delay5msec Bra Loop ECE

60 Switch/Contact Bounce A contact is made, many transient touch may occur.. ECE

61 Switch/Contact Bounce Contact bounce is due to the dynamics of a closing contact The signal falls and rises within a period of about 5ms as a contact bounces Human being cannot press and release a switch in less than 20ms, a debouncer will recognize that the switch is closed after the voltage is low for about 0ms and will recognize after that the switch is open after the voltage is high for about 0ms Both H/W and S/W solutions to the key bounce problem are available H/W solution includes an analog circuit that uses a resistor and a capacitor, and two digital solutions that uses S-R latches or CMOS buffers and double throw switches ECE 450 6

62 Switch Bounce Mitigation Set-Reset Latch Set-Reset Latches Before being presses, the key is touching the set input and the Q voltage is high When pressed the key moves towards the reset position When the key is not touching either Set or Reset, both inputs are pulled low by the pull-down resistor (no change in output) When key touches the reset position, the Q voltage will go Low If bouncing of the Set or Reset contact occurs, the first instance will set or reset the device and others will have no effect ECE

63 Switch Bounce Mitigation Non inverting CMOS buffer Non inverting CMOS buffer with high input impedance The CMOS buffer output is identical to its input When the switch is connected, the input to the buffer chip is grounded/vdd and hence Vout is forced low/high When the key switch is not connected, the resistor R keeps the input voltage at the same level as the output voltage This is due to the high input impedance of the buffer, which causes a negligible voltage drop on the feedback resistor Once initial switch connection is made, the output moves to the desired voltage and no connect bouncing will not effect the output ECE

64 Switch Bounce Mitigation Capacitor Integrated de-bouncers The RC constant of the integrator determines the rate at which the capacitor charges up towards the supply voltage once the ground connection via the switch has been removed As long as the capacitor voltage does not exceed the logic 0 threshold value, the Vout signal will be recognized as logic 0 The cheapest approach! ECE

65 Switch Bounce Mitigation Software Software De-bouncing Technique The most popular and simple one has been the wait and see method. Wait to see if the switch value stabilizes. In this method, the program simply waits for about 0 ms and reexamines the same key again to see if it is still pressed. ECE

66 Keypad Interfacing A Keypad is another commonly used input device Keypad is arranged as an array of switches, which can be mechanical, membrane, capacitors or Hall-effect in construction Mechanical Switches Two metal contacts are brought together to complete an electrical circuit Membrane Switches Plastic or rubber membrane presses one conductor onto the other Capacitive Switches comprise of two plates of a parallel plate capacitor. Pressing the key cap effectively increases the capacitance between the two plates Hall effect Switches Motion of the magnetic flux lines of a permanent magnet perpendicular to the crystal is detected as a voltage, which resembles a switch closure ECE

67 6-Button Keypad Series 96 by Grayhill, Inc. Web Site: Matrix connections based on which key is pressed Time multiplex pins -4 while reading pins 5-8 A keypad controller IC can be purchased to act as a peripheral ECE

68 Keypad Scanning Keypad scanning is usually performed row-by-row, column-by-column A 6-key keypad can be easily interfaced using any available I/O port For the keypad application the upper four pins of the port should be configured for output and the lower four pins of the port should be configured for input The rows and columns of a keypad are simply conductors The keypad interface setup to HCS2 PortA is as shown in the next slide ECE

69 Keypad Circuitry HCS2 MCU PA7 outputs PA6 PA5 PA4 PA3 3 7 B F inputs PA2 PA A 9 E D PA C 0K V CC Figure 7.4 Sixteen-key keypad connected to the HCS2 0 PA7 PA6 PA5 PA4 Selected keys ECE , 4, 8, C,, 5, 9, D, 2, 6, A, E, Table 7.6 Sixteen-key keypad row selections and 3 and 7 and B and F

70 Keypad Operation PortA pins PA3 PA0 are pulled up to high by pull-up resistors Whenever a key switch is pressed, the corresponding row and column are shorted together In order to distinguish the row being scanned and those not being scanned, the row being scanned is driven low, where as other rows are driven high PA7 PA6 PA5 PA4 Selected keys , 4, 8, C,, 5, 9, D, 2, 6, A, E, and 3 and 7 and B and F Table 7.6 Sixteen-key keypad row selections ECE

71 More Text I/O Examples LCD Controller An interface to a microcontroller that runs an LCD Digital to Analog Converter Stepper Motor Control Drive a positioning motor for robotics, etc. OK for not really fast drive motors ECE 450 7