8051 I/O and Class 6 EE4380 Spring 03. Pari vallal Kannan. Center for Integrated Circuits and Systems University of Texas at Dallas

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1 8051 I/O and 8255 Class 6 EE4380 Spring 03 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas

2 Why I/O Ports Controllers need to get external inputs and produce external outputs I/O ports serve the purpose 8051 has 4 built-in I/O ports Too many ports increase pin-count and device cost. Too few makes it inadequate for complex control needs Generally, Ports are scarce and Port usage/allotment is an engineering decision 6-Feb-03 2

3 8051 I/O Ports Internal Structure 32 pins are allotted for 4 eight bit I/O ports P0, P1, P2, P3 At power-on all are output ports by default Write D PORT LATCH P1.X CLK Q QB Vcc Internal Load M1 Pin P1.X To configure any port for input, write all 1 s (0xFF) to the port Q=1, QB=0, M1=OFF, Read_Pin asserted by read instruction INTERNAL BUS READ LATCH READ PIN 6-Feb-03 3

4 8051 I/O Ports (contd.) Ports can be read and written to like normal registers mov A, #55H mov P0, A mov P1, A mov P2, #0AAH xlr P1, #0FFH mov P0, #0FFH mov A, P0 ; can use A ; write A to P0 ; can use immediate mode ; read-modify-write (ex-or) ; configure P0 for input ; read from P0 Ports can be bit manipulated (single bit addressable) using cpl and setb instructions cpl P1.2 ; complement bit 2 of Port1 setb P1.3 ; set bit 3 for Port1 to 1 clr P0.0 ; clear bit 0 of Port0 6-Feb-03 4

5 8051 I/O Ports Pin Muxing Port pins are muxed with other signals P0 : Also carry A0:A7 and D0:D7 P1 : dedicated P2 : Also carry A8:A15 P3 : Also carry serial I/O (TxD, RxD), Timer inputs (T0, T1), external interrupts (INT0, INT1) and read write signals (RD, WR) For 8051 or DS5000, with no external memory, P0, P1 and P2 are available. For 8031, only P2 is available To increase the number of ports, use a Parallel port interface chip like Feb-03 5

6 8051 I/O Ports : Hardware Specs P0 is open drain. Has to be pulled high by external 10K resistors. Not needed if P0 is used for address lines P1, P2, P3 have internal pull-ups Port fan-out (number of devices it can drive) is limited. Use buffers (74LS244, 74LS245, etc) to increase drive. P1, P2, P3 can drive up to 4 LS-TTL inputs P0 fan-out is dependant on the pull-up resistor value, limited by the max current it can sink on the output stage. 6-Feb-03 6

7 8051 I/O Ports : Input Quirks Port read instructions either Read from the 8051 pins ( voltage levels on the pins) Read from an internal latch on the ports Writing 1 to the latch Q=1, QB=0 M1 off P1.x is available at tristate buffer Writing 0 to the latch Q=0, QB=1 M1 ON Input always gets 0 Can damage the port (M1) if P1.x is Vcc Use 10K resistance between switch on P1.x and Vcc Or use a SPST switch connected to GND Write INTERNAL BUS D PORT LATCH P1.X CLK Q QB READ LATCH Vcc READ PIN Internal Load M1 Pin P1.X 6-Feb-03 7

8 Input Quirks (contd.) Instructions that read the pins (READ_PIN is asserted) mov A, Px jnb Px.y jb Px.y mov C, Px.y Instructions that read the latch (READ_LATCH is asserted) They read the last output value and not the value on the pins [anl, orl, xrl] Px [jbc, djnz] Px.y, target [cpl, clr, setb] Px.y [inc, dec] Px 6-Feb-03 8

9 Switch On IO Ports Vcc +5V Port Pin 1. Good 10K Port Pin Internal Pullup Case-1 (top left and right): Gives a logic 0 on switch close Current is 0.5ma on switch close GND GND Pull-up needed if P0 Case-2: Vcc +5V Vcc +5V Gives a logic 1 on switch close High current on switch close Port Pin Port Pin Case-3: 2. Poor Poor Can damage port if 0 is output GND 6-Feb-03 9

10 DIP Switches on IO port GND Vcc +5 V SW-DIP8 10K ResPack 8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 DIP switches usually have 8 switches Use the case-1 from previous page Can use a Resistor Pack, instead of discrete resistors 6-Feb-03 10

11 Vcc +5 V LED on IO Port Vcc +5V Vcc +5V 470 Port Pin Port Pin Port Pin 1. Good 2. Poor 3. Poor 330 CA a b c d e f g dp 7seg LED - Common Anode P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P Vcc +5 V CA 330 7seg LED - Common Anode GND 8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Try to use current sinking Case-1 LED is ON for an output of zero Most LEDs drop 1.7 to 2.5 volts and need about 10ma Current is (5-2)/470 Case-2 Too much current Failure of Port or LED Case-3 Not enough drive (1ma) LED too dim Seven Segment LEDs Common Anode/ Cathode CA preferred Case-1 may have LEDs of different brightness 6-Feb-03 11

12 8051 Interfacing with the Widely used I/O chip 40 pins Provides 3 eight bit ports PA, PB and PC Port PC can be used as two 4 bit ports PCL and PCU Ports have handshaking ability Two address lines A0,A1 and a Chip select CS Address space of 4 bytes 00b selects Port A 01b selects Port B 10b selects Port C 11b selects a control register 6-Feb-03 12

13 8255 Functional Diagram CS is used to interface with 8051 If CS is generated from lets say Address lines A15:A12 as follows, A15:A12 = 1000 D7-D0 RD PA PB Base address of 8255 is WR PC 1000 xxxx xxxx xx00b 8000H A0 A1 Address of the registers PA = 8000H CS RESET PB = 8001H PC = 8002H CR = 8003H 6-Feb-03 13

14 8255 Operating Modes Mode 0 : Simple I/O Any of A, B, CL and CU can be programmed as input or output Mode 1: I/O with Handshake A and B can be used for I/O C provides the handshake signals Mode 2: Bi-directional with handshake A is bi-directional with C providing handshake signals B is simple I/O (mode-0) or handshake I/O (mode-1) BSR (Bit Set Reset) Mode C alone is available for bit mode access 6-Feb-03 14

15 8255 Configuration Configured by writing a control-word in CR register CR definition D7 : 1 I/O mode, 0 BSR D6,D5 : Mode selection for A and CU 00 Mode0, 01 Mode1, 1x Mode2 D4 : Port A control 1 A input, 0 A output D3 : Port CU control 1 CU input, 0 CU output D2 : Port B Mode selection 0 B is in mode 0, 1 B is in mode 1 D1 : Port B control 1 B input, 0 B output D0 : Port CL control 1 CL input, 0 CL output Refer to 8255 datasheet for additional options 6-Feb-03 15

16 8255 Usage: Simple Example 8255 memory mapped to 8051 at address 8000H base PA = 8000H, PB = 8001H, PC = 8002H, CR = 8003H Control word for all ports as outputs in mode0 CR : b = 80H Code snippet test: mov A, #80H ; control word mov DPTR, #8003H ; address of CR A ; write control word mov A, #55h ; will try to write 55 and AA alternatively repeat: mov DPTR, #8000H ; address of PA A ; write 55H to PA inc DPTR ; now DPTR points to PB A ; write 55H to PB inc DPTR ; now DPTR points to PC A ; write 55H to PC cpl A ; toggle A (55 AA, AA 55) acall MY_DELAY ; small delay subroutine sjmp repeat ; for (1) 6-Feb-03 16

17 Next Class Interfacing a keypad Interfacing a character LCD Scanned LED displays 6-Feb-03 17

ELEG3923 Microprocessor Ch.4 I/O Ports

Department of Electrical Engineering University of Arkansas ELEG3923 Microprocessor Ch.4 I/O Ports Dr. Jingxian Wu wuj@uark.edu OUTLINE 2 8051 I/O programming I/O bit manipulation programming I/O PORT