Mercury CA1. User Manual. FPGA Module. Document Info. Marc Oberholzer, Christoph Glattfelder

Transcription

1 Mercury CA1 FPGA Module User Manual Document Info Product Manager Author(s) Reviewer(s) Martin Heimlicher André Schlegel Marc Oberholzer, Christoph Glattfelder Enclustra GmbH Technoparkstr. 1 CH-8005 Zürich Switzerland Phone

2 Document Info Version 1.11 Date Enclustra GmbH Technoparkstr. 1 CH-8005 Zürich Switzerland Phone

3 Copyright reminder Copyright 2016 by Enclustra GmbH, Switzerland. All rights are reserved. Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice. All information in this document is strictly confidential and may only be published by Enclustra GmbH, Switzerland. All referenced trademarks are the property of their respective owners. Document History Version Date Author Comment D. Ungureanu Updated section Ethernet PHY Configuration and Secure EEPROM G. Köppel Updated section Ethernet PHY and Secure EEPROM P. Clements Corrected the naming of the modules in the Module Configurations section and in the DDR2 SDRAM parameters section B.Pfiffner Updated section DDR2 SDRAM P. Clements Updated to the latest pin naming, removed Mercury module connector and differential pairs net lengths tables M. Oberholzer Updated to the latest document template, added assembly drawings, added information on differential input termination resistor identifiers and locations, updated accessories section, minor improvements throughout the document S. Ziegler Corrected SPI Flash size to 16 MB S. Ziegler Corrected module dimensions top view (FX10) / 63 Version 1.10

4 Version Date Author Comment C. Glattfelder Updated SPI Flash programming section M. Oberholzer Corrected LED count in section Module Description C. Glattfelder Differential trace length table added André Schlegel First release / 63 Version 1.10

5 Table of Contents 1 Overview General Warranty RoHS Disposal and WEEE Safety Recommendations and Warnings Electro-Static Discharge EMC Features Deliverables Accessories Mercury PE1 Board Module Description Block Diagram Module Configurations Part Numbers and Ordering Codes Module Top-/Bottom Views Top View Bottom View Assembly Drawings Assembly Drawing (Top View) Assembly Drawing (Bottom View) Module Footprint Mercury Module Connectors User I/Os Pinout I/O Types FPGA I/O Banks VREF Usage VCC_IO Usage Dual Purpose Pins Signal Terminations / 63 Version 1.10

6 2.9 Power Power Generation Overview Power Enable Supply Voltage Inputs Supply Current Consumption Supply Voltage Outputs Supply Current Consumption Example Heat Dissipation Clock Generation Overview Signal Description LEDs FPGA LEDs DDR2 SDRAM DDR2 SDRAM Type Signal Description On-Die Termination Parameters SPI Flash SPI Flash Type Signal Description FPGA Bit Streams Ethernet Ethernet PHY Type Ethernet PHY Configuration Signal Description External Connectivity USB USB Device Controller Type Signal Description RTC RTC Type SHA1-EEPROM EEPROM Type Current and Power Monitor Monitor Type / 63 Version 1.10

7 3 FPGA Configuration Master Serial Configuration SPI Flash Programming Signal description In-System-Programming using the Quartus-II Programmer Slave Serial Configuration Signal Description Firmware Download via USB FPGA Configuration Flash Programming JTAG Signal description External connectivity I 2 C Communication Overview Signal description I2C Decive Addresses SHA-1 EEPROM Memory Map Technical Data Absolute Maximum Ratings Recommended Operating Conditions Mechanical Data Ordering and Support Ordering Support Additional Information Mercury Module Connector Pinout Differential Pairs Net Length / 63 Version 1.10

8 1 Overview 1.1 General The Mercury CA1 FPGA modules are optimized for SoPC high speed communication and DSP applications. They offer high-performance and yet low-cost Altera Cyclone IV E FPGAs, large and high-bandwidth memory, an USB 2.0 High-Speed interface, LVDS I/Os as well as a gigabit Ethernet interface. The use of Mercury CA1 FPGA modules, in contrast to building a custom FPGA hardware, significantly simplifies system design and thus shortens time to market and decreases the development effort of your product. The Mercury Starter base board enables you to quickly put together a prototyping system and start developing your system 'hands-on' Warranty For information concerning the warranty please read through the General Business Conditions on Enclustra s website RoHS The Mercury module are designed and produced according to the Restriction of Hazardous Substances (RoHS) Directive (2011/65/EC) Disposal and WEEE The Mercury modules must be disposed properly at the end of its life span. If a battery is installed onto the board it must also be disposed correctly. The Mercury modules are not designed ready for operation for the end-user. The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mercury boards. Nonetheless users should still dispose the product properly at the end of life Safety Recommendations and Warnings Ensure that the power supply is disconnected from the board before inserting or removing a Mercury module, connecting interfaces, replacing SD-Cards and batteries, connecting jumpers, etc. Take special care with the mounting orientation of Mercury modules they can fit in the connectors both ways round. The base board and the module may be damaged if inserted the wrong way and powered up. Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage / 63 Version 1.10

9 Over-voltage on power or signal lines can cause permanent damage Electro-Static Discharge Electronic boards are sensitive to Electro-Static Discharge (ESD). Please ensure that the product is handled with care and only in an ESD protected environment EMC This is a Class A product and is not intended to be used in domestic environments. The product may cause electromagnetic interference in which appropriate measures must be taken. 1.2 Features Altera Cyclone IV E FPGA Up to 256 MB DDR2 SDRAM Up to 16 MB SPI Flash Gigabit Ethernet PHY 25MHz clock generator Hi-Speed Dual USB UART/FIFO I2c EEPROM with SHA-1 Engine 24 differential pairs and 98 single-ended user I/Os or 148 single-ended user I/Os Voltage and temperature monitoring Single input supply V 1.2 V / 1.8 V / 2.5 V / 3.3 V I/Os Smaller than a credit card: (65 x 54 mm, dual 168-pin Hirose FX10 connectors) 1.3 Deliverables Mercury CA1 FPGA module Mercury CA1 user manual 2 (this document) Mercury CA1 pinout list (Microsoft Excel document) Mercury CA1 Reference Design Mercury CA1 VHDL Top-Level and pinout files / 63 Version 1.10

10 Mercury CA1 reduced schematics Mercury Master pinout excel sheet and Module Pin Connection Guidelines Mercury CA1 IO Netlength excel sheet 1.4 Accessories The Mercury-family base boards are ideal for rapid prototyping and low volume series for Mercury CA1 FPGA module based systems Mercury PE1 Board Dual 168-pin Hirose FX10 connectors for Enclustra Mercury FPGA modules Low-jitter clock generator System monitor System controller emmc Managed NAND flash PCIe 2.0 x4 interface USB 3.0 device interface 4 USB 2.0 host interface USB 2.0 device (UART, SPI, I2C, JTAG) mpcie/msata card holder FMC LPC connector 2 40-pin Anios pin header 3 12-pin Pmod pin header 5 to 15V or USB bus power (with restrictions) More information about the Mercury PE1 Baseboard is found on our webpage / 63 Version 1.10

11 2 Module Description 2.1 Block Diagram Figure 1: Hardware Block Diagram The heart of the Mercury CA1 FPGA module is the Altera Cyclone IV E FPGA device. Most of its I/O pins are connected to the Mercury module connector, making 148 user I/Os available at the Mercury module connector. The memory subsystem is built from a 16 MB SPI Flash and a 128 MB DDR2 SDRAM in the standard configuration. The FPGA is either configured with a bitstream residing in the SPI Flash, via an USB device controller fitted on the module, via an external microcontroller or via the JTAG interface connected to Mercury module connector. The module is also equipped with a gigabit Ethernet PHY, making it ideal for communication applications. A FTDI USB 2.0 High-Speed interface is fitted on the module to easy implement a communication link to a host PC. A real time clock as well as a voltage and power monitoring is available on the I2C bus for SOPC applications. The 25 MHz clock generation is done based on a 50 MHz crystal oscillator. The module-internal supply voltages (1.0 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V) are generated from the single input supply voltage V / 63 Version 1.10

12 Three yellow LEDs are connected to FPGA pins for easy status signaling. A yellow LED is connected to a FTDI USB 2.0 High-Speed controller user pin for easy status signaling. 2.2 Module Configurations Part number FPGA SDRAM Flash Temp Range ME-CA1-30-8C-D7 EP4CE30F23C8N 128 MB DDR2 16 MB C ME-CA1-75-8C-D7 EP4CE75F23C8N 128 MB DDR2 16 MB C ME-CA C-D8 EP4CE115F23C8N 256 MB DDR2 16 MB C Table 1: Standard Module Configurations Table 1 shows the available standard module configurations. Custom configurations are possible; please contact us for further information. 2.3 Part Numbers and Ordering Codes Every module has a label with a marking specifying the part number and the serial number, as shown in Figure 2: Part Number EN SN Serial Number Figure 2: Module label Table 2 shows the correspondence between part number and ordering code. Part number EN EN Ordering code ME-CA I-D8-R6 ME-CA C-D8-R / 63 Version 1.10

13 Part number EN EN EN EN EN EN EN EN EN Ordering code ME-CA C-D8-R6 ME-CA1-30-7I-D7-R6 ME-CA1-30-8C-D7-R4 ME-CA1-30-8C-D7-R5 ME-CA1-30-8C-D7-R6 ME-CA1-75-7I-D7-R6 ME-CA1-75-8C-D7-R4 ME-CA1-75-8C-D7-R5 ME-CA1-75-8C-D7-R6 Table 2: Part Numbers and Ordering Codesa / 63 Version 1.10

14 2.4 Module Top-/Bottom Views Top View Figure 3: Module Top View Bottom View Figure 4: Module Bottom View / 63 Version 1.10

15 2.5 Assembly Drawings Assembly Drawing (Top View) Figure 5: Assembly Drawing (Top View) / 63 Version 1.10

16 2.5.2 Assembly Drawing (Bottom View) Figure 6: Assembly Drawing (Bottom View) / 63 Version 1.10

17 2.6 Module Footprint Figure 7 shows the dimensions of the module footprint on the base board. Maximal component height under the module is depending on the connector type. See section 2.7 for detailed connector information. Figure 7: Module Dimensions Mounting Holes Top View Warning The Mercury CA1 FPGA module may be placed the wrong way around on the base board. Always check that the mounting hole positions on the base board and the Mercury CA1 FPGA module are aligned! / 63 Version 1.10

18 6.0mm 48.0mm 2x Ø 1.2mm 5.8mm 50.2mm J701 J700 2x Ø 1.1mm Figure 8: Module Dimensions Module Connector Holes Top View 2.7 Mercury Module Connectors Two Hirose FX pin 0.5mm pitch headers with a total of 336 pins have to be integrated on the base board. Up to four M3 screws may be used to mechanically fasten a Mercury module to the base board. The pinout of the module connector is found in section 7.1 on page 59. Figure 7 shows the mechanical drawing of the module footprint. Table 3 shows the connector type as well as some additional information. The connector is available with different packaging options (only tray packaging listed below, see datasheet for detailed options) and different stacking heights. Reference Type Description Digikey Part Number Mercury Module Connector A/B FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4mm stacking height FX10A-168P-SV(71)-ND Mercury Module Connector A/B FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5mm stacking height FX10A-168P-SV1(71)-ND Table 3: Mercury Connector Types Figure 9 shows the pin numbering for the Mercury module connectors J700 and J701. The pins of the Mercury module connector J700 are numbered J700-1 to J while the pins of the Mercury module connector J701 are numbered J701-1 to J / 63 Version 1.10

19 Figure 9: Pin Numbering for the Mercury Module Connector (Base Board Top View) Warning Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board as this could damage the Mercury module as well as the base board. Always make sure that the Mercury module is oriented the right way before plugging it into the base board. 2.8 User I/Os Pinout The pinout of the module connector is found in section 7.1 on page I/O Types Six different I/O types do exist. The following table shows the characteristics of each I/O type. TYPE Description Direction Termination Note IO_Bn_RX_CLKyP_zz IO_Bn_RX_CLKyN_zz Differential Input Clock Pair Input Only 100 Ω on board Each differential input clock pair can optionally be used as two single ended input clocks. For that purpose the 100 Ω termination resistor must be removed. IO_Bn_xP_zz IO_Bn_xN_zz Differential IO Pair Input or Output - Each differential IO pair can optionally be used as two single ended IOs / 63 Version 1.10

20 TYPE Description Direction Termination Note IO_Bn_RX_xP_zz IO_Bn_RX_xN_zz Differential Input Pair Input Only 100 Ω on board Each differential input pair can optionally be used as two single ended inputs. For that purpose the 100 Ω termination resistor must be removed. Bn_IN_CLKy Single Ended Input Clock Input Only - - IO_Bn_zz Single Ended IO Input or Output - - IO_Bn_S_zz Restricted Single Ended IO Input or Output - These IOs can only be used if no differential modes of any FPGA banks are used. Table 4: I/O Types Description Key: n: FPGA I/O bank number x: Differential pair number y: Clock input number (according to the FPGA pin name) zz: FPGA pin number (e.g. AA3) Warning Using differential signals in single ended mode may have an affect to any other differential signals located on the same FPGA bank. Check the pinout of your FPGA design using Altera Quartus II. FPGA Bank IO_Bn_RX_CLKyP_zz IO_Bn_RX_CLKyN_zz IO_Bn_xP_zz IO_Bn_xN_zz IO_Bn_RX_xP_zz IO_Bn_RX_xN_zz Bn_IN_CLKy Bn_IO_yy Bn_IOS_yy Bank Bank 2 1 pair 9 pairs / 63 Version 1.10

21 FPGA Bank IO_Bn_RX_CLKyP_zz IO_Bn_RX_CLKyN_zz IO_Bn_xP_zz IO_Bn_xN_zz IO_Bn_RX_xP_zz IO_Bn_RX_xN_zz Bn_IN_CLKy Bn_IO_yy Bn_IOS_yy Bank 3 1 pair - 4 pairs Bank 4 1 pair - 4 pairs Bank 5-5 pairs Bank Bank Bank Total 3 pairs 14 pairs 8 pairs Table 5: I/O Types vs. FPGA I/O Banks / 63 Version 1.10

22 2.8.3 FPGA I/O Banks The FPGA s I/O pins are grouped into eight I/O banks. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and reference (VREF) voltages. Table 6 shows the main attributes of the FPGA I/O banks. Bank Connectivity VCCO VREF Bank 1 Ethernet, FTDI USB controller, SPI Flash, I2C, FPGA configuration 3.3 V Not Supported Bank 2 Mercury module connector User selectable (VCC_IO_B2) Bank 3 Mercury module connector User selectable (VCC_IO_B3) Bank 4 Mercury module connector User selectable (VCC_IO_B4) Bank 5 Mercury module connector User selectable (VCC_IO_B5) Bank 6 Mercury module connector User selectable (VCC_IO_B6) User selectable User selectable User selectable User selectable User selectable Bank 7 DDR2 SDRAM 1.8 V 0.9 V Bank 8 DDR2 SDRAM, Ethernet 1.8 V 0.9 V Table 6: FPGA I/O Banks VREF Usage Referenced I/O standards using VREF can be used on Mercury module connector. The reference voltage has to be applied to all VREF pins of the respective bank(s). If a bank is configured to use an unreferenced I/O standard, the VREF pins of this bank on the Mercury module connector are available as user I/O pins / 63 Version 1.10

23 Warning Only use VREF voltages compliant with the equipped FPGA device. Any other voltages may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module. Do not leave a VREF pin floating when using a referenced I/O standard. Doing so may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module VCC_IO Usage The VCC_IO for the I/O banks located on Mercury module connector are configurable by applying the required voltage to the VCC_IO_B[x] pins on the Mercury module connector. Table 7 shows the VCC_IO_B[x] pins located on Mercury module connector. Signal name FPGA Pins FPGA Pin type Supported Voltages VCC_IO_B2 All VCC_IO2 pins VCC_IO2 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V VCC_IO_B3 All VCC_IO3 pins VCC_IO3 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V VCC_IO_B4 All VCC_IO4 pins VCC_IO4 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V VCC_IO_B5 All VCC_IO5 pins VCC_IO5 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V VCC_IO_B6 All VCC_IO6 pins VCC_IO6 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V Connector Pins J J J J J J J J J J Table 7: VCCO Pins Warning Only use VCCO voltages compliant with the equipped FPGA device. Any other voltages may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module. Do not leave a VCC_IO pin floating. Doing so may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module / 63 Version 1.10

24 2.8.6 Dual Purpose Pins Table 8 lists pins that have special functions during the FPGA configuration or when activated in the bitstream. For more details please refer to the Cyclone IV Configuration Handbook 11. FPGA Pin Mercury CA1 Signal Special Function CRC_ERROR IO_B6_L21 Active-high signal that indicates that the error-detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error-detection circuit is enabled. This pin can be set in Quartus II software to support open-drain output. DEV_CLR# IO_B5_3P_N21 Optional chip-wide reset pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. DEV_OE IO_B5_3N_N22 Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. INIT_DONE IO_B6_L22 This is a dual-purpose status pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. Table 8: Dual Purpose Pins Signal Terminations Differential Inputs All differential inputs (IO_Bn_RX_xP_zz / IO_Bn_RX_xN_zz) and differential clock inputs (IO_Bn_RX_CLKyP_zz / IO_Bn_RX_CLKyN_zz) are terminated on the Mercury CA1 module by means of 100 Ω parallel termination resistors. These differential inputs can be used as single-ended inputs, if the corresponding 100 Ω parallel termination resistors are removed from the Mercury CA1 FPGA module. Table 9 shows the resistor identifiers for each of the differential input pairs. Differential Input Pair IO_B3_RX_0P_AA8 / IO_B3_RX_0N_AB8 IO_B3_RX_1P_AA9 / IO_B3_RX_1N_AB9 Resistor Identifier R305 R / 63 Version 1.10

25 Differential Input Pair IO_B3_RX_2P_W10 / IO_B3_RX_2N_Y10 IO_B3_RX_3P_AA10 / IO_B3_RX_3N_AB10 IO_B4_RX_0P_AA13 / IO_B4_RX_0N_AB13 IO_B4_RX_1P_AA14 / IO_B4_RX_1N_AB14 IO_B4_RX_2P_W13 / IO_B4_RX_2N_Y13 IO_B4_RX_3P_AA15 / IO_B4_RX_3N_AB15 IO_B2_RX_CLK1P_T2 / IO_B2_RX_CLK1N_T1 IO_B3_RX_CLK6P_AA11 / IO_B3_RX_CLK6N_AB11 IO_B4_RX_CLK7P_AA12 / IO_B4_RX_CLK7N_AB12 Resistor Identifier R307 R308 R309 R310 R311 R312 R304 R303 R300 Table 9: Parallel Termination Resistor Identifiers for Differential Input Pairs Figure 10 shows the location of the parallel termination resistors for the differential input pairs. Please see Figure 6 for locating the region of interest on the Mercury CA1 FPGA Module s bottom side (use SC3 as orientation reference) / 63 Version 1.10

26 Figure 10: Parallel Termination Resistor Locations for Differential Input Pairs Differential IOs Differential IOs (IO_Bn_xP_zz / IO_Bn_xN_zz) are not terminated on the Mercury CA1 module by external termination resistors. These IOs must be terminated by external termination resistors on the base board (close to the module pins) Single-Ended Outputs There are no series termination resistors on the Mercury CA1 module for single-ended outputs. If required, series termination resistors may be equipped on the base board (close to the module pins) / 63 Version 1.10

27 2.9 Power Power Generation Overview The Mercury CA1 module uses a single power input voltage in the range of 5..15V nominal. Four supply voltages (3.3V, 2.5, 1.8V, 1.2V) are generated by the module-internal power circuitry. The 3.3V and the 2.5V voltage are fed to pins on the Mercury module connectors and can thus be used to power devices on the base board. A current and power monitor accessible through I2C can be used to observe the power consumption on the 1.2V voltage that is used as FPGA core voltage. Please note that the output of the 1.2 V regulator is limited to 8A. Since the power consumption may be higher for big FPGA devices with high toggling rates, the 1.2V regulator might be replaced by a 12A device for custom configurations. Mercury Module Connectors (10 Pins) PWR_EN I2C_SCL PWR_GOOD VCC_3V3 I2C_SDA (10 Pins) VCC_IN 5..15V max 3A VCC_2V5 (8 Pins) Input Power Filter PWR_EN PWR_GOOD I2C FPGA 16mA IR3841 η = 85% 1.2V / 8A Current/ Power Monitor INA220 max 8A LDO 5V LP V / 150mA 16mA IR3841 ƞ = 90% PWR_GOOD 3.3V / 8A max 3A 20mA 3mA PWR_EN PWR_GOOD 100mA 100mA LM26420X ƞ = 85% 2.5V / 2A max 1.6A 200mA 1.8V / 2A 400mA 200mA 50mA 450mA LDO 1.0V LD39015 M10R 1.0V / 150mA 100mA Figure 11: Power Generation Overview Power Enable The Mercury CA1 FPGA module provides a power enable input on the Mercury module connector. This input may be used to shut down the DC/DC converters for 1.2 V, 1.8 V and 2.5 V generation, / 63 Version 1.10

28 which leave the FPGA, the DDR2 SDRAM, the gigabit Ethernet PHY and the FTDI USB controller unpowered. The 3.3 V power rail is always active. The PWR_EN input is pulled to 3.3 V on the Mercury CA1 module with a 2k2 pull-up resistor. Leaving it unconnected will thus result in an always powered FPGA. The PWR_GOOD output is pulled to 3.3 V on the Mercury CA1 module with a 2k2 pull-up resistor. It is pulled down by any of the switching regulators (1.2 V, 1.8 V, 2.5 V or 3.3 V) if a problem occurs. Pin name Module Connector Pin Remarks PWR_EN J Floating/3.3V: core power supplies enabled Tied to GND: core power supplies disabled PWR_GOOD J : at least one power supply not ok 1: all power supplies ok Table 10: Module Power Enable Pins Warning Do not apply other voltages to the PWR_EN pin than 3.3V or GND. Doing so may damage the Mercury CA1 FPGA module. It is OK to leave the PWR_EN pin unconnected Supply Voltage Inputs A total of 10 Mercury module connector pins are used to feed the input supply voltage to the Mercury CA1 FPGA module. The maximum current consumption of the Mercury CA1 FPGA module is limited by the Mercury module connector, which is rated with 300 ma per pin according to the Hirose FX10 datasheet 4. Thus a maximum current of 3A can be consumed by the Mercury CA1 FPGA module. Pin name Module Connector J700 Pins Module Connector J701 Pins Nominal Voltage Minimum Voltage Maximum Voltage Maximum Current VCC_MOD 1, 2, 3, 4, 5, 6, 7, 8, 9, 11-5 V...15 V 4.75 V V 3 A Table 11: Supply Voltage Inputs / 63 Version 1.10

29 2.9.4 Supply Current Consumption The total input supply current I VCC_MOD can be expressed as follows PVCC _1V 2 PVCC _ 3V 3 1.2V I P VCC _1V 2 VCC _ 3V 3 Ptot 1 V 2 3 V 3 IVCC IN I LDO V I LDO _ 5V 2 16mA VCC _ IN VCC _ IN VCC _ IN P VCC_1V2 denotes the total consumed power on the 1.2V power supply while P VCC_3V3 denotes the total consumed power on the 3.3V power supply. η 1V2 and η 3V3 denote the efficiency of the 1.2V and 3.3V DC/DC converters. Because the 1.8 V and 2.5 V are generated based on the 3.3 V power supply the total consumed power of the 3.3 V is expressed as P VCC _ 3V 3 3.3V I 3.3V I VCC _ 3V 3 VCC _ 3V 3 P 2.5V I 0.85 VCC _ 2V 5 2V 5 VCC _ 2V 5 P VCC _1V 8 1V 8 1.8V I V I VCC _1V 8 VCC _ 3V 3 2.5V I VCC _ 2V 5 2V 5 1.8V I VCC _1V 8 1V 8 According to the equation above the higher the input supply voltage the lower the input supply current. Warning The power consumption of the FPGA is highly dependent on the configured bitstream and the actual I/O activity. Be sure to connect a power supply that is capable of delivering the required power. Please calculate the power budget of your design as described in section Make sure that voltage connected to the VCC_MOD pins and the consumed supply current are within the tolerance specified in Table 11. If this is not the case, the Mercury CA1 FPGA module will most likely not function properly and may even be Supply Voltage Outputs Two of the four generated supply voltages on the module can be used to power devices located on the base board. Table 12 lists the available supply voltages and the respective supply voltage pins. The maximum current that can be consumed of these output supply voltages are limited by the Mercury module connector and by the voltage regulators / 63 Version 1.10

30 Nominal Output Voltage Vnom Tolerance Module Connector J700 Pins Module Connector J701 Pins Max. Current Imax 3.3V +/- 5% 26, 29, 50, 86 55, 79, 115, 127, 152, 155 3A 2.5V +/- 5% 53, 62, 65, 89 52, 76, 108, 128 2A Table 12: Supply Voltage Outputs Warning The maximum output current must not be exceeded under any circumstances. Doing so will most likely cause malfunctions on the Mercury CA1 FPGA module and may even damage it Supply Current Consumption Example This section shows the typical supply current consumption for a mixed SoPC and DSP application for Cyclone IV E EP4CE30 and EP4CE75 devices. The tables below list the test conditions that are used to estimate power consumption of the FPGA. Condition EP4CE30 EP4CE75 SoPC Part Clock frequency 100 MHz 100 MHz Number of used LUTs Number of used FFs Number of used M9K Block RAMs Number of used 18x18 multipliers 4 4 Table 13: FPGA Test Conditions (SOPC) Condition EP4CE30 EP4CE75 DSP Part Clock frequency 250 MHz 250 MHz / 63 Version 1.10

31 Condition EP4CE30 EP4CE75 Number of used LUTs Number of used FFs Number of used M9K Block RAMs Number of used 18x18 multipliers Table 14: FPGA Test Conditions (DSP) The tables below list the total supply current consumption for different supply voltages and different FPGA types. Consider that the total supply current consumption I_VCC_MOD can be beyond the specification for lower input supply voltages VCC_MOD. Input Supply Voltage VCC_MOD [V] I_VCC_1V2 [A] I_VCC_2V5 external [A] I_VCC_2V5 total [A] I_VCC_3V3 external [A] I_VCC_3V3 total [A] I_VCC_MOD [A] Table 15: Typical Supply Current Consumption EP4CE30 Input Supply Voltage VCC_MOD [V] I_VCC_1V2 [A] I_VCC_2V5 external [A] I_VCC_2V5 total [A] I_VCC_3V3 external [A] I_VCC_3V3 total [A] I_VCC_MOD [A] / 63 Version 1.10

32 Table 16: Typical Supply Current Consumption EP4CE75 The Mercury CA1 module allows a maximum input supply current of 3.0 A. This input supply current depends on the FPGA configuration, the current consumption of the 2.5V 3.3V supply voltage which are fed to the module connector as well as on the input supply voltage. Warning The Mercury CA1 module allows a maximum input supply current of 3.0 A. This input supply current depends on the FPGA configuration, the current consumption of the 2.5V 3.3V supply voltages which are fed to the module connector as well as on the input supply voltage. The 1.2 V power supply provides a maximal output current of 8.0A.This may not be sufficient for larger FPGA devices operated at high clock frequencies (>200MHz) and signal toggle rates (50%). Please check your design s power consumption using the Heat Dissipation The required airflow can be calculated by using the Cyclone IV E power estimation spreadsheet provided by Altera 5. Warning Always make sure that the required airflow really is available. A heat sink for the Mercury CA1 module s FPGA may be required in some cases. Overheating may lead to damages on the Mercury CA1 FPGA module Clock Generation Overview A 50 MHz crystal oscillator is integrated on the Mercury CA1 FPGA module, whose output signal is divided into a 25 MHz clock. The 25 MHz clock is fed to the FPGA and additionally fed to the Ethernet PHY. The Ethernet PHY generates a 125 MHz reference clock based on the 25 MHz clock. This 125 MHz reference clock is also connected to the FPGA but is not always available (e.g. only a 25 MHz clock is available when the Ethernet PHY is in reset). For more details please refer to the Marvel 88E1318 Ethernet PHY datasheet / 63 Version 1.10

33 Signal Description Clk Signal Name Freq (MHz) FPGA Pin FPGA Pin Type CLK B12 CLK9/DIFFCLK_5P CLK A12 CLK8/DIFFCLK_5N Table 17: Clock Resources 2.11 LEDs FPGA LEDs Three yellow LEDs are connected to the FPGA. Optionally, a fourth LED is connected to the FPGA, but its pin is shared with a control signal of the FTDI USB device controller. In order to use the fourth LED, resistor R208 must be assembled while R210 has to be removed. Signal Name FPGA Pin FPGA Pin Type Module Connector Remarks J701 Led_N<0> B1 DIFFIO_L2N 29 Active low Led_N<1> B2 DIFFIO_L2P 33 Active low Led_N<2> J2 DIFFIO_L23P 37 Active low LED_N<3>* J1 DIFFIO_L23N 41 Active low This LED is connected to a multipurpose pin on the FPGA and cannot be used by default. Table 18: FPGA LEDs 2.12 DDR2 SDRAM The DDR2 SDRAM equipped on the Mercury CA1 is specified up to 400 MHz (CL 5-5-5) but please note: The Altera DDR2 memory controller supports only up to 166MHz on Cyclone IV! / 63 Version 1.10

34 DDR2 SDRAM Type Table 19 shows the equipped DDR2 SDRAM types. Please note that other types might be used in future. Type Size Configuration Manufacturer Datasheet W971GG6JB MB 64M x 16bit Winbond W972GG6JB MB 128M x 16bit Winbond Table 19: DDR2 SDRAM Type Signal Description Table 20 shows the signals of the FPGA-DDR2 SDRAM interface. Signal name FPGA Pin FPGA Pin type IO voltage Ddr2_A<0> E12 DIFFIO_T33P 1.8V Ddr2_A<1> F13 DIFFIO_T46P 1.8V Ddr2_A<2> E15 DIFFIO_T52P 1.8V Ddr2_A<3> E16 DIFFIO_T60N 1.8V Ddr2_A<4> F15 DIFFIO_T60P 1.8V Ddr2_A<5> F14 DIFFIO_T59P 1.8V Ddr2_A<6> C19 DIFFIO_T56N 1.8V Ddr2_A<7> D19 DIFFIO_T56P 1.8V Ddr2_A<8> B10 DIFFIO_T30P 1.8V Ddr2_A<9> A7 DIFFIO_T23N 1.8V Ddr2_A<10> B7 DIFFIO_T23P 1.8V Ddr2_A<11> A8 DIFFIO_T25N 1.8V Ddr2_A<12> B8 DIFFIO_T25P 1.8V Ddr2_A<13> A9 DIFFIO_T29N 1.8V / 63 Version 1.10

35 Signal name FPGA Pin FPGA Pin type IO voltage Ddr2_Dq<0> C6 DIFFIO_T15N 1.8V Ddr2_Dq<1> A3 DIFFIO_T9N 1.8V Ddr2_Dq<2> B3 DIFFIO_T9P 1.8V Ddr2_Dq<3> A4 DIFFIO_T14N 1.8V Ddr2_Dq<4> B4 DIFFIO_T14P 1.8V Ddr2_Dq<5> A5 DIFFIO_T18P 1.8V Ddr2_Dq<6> F10 DIFFIO_T17P 1.8V Ddr2_Dq<7> F8 DIFFIO_T11N 1.8V Ddr2_Dq<8> A13 DIFFIO_T35N 1.8V Ddr2_Dq<9> A14 DIFFIO_T36N 1.8V Ddr2_Dq<10> B14 DIFFIO_T36P 1.8V Ddr2_Dq<11> A15 DIFFIO_T45N 1.8V Ddr2_Dq<12> B15 DIFFIO_T45P 1.8V Ddr2_Dq<13> B16 DIFFIO_T49P 1.8V Ddr2_Dq<14> E14 DIFFIO_T46N 1.8V Ddr2_Dq<15> D13 DIFFIO_T44P 1.8V Ddr2_Clk_N A18 DIFFIO_T53N 1.8V Ddr2_Clk_P B18 DIFFIO_T53P 1.8V Ddr2_Cke A20 PLL2_CLKOUTN 1.8V Ddr2_Ba<0> E11 DIFFIO_T32N 1.8V Ddr2_Ba<1> A17 DIFFIO_T50N 1.8V Ddr2_Ba<2> B17 DIFFIO_T50P 1.8V / 63 Version 1.10

36 Signal name FPGA Pin FPGA Pin type IO voltage Ddr2_Cs_N B9 DIFFIO_T29P 1.8V Ddr2_Cas_N A16 DIFFIO_T49N 1.8V Ddr2_Ras_N C13 DIFFIO_T44N 1.8V Ddr2_We_N C17 DIFFIO_T54P 1.8V Ddr2_Dm<0> F7 DIFFIO_T3N 1.8V Ddr2_Dm<1> F11 DIFFIO_T32P 1.8V Ddr2_Dqs <0> C8 DIFFIO_T20N 1.8V Ddr2_Dqs <1> B13 DIFFIO_T35P 1.8V Ddr2_Odt B20 PLL2_CLKOUTP 1.8V Table 20: DDR2 SDRAM Signal Description On-Die Termination No external termination is implemented on the hardware. It is thus strongly recommended to enable the DDR2 SDRAM device s on-die termination (ODT) feature Parameters Module SDRAM Size 128 MByte ME-CA1-30-8C-D7 256 Mbyte ME-CA C-D8 Reference Design ME-CA1-75-8C-D7 Data Width 16 bit 16 bit 16 bit Bank Bits Row Bits Column Bits / 63 Version 1.10

37 Module SDRAM Size 128 MByte ME-CA1-30-8C-D7 256 Mbyte ME-CA C-D8 Reference Design ME-CA1-75-8C-D7 FMAX 166,7 MHz 166,7 MHz 166,7 MHz tck CAS Latency trrd 10 ns 10 ns 10 ns trefi 7.8 us 7.8 us 7.8 us trfc ns ns ns trcd 12.5 ns 12.5 ns 12.5 ns trp 12.5 ns ns ns tccd trc 57.5 ns ns ns twr 15 ns 15 ns 15 ns tras(max) 70 us 70 us 70 us tras(min) 45 ns 45 ns 45 ns twtr 7.5 ns 7.5 ns 7.5 ns Table 21: DDR2 SDRAM Parameters For the DDR2 Ram are used the data (Reference Design) by the Table 21 DDR2 SDRAM Parameters. With these parameters can run all different boards with the same bit stream. All the information for Quartus can be found under Mercury CA1 Memory Templates SPI Flash The SPI Flash can be used to store the FPGA bit streams, NIOS II application code and other user data. It is connected to the FPGAs configuration port and the signals are also available on the Mercury / 63 Version 1.10

38 module connector. Please refer to section 3 for more details about FPGA configuration and programming the Flash memory SPI Flash Type Table 22 shows the equipped SPI Flash device type. Type Size Manufacturer Datasheet M25P128-VME6TG 128 Mbit Numonyx / STMicro 6 Warning Table 22: SPI Flash Type Other Flash memory devices might be equipped on future revisions of the Mercury CA1 module. In Slave Serial configuration mode the configuration clock pin can t be switched to output mode after configuration. Therefore the SPI Clock must be connected to another IO pin if the SPI flash shall be used after configuring the FPGA in Slave Serial mode Signal Description Table 23 shows the signals of the SPI Flash interface. Signal name FPGA Pin Mercury Connector Pin IO voltage CLK K2 J V DO/IO1 K1 J V DI/IO0 D1 J V CS# E2 J V HOLD#/IO3 WP#/IO2 n.c. Pulled to VCC_3V3 n.c. Pulled to VCC_3V3 n.c. - n.c. - Table 23: SPI Flash Signal Description / 63 Version 1.10

39 FPGA Bit Streams The SPI Flash can be used to store the FPGA configuration bitstream. If the FPGA shall be configured from the SPI Flash, the bitstream has to be stored at address 0. The size of the bitstream is dependent of the equipped FPGA type. The remaining SPI Flash sectors are available for user data storage. See also section 3. Table 24 shows the bitstream sizes of different FPGAs. FPGA Size No of Sectors (64kByte) EP4CE Mbit 146 EP4CE Mbit 146 EP4CE Mbit 228 EP4CE Mbit 305 EP4CE Mbit 436 Table 24: FPGA Bit Stream Sizes 2.14 Ethernet There is one 10/100/1000 Mbit Ethernet PHY on the CA1 board, connected to the FPGA via the RGMII interface. The 25 MHz clock for the PHY is generated on board from the 50 MHz oscillator. A 125 MHz reference clock generated by the PHY is fed back to the FPGA. All necessary components for the Ethernet PHY are on board. The signals on the Mercury Module connector can be connected directly to the magnetics. The center tap voltage is also provided by the Mercury CA1 FPGA module (see also section ). The LED signals are active low Ethernet PHY Type Table 25 shows the equipped Ethernet PHY device type. With revision 6, a new type of PHY has been introduced. This requires new software functions to configure the PHY. Revision Type Manufacturer MDIO Address Type R1 to R5 88E1318 Marvell 0 10/100/1000 Mbit R6 KXZ9031RNXIA Micrel 3 10/100/1000 Mbit Table 25: Ethernet PHY Type / 63 Version 1.10

40 The Marvel 88E1318 datasheet is only available on Marvell s extranet (account creation required) ( Ethernet PHY Configuration The new Ethernet PHY on the Mercury CA1 module requires the configuration of the RGMII delays in order to achieve the same timing as the Marvel 88E1318 PHY used in the previous versions. The steps required for the PHY configuration are presented in Table 26. Step Register Write Value Description 1 0xD 0x0002 Select MMD Device Address 2h 2 0xE 0x0004 Select RGMII Control Signal Pad Skew Register 3 0xD 0x4002 Select register data for the selected register 4 0xE 0x0070 Write the value for Control Delay (RX delay = 7, TX delay = 0) 5 0xD 0x xE 0x0005 Select RGMII RX Data Pad Skew Register 7 0xD 0x xE 0x7777 Write the value for RX Delay (RX delay = 7 for all lanes) 9 0xD 0x xE 0x0006 Select RGMII TX Data Pad Skew Register 11 0xD 0x xE 0x0000 Write the value for TX Delay (TX delay = 0 for all lanes) 13 0xD 0x xE 0x0008 Select RGMII Clock Pad Skew Register 15 0xD 0x xE 0x03FF Write the value for Clock Delay (RX delay = 31, TX delay = 31) Table 26 Ethernet PHY Configuration- RGMII Delays / 63 Version 1.10

41 Because the new PHY is on MDIO address 3 and the previous version was on MDIO address 0, there are no compatibility issues when using a logic block or a firmware code that configures the Micrel Ethernet PHY. The configuration can be used with any module revision Signal Description Table 27 shows the signals of the Ethernet interface. Signal name FPGA Pin FPGA Pin type IO voltage ETH_INT# A11 DIFFCLK_4N 1.8 V ETH_RST# G5 VREFB1N0 3.3 V ETH_MDC H7 DIFFIO_L1P 3.3 V ETH_MDIO D10 DIFFIO_T31N 1.8 V ETH_RXC B11 DIFFCLK_4P 1.8 V ETH_RX_CTL B6 DIFFIO_T22P 1.8 V ETH_RXD0 C3 DIFFIO_T4N 1.8 V ETH_RXD1 C7 DIFFIO_T20P 1.8 V ETH_RXD2 E7 DIFFIO_T7N 1.8 V ETH_RXD3 F9 IO 1.8 V ETH_TXC E5 PLL3_CLKOUTP 1.8 V ETH_TX_CTL E6 PLL3_CLKOUTN 1.8 V ETH_TXD0 A6 DIFFIO_T22N 1.8 V ETH_TXD1 D7 DIFFIO_T15P 1.8 V ETH_TXD2 A10 DIFFIO_T30N 1.8 V ETH_TXD3 C4 DIFFIO_T4P 1.8 V Table 27: Ethernet Signal Description / 63 Version 1.10

42 External Connectivity The Ethernet lines can be directly connected to the magnetics. Please refer to the Mercury Master Pinout and the Enclustra Module Pin Connection Guidelines for more details about the connection of Ethernet signals USB USB Device Controller Type Table 22 shows the equipped USB controller device type. Type Manufacturer Datasheet FT2232HQ FTDI 7 Table 28: USB Device Controller type The FTDI FT2232H USB device controller can be used to easy implement a communication link to a host PC. Port A is intended for data transfer in UART, SPI, I2C or synchronous FIFO mode. Port B is used to configure the FPGA, program the SPI Flash and access the I2C bus. Note that for synchronous FIFO mode an additional D Flip-Flop is inserted for each of the read and write control signals (FTDI_RD#, FTDI_WR#, see Figure 12) in order to meet the setup time of the FT2232H. For more information please refer to the schematics. For more information about the FPGA configuration and SPI Flash programming and I2C bus access refer to section 3.4. For more information about the I2C bus access refer to section 4. FT2232H Cyclone IV E FPGA FTDI_CLKOUT FTDI_D [7:0] FTDI_OE# Q D FTDI_RD# Q D FTDI_WR# FTDI_RXF# FTDI_TXE# FTDI_SIWU Figure 12: FT2232H Synchronous FIFO Mode Connectivity / 63 Version 1.10

43 Figure 12 shows the connectivity between the FPGA and the FT2232H USB device controller in synchronous FIFO mode Signal Description Table 27 shows the signals of the USB interface for the synchronous FIFO configuration. Signal name FPGA Pin FPGA Pin type IO voltage FTDI_CLKOUT G1 CLK1 3.3 V FTDI_D0 D2 DIFFIO_L5P 3.3 V FTDI_D1 E1 DIFFIO_L8N 3.3 V FTDI_D2 E3 DIFFIO_L3N 3.3 V FTDI_D3 E4 DIFFIO_L3P 3.3 V FTDI_D4 F1 DIFFIO_L9N 3.3 V FTDI_D5 F2 DIFFIO_L9P 3.3 V FTDI_D6 G3 DIFFIO_L1N 3.3 V FTDI_D7 H6 DIFFIO_L6P 3.3 V FTDI_OE# J1 DIFFIO_L23N 3.3 V FTDI_RD# H2 DIFFIO_L13P 3.3 V FTDI_WR# J6 DIFFIO_L6N 3.3 V FTDI_RXF# H1 DIFFIO_L13N 3.3 V FTDI_TXE# J4 DIFFIO_L12P 3.3 V FTDI_SIWU H5 VREFB1N1 3.3 V Table 29: FTDI USB Controller in Synchronous FIFO Mode Signal Description 2.16 RTC A real time clock is connected to the I2C bus. VCC_BAT can be connected directly to a 3V battery or left open. The RTC also features a battery buffered 128 bytes user SRAM and a temperature sensor. See section 4 for more details about the I2C bus on the Mercury CA / 63 Version 1.10

44 RTC Type Table 25 shows the equipped RTC device type. Type Manufacturer Datasheet ISL12020M Intersil 8 Table 30: Real Time Clock Type 2.17 SHA1-EEPROM The security EEPROM is used to store the module type and serial number as well as the Ethernet MAC address and other information. It is connected to the I2C bus. See section 4 for more details. This EEPROM should only be read be the user. With revision 6 a new type of EEPROM has been introduced. This requires new software functions to access the module information. Refer to the EEPROM manufacturer s datasheet for details EEPROM Type Table 31 shows the equipped EEPROM device type. Revision Type Manufacturer Datasheet R1 to R5 DS28CN01 Maxim 9 R6 ATSHA204A Atmel Table 31: EEPROM Type 2.18 Current and Power Monitor An I2C current and power monitor can be equipped to monitor the 1.2V supply. The shunt for the monitor is 5 mω. See section 4 for more details about the I2C bus on the Mercury CA Monitor Type Table 32 shows the equipped current monitor device type. Type Manufacturer Datasheet INA220 TI 10 Table 32: Current Monitor Type / 63 Version 1.10

45 3 FPGA Configuration Table 33 shows the FPGA configuration pins and their location on the Mercury module connector. These signals allow to boot the FPGA from the SPI Flash (section 3.1), to program the SPI Flash from an external device (section 3.2) or to directly configure the FPGA from an external device (section 3.2.2). The pins MSEL0, MSEL2 and MSEL3 of the FPGA are always low. Signal Name FPGA Pin FPGA Pin Type SPI Flash Pin Mercury Module Connector Pin FPGA_DCLK K2 DCLK CLK J FPGA_DI K1 IO/DATA0 DO J FPGA_STATUS# K6 STATUS# - J FPGA_CONF_DONE M18 CONF_DONE - J FPGA_CONFIG# K5 CONFIG# - J FPGA_MODE (L18) 1 MSEL1 - J FLASH_DI D1 DIFFIO_L5N DI J FLASH_CS# E2 DIFFIO_L8P CS# J Table 33: FPGA Configuration Interface Warning All configuration signals except FPGA_STATUS#, FPGA_MODE and FPGA_CONFIG# must be high impedance as soon as the FPGA is programmed! Violating this rule may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module. 3.1 Master Serial Configuration In master serial configuration mode the FPGA reads the bitstream from the SPI Flash. The bitstream must be located at address 0x0. 1 This signal is inverted on the Mercury CA1 module and thus not directly connected to the FPGA / 63 Version 1.10

46 Signal Name FPGA_DCLK FPGA_DI FPGA_STATUS# FPGA_CONF_DONE FPGA_CONFIG# FPGA_MODE FLASH_DI FLASH_CS# Description Must be high impedance during configuration and operation Must be high impedance during configuration and operation Is used as input to delay the start of the configuration when pulled low and is pulled low by the FPGA if any CRC error occurs during the configuration. Goes high after configuration (when enabled in the bitstream) When pulled low, the FPGA is de-configured and all pins are tri-stated. The rising edge of FPGA_CONFIG# initializes the configuration. Must be pulled down during and after configuration. Use a resistor (100R..560R) and do not connect FPGA_MODE directly to GND. Must be high impedance during configuration and operation Must be high impedance during configuration and operation Table 34: Master Serial Configuration Signal Description 3.2 SPI Flash Programming The signals of the SPI Flash are directly connected to the module connector. Because the SPI Flash signals are also connected to the FPGA, the FPGA pins must be tri-stated while accessing the SPI Flash directly. This is ensured by pulling the FPGA_CONFIG# signal to GND and the FPGA_MODE signal to VCC Signal description Signal Name FPGA_DCLK FPGA_DI FPGA_CONFIG# FPGA_MODE Description SPI clock SPI MISO Must be pulled to GND during SPI Flash programming. When released, all pins of the SPI interface must be high impedance! Must be high during the flash programming to put the SPI interface of the FPGA into high impedance mode! When FPGA_MODE is low, all pins of the SPI interface must be high impedance! / 63 Version 1.10

47 Signal Name FLASH_DI FLASH_CS# Description SPI MOSI SPI CS# Table 35: Flash Programming Signal Description Warning Accessing the SPI Flash directly without pulling FPGA_CONFIG# to GND and FPGA_MODE to VCC may damage the equipped FPGA device as well as other devices on the Mercury CA1 FPGA module In-System-Programming using the Quartus-II Programmer To do in-system programming with the Quartus-II Programmer (Cyclone IV datasheet section 8 11 ) the configuration signals have to be connected as shown in Table 36. Further, a jumper or DIP switch on the signal FPGA_MODE to GND must be installed. FPGA_MODE must be pulled to GND to allow the FPGA to load the bitstream from the SPI flash. But for the flash programming FPGA_MODE must be high. Signal Name Altera ByteBlaster Connector Signal Name FPGA_DCLK 1 2 GND FPGA_CONF_DONE 3 4 VCC FPGA_CONFIG# 5 6 Open FPGA_DI 7 8 FLASH_CS# FLASH_DI 9 10 GND Table 36: Altera ByteBlaster Connector Pinout for in-system Flash Programming 3.3 Slave Serial Configuration In the slave serial configuration mode, the bitstream is transmitted from an external device to the FPGA. The configuration pins of the FPGA are connected directly to the Mercury module connector. This allows configuring the FPGA from a microcontroller or another SPI capable device / 63 Version 1.10

48 Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device. For more details about the Altera configuration interface please refer to the Cyclone IV configuration handbook 11. FPGA_DCLK remains in input mode after the configuration has finished. If the SPI Flash shall be accessed after slave serial configuration, another IO pin must be connected to the FPGA_DCLK signal on the base board Signal Description Signal Name FPGA_DCLK FPGA_DI FPGA_STATUS# FPGA_CONF_DONE FPGA_CONFIG# FPGA_MODE Description Configuration clock Configuration data Is pulled low by the FPGA if any CRC error occurs during the configuration. Goes high after configuration When pulled low, the FPGA is de-configured and all pins are tri-stated. The rising edge of FPGA_ CONFIG # initializes the configuration. Must be pulled high (or left open) during and after configuration Table 37: Slave Serial Configuration Signal Description 3.4 Firmware Download via USB The FPGA configuration interface and SPI Flash signals are connected to the FTDI FT2232H USB device controller. This allows to configuring the FPGA over USB or programming the SPI flash from a PC without any additional hardware. The Enclustra FPGA module configuration tool is available for download on our homepage and offers both, FPGA configuration and Flash programming via USB. The FPGA is configured in serial slave mode; please refer also to section Port A of the FT2232H is used in synchronous FIFO mode to transfer data between the FPGA and the USB master. Port B of the FT2232H is used to interface to the I2C pins of the Mercury CA1 FPGA module and to program the SPI Flash or to configure the FPGA in passive serial mode. Furthermore, general purpose IO pins of Port B are used to control the configuration multiplexers (U ). The configuration multiplexers allow 4 different states as shown in Table 38. While accessing the SPI flash it is required to set FPGA_CONFIG# low to ensure that the FPGA SPI link is inactive! / 63 Version 1.10