Interfacing GSI Sync SRAMs to a Freescale Multiplexed MPC567xF or PXR40xx Microcontroller

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Frederica Heath
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1 N1020 Interfacing SI Sync SRMs to a Freescale Multiplexed MPC567xF or PXR40xx Introduction This application note will discuss interfacing a Freescale MPC567xF microcontroller or the Freescale e200 Power PXR40xx microcontroller operating in Multiplexed mode with SI Synchronous Burst SRMs. Compatibility The Freescale MPC567xF and PXR40xx are capable of interfacing with SRMs that operate in either Flow Through or Pipeline mode, which is selectable by the addition of wait states in the MPC567xF read timing. The SRMs must operate in a Late Write mode, where the data and byte writes are supplied one cycle after the write command is loaded. ll of SI s Synchronous Burst SRMs are compatible with the Freescale MPC567xF and PXR40xx. Interfacing Using 16-bit Multiplexed Mode Figure 1 shows the basic connection between either an MPC567xF or PXR40xx and a SI SRM. Both microcontrollers have been configured internally to interface with the SRM using 16-bit Multiplexed mode. During an address cycle while operating in 16-bit Multiplexed mode, the microcontroller utilizes the Data Bus D_DT[0:15] and parts of the address D_DD[8:15] to issues addresses [0:23]. The FT pin controls whether the SRM operates in Pipeline mode or Flow Through mode. This pin needs to be tied to V SS if the microcontroller is operating in a zero wait state Read mode, which is also referred to as Flow Through mode in the SRM datasheet. The FT pin will need to be tied to V DD if the microcontroller is operating in a one wait state Read mode, which is also referred to as Pipeline mode in the SRM datasheet. Freescale MPC567xF or PXR40xx Figure 1: Connection diagram 16-bit Multiplexed mode SI Synchronous SRM V DD for Pipeline mode D_DD[8:15] [16:23] D_DT[0:15] [0:15] & [0:15] FT CLKOUT DSP W DSC V SS for Flow Through mode V DD E2 WE[0:3] B B D E3 DV LBO V SS The MPC567xF and PXR40xx microcontrollers use a Late Write protocol when performing L2 cache writes. This requires the design to use the DSP pin to configure the SRM to utilize a Late Write protocol. Rev: /2011 1/ , SI Technology

2 N1020 Timing nalysis For all of the following timing diagrams, the SI pin names are displayed on the left next to the microcontroller pin names. Figure 2 is a timing diagram for L2 cache write. s seen in Figure 2, the addresses, supplied on D_DD and D_DT buses, and DSP signals are supplied on the first rising edge of clock for the beginning of the write cycle and the write enable, byte writes, and data signals are supplied on the following rising edge of clock. Figure 2: L2 Cache Write in 16-bit Multiplexed mode SRM D_DD[8:15] [16:23] DV DSP D_DT[0:15] [0:15] DT_ T Ba Bd WE Rev: /2011 2/ , SI Technology

3 N1020 Figure 3 illustrates a flow through read, which is also referenced as a zero wait state read. When the SRM operates in Flow Through mode, the read command is clocked in and data is referenced to the same rising edge of clock. Figure 3: 16-bit Flow Through mode or Zero Wait State Read SRM D_DD[8:15] [16:23] DV DSP D_DT[0:15] [0:15] Data Valid T Rev: /2011 3/ , SI Technology

4 N1020 Figure 4 illustrates a flow through read cycle followed by a write cycle. One thing to notice is the required deselect cycle that is added between the read cycle and the write cycle. The deselect cycle is necessary to allow the SRM to get off the bus and the microcontroller to begin driving. If this cycle is omitted, there will be bus contention and it is possible that the microcontroller will not latch in correct data. Figure 4: 16-bit Flow Through Read/Write Read Clock ap Write B Deselect SRM D_DD[8:15] 1[16:23] 2[16:23] DV DSP D_DT[0:15] 1[0:15] Data Valid 2[0:15] Data 2 T Ba Bd WE 2 Rev: /2011 4/ , SI Technology

5 N1020 Figure 5 illustrates a pipeline read, which is also referenced as a one wait state read. The read address is supplied on the rising edge of clock. On the next rising edge of the clock, data is driven out from the SRM. The data is referenced to the second rising edge of clock. Figure 5: 16-bit Pipeline Read or One Wait State Read SRM D_DD[8:15] [16:23] DV DSP D_DT[0:15] [0:15] Valid DT T Rev: /2011 5/ , SI Technology

6 N1020 Interfacing Using 32-bit Multiplexed Mode Figure 6 shows the basic connection between either an MPC567xF or PXR40xx and a SI SRM. Both the MPC567xF and PXR40xx have been configured internally to interface with the SRM using 32-bit Multiplexed mode. During an address cycle while operating in 32-bit Multiplexed mode, the microcontroller utilizes the Data Bus D_DT[9:30] to issues addresses [0:22]. The FT pin controls whether the SRM operates in Pipeline mode or Flow Through mode. This pin needs to be tied to V SS if the microcontroller is operating in a zero wait state Read mode, which is also referred to as Flow Through mode in the SRM datasheet. The FT pin will need to be tied to V DD if the microcontroller is operating in a one wait state Read mode, which is also referred to as Pipeline mode in the SRM datasheet. Freescale MPC567xF or PXR40xx Figure 6: Connection diagram 32-bit Multiplexed mode SI Synchronous SRM V DD for Pipeline mode D_DT[0:31] [0:22] [0:31] FT CLKOUT DSP W DSC V SS for Flow Through mode V DD E2 WE[0:3] B B D E3 DV LBO V SS Rev: /2011 6/ , SI Technology

7 N1020 The MPC567xF and PXR40xx microcontrollers use a Late Write protocol when performing L2 cache writes. This requires the design to use the DSP pin to configure the SRM to utilize a Late Write protocol. For all of the following timing diagrams, the SI pin names are displayed on the left next to the microcontroller pin names. Figure 7 is a timing diagram for L2 cache write. s seen in Figure 7, the addresses, supplied on the D_DT bus, and DSP signals are supplied on the first rising edge of clock for the beginning of the write cycle and the write enable, byte writes, and data signals are supplied on the following rising edge of clock. Figure 7: L2 Cache Write in 32-bit Multiplexed mode SRM D_DT[9:30] DV DSP D_DT[0:31] DT_ T Ba Bd WE Rev: /2011 7/ , SI Technology

8 N1020 Figure 8 illustrates a flow through read, which is also referenced as a zero wait state read. When the SRM operates in Flow Through mode, the read command is clocked in and data is referenced to the same rising edge of clock. Figure 8: 32-bit Flow Through mode or Zero Wait State Read SRM D_DT[9:30] DV DSP D_DT[0:31] Data Valid T Rev: /2011 8/ , SI Technology

9 N1020 Figure 9 illustrates a flow through read cycle followed by a write cycle. One thing to notice is the required deselect cycle that is added between the read cycle and the write cycle. The deselect cycle is necessary to allow the SRM to get off the bus and the microcontroller to begin driving. If this cycle is omitted, there will be bus contention and it is possible that the microcontroller will not latch in correct data. Figure 9: 32-bit Flow Through Read/Write Read Clock ap Write B Deselect SRM D_DT[9:30] 1 2 DV DSP D_DT[0:31] Data Valid Data 2 T Ba Bd WE 2 Rev: /2011 9/ , SI Technology

10 N1020 Figure 10 illustrates a pipeline read, which is also referenced as a one wait state read. The read address is supplied on the rising edge of clock. On the next rising edge of the clock, data is driven out from the SRM. The data is referenced to the second rising edge of clock. Figure 10: 32-bit Pipeline Read or One Wait State Read SRM D_DT[9:30] DV DSP D_DT[0:31] Valid DT T Summary The Freescale MPC567xF and PXR40xx microcontrollers will interface with SI Synchronous Burst SRMs that are configured to operate in either Pipeline or Flow Through mode. The timing diagrams in this document bridged the gap between those provided in the Freescale documentation referencing the microcontroller signal names and SI Synchronous Burst SRM signal names. designer using this document as a guide should be able to properly configure the interface to work with SI Synchronous BurstRM devices. If further questions still exist, please feel free to contact SI pplication Engineers at apps@gsitechnology.com. Rev: / / , SI Technology

Interfacing GSI Sync SRAMs to a Freescale MPC5554 microcontroller

Interfacing GSI Sync SRAMs to a Freescale MPC5554 microcontroller N1022 Interfacing SI Sync SRMs to a Freescale MPC5554 microcontroller Introduction This application note will discuss interfacing a Freescale MPC5554 microcontroller with SI Syncronous urst SRMs. Compatibility