ECEN 449 Microprocessor System Design. Memories

Transcription

1 ECEN 449 Microprocessor System Design Memories 1 Objectives of this Lecture Unit Learn about different types of memories SRAM/DRAM/CAM /C Flash 2 1

2 SRAM Static Random Access Memory 3 SRAM Static Random Access Memory 4 2

3 SRAM function When RowSelect = 1, cell can be written or read Cell written by precharging bit/bit~ lines to required value Write drivers more powerful than NOT gates Cell read by comparing bit/bit~ lines Single port which covers both reads and writes Sufficient for use as a processor register file? 5 Basic Processor Microarchitecture What must a register file do in each cycle? 6 3

4 Basic Processor Microarchitecture Register file may need to provide two source operands for the ALU Register file may need to store a resultant output from the ALU (or data memory) Up to three operations in one cycle! 7 Multi-ported SRAM Need support 2 reads and 1 write at the same time Add more bit and word lines 8 4

5 Dual Ported SRAM BitB Line WordB Line 9 Dual Ported SRAM Second Design What are the implications of this design vs. the previous dualported SRAM? 10 5

6 Register cell 2 Reads and 1 Write 11 SRAM 16 words, each word = 4bits 12 6

7 Register File 32 Registers each 32 bits 13 SRAM Access timing cycles 14 7

8 DRAM Dynamic RAM Benefits vs. SRAM? Costs? 15 DRAM Physical Implementation Types of DRAM Focused Ion Beam (FIB) cross-section of two DRAM cells 16 8

9 DRAM Charge on the capacitance stores data Optimized for area! Need to refresh memory Charge dissipates over time Over time 1 becomes 0 Reads are destructive To read, Row Select = 1, charge is transferred to bit line Capacitor discharged Every read requires rewriting read value back Only one port, one operation per cycle Buffering in SRAMs helps 17 DRAM organization 18 9

10 19 DRAM organization Typically Din, Dout combined into D pins WrEn (WriteEnable) and OEn (Output Enable) distinguish whether Data pins are input or output WrEn asserted, OEn deasserted D = Din (Write Cycle) WrEn deasserted, OEn asserted D = Dout (Read cycle) Column and Row addresses are serially input on address pins Column Address Select (CAS), Row Address Select (RAS) lines used RAS asserted => latch address as row address CAS asserted => latch address as column address 20 10

11 DRAM Read Timing 21 DRAM Write Timing 22 11

12 SRAM/DRAM comparison Speed SRAM +, DRAM Use SRAM for cache, network buffers, etc. Volatility SRAM retains data while power is on DRAM must be refreshed every few milliseconds Cost SRAM -, DRAM ++ Use DRAM for big, cheap memories Overhead SRAM +, DRAM (due to refreshing and clocks) Use SRAM for small memories, DRAM for big 23 Content Addressable Memory (CAM) In normal memories, we access data stored at a particular address We give the address as input, to write/read e data What if we want to access data by its contents (ie. map table in HW)? Content addressable memories Used extensively Network routers/switches Cache tag arrays Many microprocessor internal structures (reorder buffer, load-store queue, etc.) CAM tutorial:

13 Example use of CAMs Network Router Destination Address Next Hop Output Port xxx Xxxx xxxx 1 25 Example use of CAMs network routers Given a destination address, we want to find which way to send the packet The routing table as organized as shown We want to match the contents of the routing table entries to the destination address to find the direction in which to send the packet Addresses may be completely or partially specified - Don t cares are a concise way of representing many addresses - Saves space in the routing table Many other uses: - Processor TLBs - LSQs 26 13

14 10T CAM Cell word bit bit_b match cell cell_b 27 Binary CAMs CAM can be designed as 10-Transistor cell Storage cell = 6-transistor SRAM Match line is precharged high When the Content in the cell doesn t match the data on the search lines, match line is discharged => no match 28 14

15 CAM architecture 29 CAM architecture When a line matches, we can output the address or location of that content When multiple entries match, output the first match Gives priority to earlier entries 30 15

16 Ternary CAM In many applications, we need to store Don t cares Three states: 0, 1, X Use two bits of actual storage to encode the three different values For example, use 01 = 0, 10 = 1, 00 = X 31 TCAM Cell Search bit 0/0 always yields a match 32 16

17 TCAM Precharge Match line high When stored data matches search line match line stays high Otherwise, match line pulled low 33 Persistent memory SRAM/DRAM lose memory when power is turned off More persistent memory needed for several applications Photos in a digital camera Bootable code or settings on circuits Flash memory used for these applications Memory persists across power on/off cycles Small size 34 17

18 Flash memory Charge stored on an isolated conductor called floating gate Charge has no path to dissipate The charge on the floating gate controls the current flowing between source and drain Tells if a 1 or 0 is in the cell To erase the cell, a reverse voltage is applied between the drain and the controlling gate Charge is dissipated i d through h tunneling 35 Flash Memory Cell (1) 36 18

19 Flash Memory Cell (2) Default state: 1 current flows between drain/source when a voltage is applied Can set to a binary 0 value via programming Cannot program back to 1 unless erasing it first Limitations Can be read/programming a byte/word at a time Can only be erased a block at a time Block Erasure (set all bits in the block to 1 ) Memory wear a finite number of program-erase cycles (~1million P/E cycles) 37 Flash Write (Programming) Hot-Electron Injection: increase transistor threshold voltage V T 38 19

20 Flash Read Programmed cell: conduct only with a high gate voltage 39 Flash Erase Tunneling: bring back transistor threshold voltage V T 40 20

21 Flash Organization NAND: Memory cards: USB flash drives, solid-state drives Optimized for higher density (smaller area) Read/program in small blocks Read operation: Selected cell: WL voltage < threshold voltage of programming cell (conduct if not programmed) Pass cells: WL voltage >threshold voltage of programmed cell (always conduct) NOR: Rewriteable ROM: to replace EPROM/EEPROM Optimized to facility random access (larger area) Read slightly faster than NAND NAND: V Write/erase slower than NAND T with programming can be <0 41 Memory organizations 42 21

22 43 Wide Memory Organization Memory is slow compared to processor There is normally locality in memory accesses If you access location A, likely to access A+1, A+2 Why not access multiple words at a time to reduce access times What do we do with the extra words? (hint: caches!) Word 0 Word 1 Word 2 Word 3 Address bus 28 Data bus

23 Interleaved Memory Organization Organize memory into banks Each bank can be separately e accessed Data can be distributed across multiple banks Increase parallelism Address Bus Data Bus 45 Interleaved Memory Organization Can keep multiple banks busy at the same time Give address to first bank, then a different address to second bank so on Data accesses will be in different stages in different banks Somewhat like a pipeline Caveats? Consider 4-bank memory with each bank organized as 2-word wide 3 bits a 2 a 1 a 0 needed to address the 2-words (8 bytes) Each bank is addressed by the same a 4 a 3 bits. Bank 0 will have a 4 a 3 = 00, bank 1 will have a 4 a 3 =

24 Interleaved Memory Organization Can function as a wide-word access if we give the consecutive addresses to different banks Can also access different words from different banks that are not consecutive As long as there are no bank conflicts Flash memories/drives have wide bank organizations An example drive: with 2048 banks with each bank holding 512-byte sector Access 1MB memory fast Random access slow 47 24