Flash Memories. Ramin Roosta Dept. of Computer Engineering. EE 595 EDA / ASIC Design Lab

Transcription

1 Flash Memories Ramin Roosta Dept. of Computer Engineering EE 595 EDA / ASIC Design Lab

2 Content Non-volatile memories Flash applications Industry standards Architectures Main reliability issues New cells and architectures Conclusion

3 Non-Volatile Memories Solid-state memory devices that retain information once the power is switched off are: ROM (Read Only Memory) PROM (Programmable ROM) EPROM (Electrically Programmable ROM) EEPROM (Electrically Erasable PROM) Flash

4 Non-Volatile Memory Applications

5 Flash Memory Applications EPROM-like telecom (cellular phones), automotive, hard disk drives, printers, set-top box, PC BIOS, etc. Mass-storage miniature cards, multimedia palm top

6 Applications Computers & Hand-Helds PC BIOS, local storage of OSs and applications, storage of critical system information Hard disk drive controllers Personal organizers (PDAs) Portable PCs, smart phones and scanners Rugged, non-volatile storage for code and data in pricesensitive, space-constrained products, with capacity for flexible code change

7 Applications Set-Top Box and Embedded Digital TV, internet terminals, digital broadcast equipment, integrated receiver/decoders Re-write-able storage for system and applications code, graphical user interface, and applets Bar-code scanners, POS terminals, hard disk replacement, arcade games, consumer game consoles Integrated storage of boot code, application code, and/or data storage, added capacity for 3D games, insystem updates

8 Applications Networking & Telecom Routers, switches, net PCs, remote access servers Reliable network OS code storage (storage requirements double in size every two years) Base stations, PBX, phone systems, xdsl modems Reliable memory storage Increased capacity for increasingly complex application code and digital voice recording

9 Applications Mass Storage Digital still cameras, smart cards, MP3

10 Smart Cards Cost effective Small size Reliable

11 Device Trade-Offs Sector erase size Power supply requirements Read performance Program/Erase (P/E) performance P/E cycling performance Complexity of manufacturing process and device size (cost)

12 Main Features of Semiconductor Memories TYPE CAPACITY CELL AREA SPEED (random) WRITING CYCLES RETENTION VOLTAGE DRAM 16 M f ns > 1E14 VOLATILE + REFRESH 3.3V SRAM 4 M F ns > 1E14 VOLATILE 3.3V E 2 PROM 1 M F ns 1E6 > 10 YEARS 2.7-5V FLASH 16 M 7-10 F ns 1E5 > 10 YEARS 3-5V/12V 3-5Vonly EPROM 16 M 9 F ns 1-10 > 30 YEARS 3-5V/12V ROM 16 M - 32 M 7 F ns 0 NO LIMIT 3-5V

13 New Challenges Embedded in multi-media systems ; fast access time low voltage endurance low cost Solid state recorders ; write speed and throughput endurance low bit-cost (can be multi-level)

14 Floating Gate Transistor The storage element is a device whose conductivity can be changed in a nondestructive way. This is a MOS transistor with a conductive element completely surrounded by dielectric. The threshold voltage can be altered by changing the amount of charge present between the channel and the gate (in the floating gate).

15 Floating Gate Transistor The storage element is a device whose conductivity can be changed in a nondestructive way. This is a MOS transistor with a conductive element completely surrounded by dielectric. The threshold voltage can be altered by changing the amount of charge present between the channel and the gate (in the floating gate).

16 Floating Gate Program & Erase PROGRAM Channel hot electron injection in the FG at the drain side ERASE Fowler- Nordheim tunnel through the tunnel oxide at the source side

17 Floating Gate NOR Array 0.25 µm Flash - 32MB 1.6V, Dual Bank, Page

18 Memory Array V T Distribution and Tunnel Oxide Defects Gaussian distribution of UV erased cells Wide and asymmetrical distribution after electrical erase, still Gaussian for over 99% of cells Dispersion of "normal" bits due to capacitive coefficient variations

19 Over-Erasing The erase mechanism is not self-stopping. V T can eventually assume negative values resulting in over-erased cells. Over-erasing is a cause of failure for NORtype memory arrays. Solution Erase algorithms Redundancy

20 Data Retention As with any non-volatile memory, Flash MUST retain data for 10 years. Causes of charge loss defects in tunnel oxide defects in inter-poly dielectric mobile ion contamination Tunnel oxide SCALING! Process control problems

21 NOR Array Layout single cell and array

22 The erase function is performed by applying high voltages to the word lines and grounding the source line, leaving the bit lines floating. All the cells that are connected to the diffused source line are erased. This is the sector size. Programming/Erasing Programming of a single bit or cell is performed by applying a high voltage to the whole word line, a high voltage to the whole bit line, and grounding the source. Only the devices with high word line and high bit line are programmed. Devices on the same row, or word line, are stressed. Also devices on the same column, or bit line, are stressed.

23 AMG Array Architecture and Layout Selection 1WL - 1SEL - 2BL Metal pitch is very relaxed - 4l

24 AND Array Common ground terminal High metal BL density Sharing global BL1 adds complexity

25 NAND Array Mass Storage Compact Complex coding Longer read

26 Multi-Level Flash Memory Tight V T distribution Less margin between levels No specific multi-level failure mechanism Every failure mode already seen must be carefully tested Array disturbances

27 Flash Evolution

28 NOR Flash Cell Evolution

29 New Cells and Architectures New cells, based primarily on the floatinggate concept, plus other new concepts, are becoming available, for example, -cell and NROM charge-trapping devices. New architectures. Designers attempt to meet specific requirements by improving reliability, scalability, and performance.

30 Technology Roadmap

31 Concluding Remarks There are many new applications for Flash technology in the world of electronics. All NVMs are based on the Floating Gate concept: Technology double poly CMOS with very thin dielectrics Physics hot carrier, FN Tunneling Reliability endurance, retention Each application imposes specific reliability constraints.

32 References P. Pavan, R. Bez, P. Olivo, E. Zanoni, "Flash Memory Cells - An Overview", Proceedings of IEEE, Vol. 85, N. 8, pp , Aug B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H.E. Maes, D. Montanari, A. Modelli, "Nonvolatile Multilevel Memories for Digital Applications", Proceedings of IEEE, Vol. 86, N. 12, pp , Dec Flash Memories, P. Cappelletti, C. Golla, P. Olivo, E. Zanoni Editors, Kluwer Academic Press, Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices, W.D. Brown, J.E. Brewer Editors, IEEE Press, A.K. Sharma, Semiconductor Memories, IEEE Press, 1997.