Clock Distribution Overview

Transcription

1 Clock Distribution Overview CONTENTS Buffers LVCMOS Buffers LVDS Buffers Buffers HCSL s Universal s LVCMOS Zero Delay Buffers HCSL Zero Delay Buffers Multiplexers LVCMOS Multiplexers LVDS Multiplexers Multiplexers HCSL Multiplexers Clock Dividers With a product portfolio 0 times greater and broader than any other, IDT is the world s leader in silicon timing and is in a unique position to address the needs of virtually any application. With the industry s largest market share, IDT is the only one-stop-shop for timing, offering products from full-featured system solutions to simple clock building-block devices. Factory-programmable options and clock solution customization capabilities address unique customer requirements, while the lowest jitter and lowest power features set IDT apart from the competition. Products are accompanied by a world-class support team driven by service and responsiveness goals. The products in this guide represent a portion of IDT s timing portfolio. For more information about IDT s comprehensive portfolio of timing products or to request samples, please visit: idt.com/go/timing IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION

2 Clock Distribution FANOUT BUFFERS are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. The clock fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Single output buffers are useful for translating a clock from one signaling standard to another (e.g. LVCMOS-in to -out). Some devices have an integrated crystal oscillator, requiring only a low cost external fundamental-mode quartz crystal. The integrated oscillator provides an extremely low phase noise reference clock to drive jitter sensitive devices such as the clock inputs of PHYs. ZERO DELAY BUFFERS are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization. LVCMOS Buffers CLKIN Y0 Y 5PBxx -.8V to 3.3V LVCMOS High Performance Clock Buffer High performance :2, :4, :6, :8, :0 LVCMOS clock buffer Very low pin-to-pin skew <50 ps Y2 Very low additive jitter <50 fs Supply voltage:.8 V to 3.3 V Y3 Packaged in 8-, 4-,6-, 20-TSSOP and small DFN and QFN packages Q0 SEL[:0] Q G Yn 8L300 Crystal or Differential to LVCMOS/LVTTL Clock Buffer Up to 0 outputs Dual reference inputs or crystal input power supply modes of 3.3, 2.5,.8 or.5 volts Low output skew, 63 ps (typical) Low additive phase jitter, 22 fs (typical) 5 x 5 mm 32-VFQFN package CLK0 nclk0 CLK nclk XTAL_OUT XTAL_IN OE Pullup Pullup/ OSC 00 0 x SYNC Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 5PB02.8V to 3.3V :2 LVCMOS High-Performance Clock Buffer s Additive Phase Jitter Typ RMS , 2.5, FCT38072S Low to 2 Clock Buffer , 2.5, P03 Programmable , 2.5, S Low to 4 Clock Buffer , 2.5, S Low to 4 Clock Buffer , 2.5, S Low to 4 Clock Buffer , 2.5, PB04.8V to 3.3V :4 LVCMOS High-Performance Clock Buffer , 2.5, S Low to 4 Clock Buffer , 2.5, S Low to 4 Clock Buffer , 2.5, CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

3 Clock Distribution LVCMOS Buffers, continued s Additive Phase Jitter Typ RMS 74FCT38074S Low to 4 Clock Buffer , 2.5, FCT38075S Low to 5 Clock Buffer , 2.5, i 8L30205 Low, -to-4, Multiplexed Differential / LVCMOS-to-LVCMOS / LVTTL Crystal or Differential to LVCMOS/LVTTL Clock Buffer , 2.5, , 2.5,.8, P05 Programmable , 2.5, PB06 5PB i 8L300 8L3020 8L300 5PB0.8V to 3.3V :6 LVCMOS High-Performance Clock Buffer.8V to 3.3V :8 LVCMOS High-Performance Clock Buffer Low, -to-8 Differential / LVCMOS-to-LVCMOS Crystal or Differential to LVCMOS/LVTTL Clock Buffer Crystal or Differential to LVCMOS/LVTTL Clock Buffer Crystal or Differential to LVCMOS/LVTTL Clock Buffer.8V to 3.3V :0 LVCMOS High-Performance Clock Buffer , 2.5, , 2.5, , , 2.5,.8, , 2.5,.8, , 2.5,.8, , 2.5, FCT3807S Low to 0 Clock Buffer , 2.5, Di 8398i Low, -to-6 LVCMOS / LVTTL Low,-to-8 -to-lvcmos/ LVTTL Low,:8 Crystal-to-LVCMOS/ LVTTL , , , 2.5, LVDS Buffers PCLK npclk V DD Q0 nq0 Q nq 8P34S02i - :2 LVDS.8V Two low skew, low additive jitter LVDS output pairs One differential clock input pair Differential PCLK, npclk pair can accept the following differential input levels: LVDS,, CML Maximum input clock frequency:.2 GHz Low additive RMS phase jitter < 42 fs (typical) 3 x 3 mm 6-VFQFN package Continued next page IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 3

4 Clock Distribution LVDS Buffers, continued PCLK npclk V DD Q0 nq0 Q nq Q2 nq2 Q3 nq3 Q4 8P34S06i - :6 LVDS.8V Six low skew, low additive jitter LVDS output pairs One differential clock input pair Differential PCLK, npclk pair can accept the following differential input levels: LVDS,, CML Maximum input clock frequency:.2 GHz (maximum), design target Low additive RMS phase jitter <39 fs (typical) 4 x 4 mm 20-VFQFN package nq4 Q5 nq5 s Additive Phase Jitter Typ RMS 8P34S02i :2 LVDS.8V , LVDS, CML P03 Programmable LVCMOS,, LVDS, HCSL, Crystal.8, 2.5, SLVD204i 2:4, LVDS LVDS, SLVD202i 8P34S204i Dual :2, LVDS :4 LVDS.8V LVDS, LVDS,, CML SLVD :4, LVDS LVDS, P05 Programmable LVCMOS,, LVDS, HCSL, Crystal.8, 2.5, P34S06i :6 LVDS.8V , LVDS, CML SLVD208i 2:8, LVDS LVDS, SLVD :8, LVDS LVDS, SLVD204 8P34S208i Dual :4, LVDS Fanout Buffer :8 LVDS.8V LVDS, LVDS,, CML T39S0i Crystal or Differential to Differential Clock Crystal,, LVDS, HCSL 2.5, T39S Crystal or Differential to Differential Clock LVDS,, HCSL, HSTL, LVCMOS 2.5, SLVD22 :2, LVDS LVDS,, CML P34S22i :2 LVDS.8V LVDS,, CML T34936 :6 LVDS Clock , HCSL, HSTL, LVTTL CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

5 Clock Distribution Buffers PCLKA npclka V DD QA0 nqa0 QA nqa QA2 nqa2 8SLVP04i - Low Phase Noise, -to-4, 3.3V, 2.5V Four low skew, low additive jitter differential output pairs Differential input pair can accep the following differential input levels: LVDS,, CML Differential PCLKx pairs can also accept single-ended LVCMOS levels. LVCMOS interface levels for the control input (input select) PCLK npclk V DD Q0 nq0 Q nq Q2 nq2 Q3 nq3 A QA7 nqa7 Low additive RMS phase jitter <40 fs max 3 x 3 mm 6-VFQFN QB0 8SLVP208i - Dual :8, 3.3V, 2.5V PCLKB npclkb V DD nqb0 QB nqb QB2 nqb2 Two :8, low skew, low additive jitter fanout buffers Two differential clock inputs Differential PCLKA, npclka and PCLKB, npclkb pairs can accept the following differential input levels: LVDS,, CML Differential PCLKA, npclka and PCLKB, npclkb pairs can also accept single-ended LVCMOS levels. B QB7 nqb7 Maximum input clock frequency: 2 GHz Low additive RMS phase jitter <54 fs (maximum) 7 x 7 mm 48-VFQFN package s Banks Additive Phase Jitter Typ RMS 8SLVP02i :2, CML, LVDS, 2.5, S0Bi Low, -to-2, Differential-to-2.5V, 3.3V /ECL CML, LVDS,, SSTL 2.5, S0Ci Low, -to-2, Differential-to-2.5V, 3.3V /ECL CML, LVDS,, SSTL 2.5, P03 Programmable LVCMOS,, LVDS, HCSL, Crystal.8, 2.5, SLVP04i 8SLVP202i Low Phase Noise, -to-4, 3.3V, 2.5V Dual :2, 3.3V, 2.5V CML, LVDS, 2.5, CML, LVDS, 2 2.5, S8983i Differential -to-/ecl CML, LVDS,, SSTL Continued next page IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 5

6 Clock Distribution Buffers, continued s Banks Additive Phase Jitter Typ RMS 8SLVP204i 2:4, LVDS,, CML 2.5, P05 Programmable LVCMOS,, LVDS, HCSL, Crystal.8, 2.5, S006i Low, -to-6, Differential-to-2.5V, 3.3V /ECL CML, LVDS, 2.5, S03i Low,Dual, -to-3, Differential-to-2.5V, 3.3V /ECL CML, LVDS,, SSTL 2 2.5, SLVP204i Dual :4, 3.3V, 2.5V CML, LVDS, 2 2.5, S30i Low, -to-8 Differential-to-3.3V /ECL , LVDS, CML, SSTL 3.0V to 3.8V SLVP208i 2:8, LVDS,, CML 2.5, T53Si 8T33FS6 :0 Low 2.5V/3.3V Differential / HSTL LVDS, 2.5, , HSTL 2.5, T39S0i Crystal or Differential to Differential Clock Crystal,, LVDS, HCSL 2 2.5, T39S 853S2i 8SLVP206i 8T33FS6222 8SLVP208i Crystal or Differential to Differential Clock Fanout Buffer Low,-to-2, Differential-to-3.3V, 2.5V Dual :6, 3.3V, 2.5V Low, :5 Differential PECL Clock Divider and Dual :8, 3.3V, 2.5V Xtal,, LVDS, HCSL, HSTL, LVCMOS 2 2.5, CML,, SSTL 2.5, LVDS, 2 2.5, , , i-0 Low, -to-6 Differential-to-3.3V , LVDS, LVHSTL, HCSL, SSTL T33FS622 Low :20 Differential PECL/HSTL Clock PECL, HSTL 2.5, CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

7 Clock Distribution HCSL s 9DBV094: 9-output.8 V PCIe Gen/2/3 with Zo = 00 Ω Additive phase jitter is <00 fs RMS for PCIe Gen3 Additive phase jitter is <300 fs RMS (2 k to 20 M) Push-pull LP-HCSL outputs with integrated terminations save 36 resistors compared to standard HCSL 56 mw typical power consumption eliminates thermal concerns MHz to 200 MHz operating frequency supports other interfaces such as Ethernet Space-saving 6 x 6 mm VFQFPN-48 s Diff. Signaling Diff. Supply Supply Supply 9DBU054 9DBV054 9DBU074 9DBV074 9DBU094 9DBV094 5-output.5 V PCIe Gen/2/3 5-output.8 V PCIe Gen/2/3 7-output.5 V PCIe Gen/2/3 7-output.8 V PCIe Gen/2/3 9-output.5 V PCIe Gen/2/3 9-output.8 V PCIe Gen/2/3 5 LP-HCSL -67 HCSL LP-HCSL -200 HCSL LP-HCSL -67 HCSL LP-HCSL -200 HCSL LP-HCSL -67 HCSL LP-HCSL -200 HCSL Universal Buffers SMODEA[:0] 8T39S - Crystal or Differential to Differential Clock QA0 nqa0 0 total outputs with 2 banks (5 outputs each) REF_SEL[:0] CLK0 nclk0 CLK nclk 00 0 QA nqa QA2 nqa2 QA3 nqa3 QA4 nqa4 QB0 nqb0 Dual reference inputs or crystal input Selectable output levels:, LVDS, HCSL and LVCMOS Up to 2 GHz operation for and LVDS outputs XTAL_IN XTAL_OUT OSC 0/ QB nqb QB2 nqb2 Low output skew, 80 ps max SMODEB[:0] OE_SE SYNC QB3 nqb3 QB4 nqb4 REFOUT Low additive phase jitter, 34.7 fs (typical) 7 x 7 mm 48-VFQFN package Product Title s Type Freq Input Freq Input Type Core Additive Phase Jitter Typ RMS 5P03 Programmable Fanout Buffer 3 HCSL, LVCMOS, LVDS, Crystal, HCSL, LVCMOS, LVDS,.8, 2.5, 3.3.8, 2.5, P05 Programmable Fanout Buffer 5 HCSL, LVCMOS, LVDS, Crystal, HCSL, LVCMOS, LVDS,.8, 2.5, 3.3.8, 2.5, T39S0i Crystal or Differential to Differential Clock HCSL, LVCMOS, LVDS, Crystal, HCSL, LVDS, 2.5, , T39S Crystal or Differential to Differential Clock 0 HCSL, LVCMOS, LVDS, Xtal,, LVDS, HCSL, HSTL, LVCMOS 2.5, , IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 7

8 Clock Distribution LVCMOS Zero Delay Buffers 6 FRK 2 REF 2 S2 S 8 9 PLL Control Logic CLKA CLKA2 CLKA3 CLKA4 CLKB CLKB2 CLKB3 2308B - 3.3V Zero Delay Clock Multiplier Phase-lock loop clock distribution for applications ranging from 0 MHz to 33 MHz operating frequency Distributes one clock input to two banks of four outputs Separate output enable for each output bank External feedback (FBK) pin is used to synchronize the outputs to the clock input 9.9 x 3.9 mm 6-SOIC and 5 x 4.4 mm 6-TSSOP packages CLKB4 PLL_SEL Pullup 87004i - :4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator CLK0 nclk0 CLK nclk CLK_SEL FB_IN SEL0 SEL0 SEL0 SEL0 MR Pullup/ Pullup/ 0 2, 4, 8, 6 32, 64, 28 PLL 8:, 4:, 2:, : :2, :4, :8 0 Q0 Q Q2 Q3 Four LVCMOS/LVTTL outputs, 7 Ω typical output impedance Selectable CLK0/nCLK0 or CLK/nCLK clock inputs CLKx/nCLKx pairs can accept the following differential input levels:, LVDS, LVHSTL, HCSL, SSTL Internal bias on nclk0 and nclk to support LVCMOS/LVTTL levels on CLK0 and CLK inputs frequency range: MHz to 250 MHz 7.8 x 4.4 mm 24-TSSOP package s Freq Banks Clock Slicer User Configurable Zero Delay Buffer LVCMOS Multiplier and Zero Delay Buffer LVCMOS 3.3, 5 57 Low Phase Noise Zero Delay Buffer LVCMOS 2 3.3, Low Phase Noise Zero Delay Buffer LVCMOS 2 3.3, Low Phase Noise Zero Delay Buffer LVCMOS 2 3.3, :2, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator HCSL, HSTL, LVDS,, SSTL 2.5, :2 LVCMOS/LVTTL-to-LVCMOS / LVTTL Zero Delay Buffer For Audio LVCMOS Zero Delay, Low Buffer LVCMOS 3.3, i MHZ TO 62.5 MHZ, :4 LVCMOS/LVTTL Zero Delay Buffer MHz to 62.5 MHz, :4 LVCMOS/ LVTTL Zero Delay Buffer LVCMOS 2.5, LVCMOS 2.5, 3.3 Continued next page 8 CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

9 Clock Distribution LVCMOS Zero Delay Buffers, continued s Freq Banks 87004i :4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator HCSL, HSTL, LVDS,, SSTL 2.5, B 3.3V Zero Delay Clock Multiplexer LVCMOS i Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator HCSL, HSTL, LVCMOS, LVDS,, SSTL 2.5, i-47 Low, -to-2 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer Crystal, LVCMOS i-47 Low, -to-2 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer HCSL, HSTL, LVCMOS, LVDS,, SSTL HCSL Zero Delay Buffers voe(7:0)# 8 9DBV084.8V 8-output PCIe Gen /2/3 Zero Delay/Fan out Buffer CLK_IN CLK_IN# vsadr v v vhibw_bypm_lobw# CKPWRGD_PD# SDATA_3.3 SCLK_3.3 Control Logic SS-Compatible PLL DIF 7 DIF 6 DIF 5 DIF 4 DIF 3 DIF 2 DIF DIF 0 Additive phase jitter is 00 fs rms typical for PCIe Gen3 (bypass mode) Additive phase jitter is 250 fs rms typical (2 k-20 M, bypass mode) MHz to 200 MHz operating frequency (bypass mode) Direct connection to 00 transmission lines; saves 32 resistors compared to standard HCSL outputs 64 mw (typical) power consumption eliminates thermal concerns 6 x 6 mm 48-VFQFPN 9DBU024 9DBV i 9DBU043 9DBU044 2-output.5 V PCIe Gen /2/3 Zero Delay / 2-output.8 V PCIe Gen /2/3 Zero Delay / FemtoClock Zero Delay Buffer/Clock Generator for PCIe and Ethernet 4-output.5 V PCIe Gen /2/3 Zero Delay / 4-output.5 V PCIe Gen /2/3 Zero Delay / s Type Freq Supply Supply 2 LP-HCSL -67 HCSL LP-HCSL -200 HCSL HCSL , LVDS, M-LVDS, LVHSTL, HCSL LP-HCSL -67 HCSL LP-HCSL -67 HCSL.5.5 Continued next page IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 9

10 Clock Distribution HCSL Zero Delay Buffers, continued 9DBV044 9ZXL065 9DBU063 9DBU064 9DBV064 4-output.8 V PCIe Gen /2/3 Zero Delay / DB600ZL Derivative with Zo = 85 Ω 6-output.5 V PCIe Gen /2/3 Zero Delay / 6-output.5 V PCIe Gen /2/3 Zero Delay / 6-output.8 V PCIe Gen /2/3 Zero Delay / s Type Freq Supply Supply 4 LP-HCSL HCSL LP-HCSL HCSL LP-HCSL 0-67 HCSL LP-HCSL -67 HCSL LP-HCSL HCSL ZXL083 DB800ZL 8 LP-HCSL HCSL ZXL i 9DBU084 9DBV084 DB200ZL Derivative with Zo = 85 Ω FemtoClock Zero Delay Buffer/Clock Generator for PCIe and Ethernet 8-output.5 V PCIe Gen /2/3 Zero Delay / 8-output.8 V PCIe Gen /2/3 Zero Delay / 8 LP-HCSL HCSL HCSL , LVDS, M-LVDS, LVHSTL, HCSL LP-HCSL 0-67 HCSL LP-HCSL HCSL ZX DB200Z Derivative 2 HCSL HCSL ZX DB200Z Compliant Buffer 2 HCSL HCSL ZXL23 2- DB200ZL 2 LP-HCSL HCSL ZML232 2:2 DB200ZL Derivative 2 LP-HCSL HCSL ZX DB900Z Derivative 5 HCSL HCSL ZXL530 9ZXL550 9ZX290 9ZXL930 9ZXL DB900Z Low-Power Derivative 5- DB900Z Low-Power Derivative 9- DB900Z Compliant Buffer 9- DB900Z Low-Power Derivative 9- DB900Z Low-Power Derivative 5 LP-HCSL HCSL LP-HCSL HCSL HCSL HCSL LP-HCSL HCSL LP-HCSL HCSL CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

11 Clock Distribution IDT MULTIPLEXERS allow the selection from multiple clock inputs to drive the output. Devices are available with fanout capability, providing multiple copies of the output signal. Some devices have integrated crystal oscillators, requiring only low cost external fundamental-mode quartz crystals. The integrated oscillators provide an extremely low phase noise reference clock to drive jitter sensitive devices such as the clock inputs of PHYs. Others are available that can translate the input clock from one signaling level to another (e.g. LVCMOS-in to -out). Many of IDT s multiplexers feature fully differential internal architecture, even devices with single ended I/Os. This improves jitter due to inherent common-mode noise rejection and improves output skew. The differential circuitry is constant current and therefore injects less noise into system power supplies than single-ended solutions, reducing noise and decreasing EMI compliance concerns. LVCMOS Multiplexers CLK i- 4: Single-Ended Multiplexer 4: single-ended multiplexer CLK CLK2 Q nominal output impedance: 7 Ω (VDDO = 3.3 V) Maximum output frequency: 250 MHz CLK3 Q Propagation delay: 3 ns (maximum), VDD = VDDO = 3.3 V CLK4 Additive RMS phase jitter: 40 fs typical CLK5 4.4 x 5.0 mm 6-TSSOP CLK0 CLK6 CLK7 SEL2 SEL SEL0 OE 83058i - 8: Single-Ended Multiplexer 8: single-ended multiplexer Q nominal output impedance: 7 Ω (VDDO = 3.3 V) Maximum output frequency: 250 MHz Propagation delay: 3 ns (maximum), VDD = VDDO = 3.3 V CLK CLK2 CLK3 SEL SEL0 Q Additive RMS phase jitter: 40 fs (typical) 4.4 x 5 mm 6-TSSOP OE s Input Type Core Additive Phase Jitter Typ RMS 83054i 4: Single-Ended Multiplexer LVCMOS 2.5, 3.3.8, 2.5, i 6: Single-Ended Multiplexer LVCMOS 2.5, 3.3.8, 2.5, i 8: Single-Ended Multiplexer LVCMOS 2.5, 3.3.8, 2.5, S20i 2: Single-Ended Multiplexer LVCMOS 2.5, , S60i 6: Single-Ended Multiplexer LVCMOS 2.5, , S208 Differential-to-LVCMOS/ LVTTL with Divider and Glitchless Switch HCSL, HSTL, LVDS,, SSTL 2.5, , IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION

12 Clock Distribution LVDS Multiplexers OEA CLK_SEL0 CLK_SEL Pullup 859S0424i - 4:4 Differential-to-/LVDS Clock Multiplexer High speed 4: differential multiplexer with a :4 fanout buffer Four programmable differential or LVDS output pairs Four selectable differential PCLKx, npclkx input pairs PCLK0 npclk0 PCLK npclk PCLK2 npclk2 PCLK3 npclk3 Pullup/ Pullup/ Pullup/ Pullup/ QA0 nqa0 QA nqa QB0 nqb0 QB nqb PCLKx, npclkx pairs can accept the following differential input levels:, LVDS, CML Maximum output frequency: 3 GHz 4.4 x 7.8 mm 24-TSSOP package 8SLVD204-33i - 2:4, LVDS, 3.3 V Four low skew, low additive jitter LVDS output pairs Two selectable differential clock input pairs PCLK0 npclk0 PCLK npclk Pullup/ Pullup/ VDO GND GND VDO 0 Q0 nq0 Q nq Q2 nq2 OEB SEL_OUT Pullup Pullup Differential PCLKx, npclkx pairs can accept the following differential input levels: LVDS, Maximum input clock frequency: 2 GHz SEL Pullup/ GND GND VDO Q3 nq3 Low additive RMS phase jitter: 00 fs (maximum) GND 3 x 3 mm 6-VFQFN package Generator s Additive Phase Jitter Typ RMS 854S0i 2: Differential-to-LVDS Multiplexer , LVDS S054i 854S057Bi 854S058i 859S022i 859S042i 859S0424i 4: Differential-to-LVDS Clock Multiplexer 4: Or 2: LVDS Clock Multiplexer with Internal Input Termination 8: Differential-to-LVDS Clock Multiplexer 2:2 Differential-to-/LVDS Clock Multiplexer 4:2 Differential-to-/LVDS Clock Multiplexer 4:4 Differential-to-/LVDS Clock Multiplexer , LVDS, CML CML, LVDS,, SSTL LVDS,, SSTL CML, LVDS,, SSTL CML, LVDS,, SSTL 2.5, , CML, LVDS, 2.5, P34S204i :4 LVDS.8V , LVDS, CML SLVD204-33i 2:4, LVDS, 3.3 V , LVDS SLVD204i 2:4, LVDS, 2.5V , LVDS S208i Differential-to-LVDS with Divider and Glitchless Switch HCSL, LVDS, 2.5, P34S208i :8 LVDS.8V , LVDS, CML SLVD208-33i :8, LVDS , LVDS SLVD208i :8, LVDS , LVDS P34S22i :2 LVDS.8V , LVDS, CML SLVD22 :2, LVDS , LVDS, CML CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

13 Clock Distribution Multiplexers 853S02i - 2: Differential-to-3.3V, 2.5V Clock/Data Multiplexer CLK0 nclk0 CLK nclk CLK2 nclk2 CLK3 nclk3 CLK nclk SEL [3:0] Pullup/ Pullup/ Pullup/ Pullup/ Pullup/ Q nq High speed 2: differential multiplexer One differential 3.3V or 2.5V output Twelve selectable differential clock or data inputs CLKx, nclkx pairs can accept the following differential input levels:, LVDS, CML Additive RMS phase jitter: 0.44 ps (typical) 5 x 5 mm 32-VFQFN package 8SLVP22i - 2:2, 3.3V, 2.5V Twelve low skew, low additive jitter outputs Two selectable, differential clock inputs Differential pairs can accept the following differential input levels: LVDS,, CML Maximum input clock frequency: 2 GHz Low additive RMS phase jitter: <50 fs (typical) 6 x 6 mm 40-VFQFN package PCLK0 npclk0 PCLK npclk SEL V DD V DD f REF Q0 nq0 Q nq Q2 nq2 Q3 nq3 Q4 nq4 Q5 nq5 Q6 nq6 Q7 nq7 Q8 nq8 Q9 nq9 Q0 nq0 Q nq s Additive Phase Jitter Typ RMS 853S02i 2: Differential-to-3.3V, 2.5V Clock/Data Multiplexer CML, LVDS, 2.5, S0i 2: Differential-to- Multiplexer LVDS, 2.5, S058i 853S057i 85356i 853S54i 8S89834i 8: Differential-to-3.3V or 2.5V / ECL Clock Multiplexer 4:, Differential-To-3.3V, 2.5V / ECL Clock Multiplexer 2: Differential-to-3.3V Dual / ECL Clock Multiplexer Dual 2:, :2 Differential-to-/ECL Multiplexer Low, 2-to-4 LVCMOS/LVT- TL-to-/ECL Clock Multiplexer LVDS,, SSTL 2.5, CML,LVDS,LVPE- CL,SSTL HCSL, HSTL, LVDS,, SSTL 2.5, LVDS, 2.5, LVCMOS 2.5, SLVP204i 2:4, CML, LVDS, 2.5, T33FS34i 853S04i 853S30i Low, -to-4 Differential-to-2.5V, 3.3V /ECL Low, -to-5 Differential-to-2.5V, 3.3V /ECL Low, -to-8 Differential-to-3.3V /ECL , ECL, HSTL 2.5, CML, LVDS,, SSTL CML, LVDS,, SSTL 2.5, SLVP208i 2:8, CML, LVDS, 2.5, SBi Low, -to-0 Differential-to-2.5V, 3.3V /ECL LVDS,, SSTL 2.5, SLVP22i 2:2, 3.3V, 2.5V CML, LVDS, 2.5, T33FS6222 Low, :5 Differential PECL Clock Divider and PECL 3.3, IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 3

14 Clock Distribution HCSL Multiplexers 9DMV04-2:.8 V PCIe Gen/2/3 Clock Multiplexer w/zo=00 W One low-power (LP) HCSL DIF pair integrated terminations Suitable for PCIe Gen/2/3 systems can be easily coupled to LVDS, and CML, see AN-89 < 00 fs RMS additive phase jitter for PCIe Gen3 5 mw (typ) power consumption Space-saving 3 x 3 mm 6-VFQFPN package; minimal board space SMODEA [:0] REF_SEL [:0] CLK0 nclk0 CLK nclk XTAL_IN XTAL_OUT IREF SMODEB [:0] OE_SE Pullup/ Pullup/ OSC SYNC QA0 nqa0 QA nqa QA2 nqa2 QA3 nqa3 QA4 nqa4 QB0 nqb0 QB nqb QB2 nqb2 QB3 nqb3 QB4 nqb4 REFOUT 8T39S0i - Crystal or Differential to Differential Clock Two differential reference clock input pairs Differential input pairs can accept the following differential input levels:, LVDS, HCSL Crystal oscillator interface Crystal input frequency range: 0 MHz to 40 MHz Additive RMS phase jitter: 53 fs (typical) 7 x 7 mm 48-VFQFN package s Additive Phase Jitter Typ RMS 5V4068A 2: PCIe Gen /2/3 Clock Multiplexer HCSL i Clock Switch for ATCA/AMC and PCIe Applications HCSL, LVDS, 2.5, i 2: Differential Clock/Data Multiplexer HCSL, LVDS, HSTL, i 4:2 Differential Clock/Data Multiplexer HCSL, LVDS, V4067A 2:4 PCIe Gen /2/3 Clock Multiplexer HCSL i 2:4 HCSL PCIe Clock Buffer , LVDS, HSTL, SSTL, HCSL T39S0i Crystal or Differential to Differential Clock Crystal, HCSL, LVDS, 3.3, DMU04 9DMV04 9DMU044 9DMV044 2:.5V PCIe Gen/2/3 Clock Multiplexer w/zo=00 W 2:.8V PCIe Gen/2/3 Clock Multiplexer w/zo=00 W 2:4.5V PCIe Gen/2/3 Clock Multiplexer w/zo=00 W 2:4.8V PCIe Gen/2/3 Clock Multiplexer w/zo=00 W HCSL HCSL HCSL HCSL T39S Crystal or Differential to Differential Clock Xtal,, LVDS, HCSL, HSTL, LVCMOS 2.5, CLOCK DISTRIBUTION INTEGRATED DEVICE TECHNOLOGY IDT

15 Clock Distribution CLOCK DIVIDERS provide an output clock signal that is a divided frequency of the input. They can also be used to provide signal buffering and make multiple copies of the output frequency. Clock divider devices, when used in divide-by- mode, can also function as a fanout buffer. Clock Dividers FSELA 8T33FS Low, :5 Differential PECL Clock Divider and CLK0 nclk0 CLK nclk CLK_SEL FSELB FSELC MR FSELD V CC V EE V CC V EE V EE V EE V EE V EE QA0 QA QB0 QB QB2 QC0 QC QC2 QC3 QD0 QD QD2 QD3 QD4 QD5 5 differential PECL outputs on 4 separate banks Selectable / or /2 frequency divider Operation to 2 GHz 2.5 V or 3.3 V supply 0 x 0 mm 52-TQFP package Dual-channel LVCMOS Clock Divider General purpose programmable divider Supports 673 PLL Building Block User determines the divide by setting input pins Pull-ups on all select inputs Operating voltage of 3.3 V or 5 V 6.2 x 0.0 mm 28-SSOP package INA INB A6:A0 7 Divider A (7-Bit) Divider B (9-Bit) 9 3 V DD 2 Post Divider 8 OUTA OUTB V EE V BB B8:B0 GND S2:S0 s Type Divider Value Additive Phase Jitter Typ RMS 8700I-0 LVCMOS/LVTTL Clock Divider LVCMOS LVCMOS 2.5, 3.3, 2, 3, 4, 5, 6, 8, 6 8S89874i :2 Differential-to- Buffer/Divider 2, ECL , 0-250, 0-625, , CML, LVDS, 2.5, 3.3, 2, 4, 8, S89875i Differential-to-LVDS Buffer/ Divider with InternalTermination 2 LVDS , 0-250, 0-625, , CML, LVDS, 2.5, 2, 4, 8, 6 5 8V74S4622 Clock / Divider 2 LVDS LVDS, 3.3 2, 4, 5, S89876i Differential-to-LVDS Buffer/ Divider with Internal Termination 2 LVDS CML, LVDS, 3.3, 2, 4, 8, PECL/CMOS to CMOS Clock Driver 2 LVCMOS 0-56 LVCMOS 3.3 2, 4, 6, 8, 2, Clock Divider 2 LVCMOS 0-200, LVCMOS 5, 2, 4, 5, 6, 7, 8, 0 8P73S674i Differential-to-.8V Clock Divider and , 0-500, 0-250, 0-25 LVDS,.8, 2, 4, V79S674 Differential-to-3.3V, 2.5V Clock Divider and , 0-500, 0-250, 0-25 LVDS, 2.5, 3.3, 2, 4, Dual-channel LVCMOS Clock Divider 4 LVCMOS LVCMOS, 3.3, 5, 2, 3, 4 8T73S208i Differential Clock Divider and LVDS,, CML 2.5, 3.3, 2, 4, T79S88I-08 -to-8 Differential to Universal Clock Divider/Fanout Buffer 8 Selectable LVDS, LVDS,, CML V to V through 6, T74S208i Differential LVDS Clock Divider and 8 LVDS LVDS,, CML 2.5, 2, 4, T33FS6222 Low, :5 Differential PECL Clock Divider and PECL 3.3, 2.5, i Low, -to-6 LVCMOS/ LVTTL Clock Generator 6 LVCMOS 0-250, LVDS, LVHSTL, SSTL, HCSL.8, 2.5, 3.3, 2 70 IDT INTEGRATED DEVICE TECHNOLOGY CLOCK DISTRIBUTION 5

16 Clock Distribution IDT is in a unique position to address the needs of virtually any application. IDT s industry-leading portfolio of timing devices consists of clock generators, buffers, dividers, multiplexers, crystal oscillators, and jitter attenuators with frequency translation many with programmable capabilities for maximum flexibility. Application-specific clock ICs address needs for RF timing and network synchronization, including JESD204B, synchronous Ethernet, IEEE 588, PDH, and SONET / SDH. Software, Tools and Services Complimentary Clock Tree Design and Review Services Our in-house experts can assist you in building a new clock tree from the ground up or evaluating and improving an existing clock tree design. Visit idt.com/go/timingservices to get started Timing Commander Software IDT s Timing Commander is an innovative Windows -based software platform enabling system design engineers to configure, program, and monitor sophisticated timing devices with an intuitive and flexible graphical user interface (GUI). The support tool empowers customers to expedite development cycles and optimize the configuration of IDT s industry-leading clocking solutions. Download software and resources: idt.com/go/timingcommander Evaluation Boards and Samples IDT offers evaluation boards for many of our advanced timing solutions. These evaluation boards help you evaluate the features and performance of selected products and system solutions that demonstrate optimized and tested solutions for your application design. IDT, the IDT Logo, FemtoClock and Timing Commander are registered trademarks or trademarks of Integrated Device Technology, Inc., in the United States and other countries. All other trademarks are the property of their respective owners Integrated Device Technology, Inc. All Rights Reserved. IDT INTEGRATED DEVICE TECHNOLOGY OV_CLOCKDISTRIBUTION_REVC_046 CLOCK DISTRIBUTION 6