GENERAL DESCRIPTION The is a LVCMOS/LVTTL clock generator. The has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs.

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1 Low Skew, -to-2 LVCMOS / LVTTL Clock Multiplier/Zero elay Buffer ata Sheet GENERAL ESCRIPTION The is a LVCMOS/LVTTL clock generator. The has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The is a highly fl exible device. The three selectable inputs ( differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to25mhz. The input frequency range is 5MHz to 2MHz. The also has a Q output which can by used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. Q then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications:. System Clock generator: Use a 6.66MHz reference clock to generate eight 33.33MHz copies for PCI and four MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 25MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero elay buffer for Synchronous memory: Fan out up to twelve MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. FEATURES Fully integrated PLL Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync Selectable LVCMOS/LVTTL or differential CLK, nclk inputs CLK, CLK can accept the following input levels: LVCMOS or LVTTL CLK, nclk pair can accept the following differential input levels: LVPECL, LVS, LVHSTL, SSTL, HCSL Output frequency range: 8.33MHz to 25MHz VCO range: 2MHz to 48MHz Output skew: 55ps (maximum) Cycle-to-cycle jitter: ±ps (typical) Full supply voltage -4 C to 85 C ambient operating temperature Available in lead-free RoHS compliant package Compatible with PowerPC and Pentium Microprocessors PIN ASSIGNMENT 25 Integrated evice Technology, Inc

2 BLOCK IAGRAM VCO_SEL PLL_SEL REF_SEL CLK nclk CLK CLK CLK_SEL EXT_FB PHASE ETECTOR LPF VCO Q QA QA QA2 QA3 Q QB QB QB2 FSEL_FB2 QB3 nmr/oe FSEL_A: FSEL_B: FSEL_C: FSEL_FB:2 POWER-ON RESET , 6, 8, 2 4, 6, 8, 2, 4, 6, 8 4, 6, 8, PULSE ATA GENERATOR 2 Q Q Q Q QC QC QC2 QC3 QFB Q _CLK _ATA OUTPUT ISABLE CIRCUITRY 2 INV_CLK 25 Integrated evice Technology, Inc 2

3 SIMPLIFIE BLOCK IAGRAM nmr/oe CLK nclk CLK CLK CLK_SEL REF_SEL EXT_FB PLL VCO RANGE 2MHz - 48MHz 2 FSEL_A[:] 2 FSEL_ A A QAx FSEL_B[:] 2 QA QA QA2 QA3 VCO_SEL PLL_SEL FSEL_ B B QBx FSEL_C[:] 2 QB QB QB2 QB3 FSEL_ C C QCx QC QC QC2 QC3 INV_CLK FSEL_FB[:2] 3 FSEL_ FB2 FB FB QFB QFB _CLK _ATA OUTPUT ISABLE CIRCUITRY Q 25 Integrated evice Technology, Inc 3

4 TABLE. PIN ESCRIPTIONS Number Name Type escription GNI Power Power supply ground. 2 nmr/oe Input Pullup Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs to tristate and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 _CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. 4 _ATA Input Pullup 5, 26, 27 FSEL_FB2, FSEL_FB, FSEL_FB Input Pullup Confi guration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Select pins control Feedback ivide value. LVCMOS / LVTTL interface levels. 6 PLL_SEL Input Pullup Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVC- MOS / LVTTL interface levels. 7 REF_SEL Input Pullup Selects between CLK or CLK and CLK, nclk inputs. When HIGH, selects CLK, nclk. When LOW, selects CLK or CLK. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. Selects between CLK and CLK as phase detector reference. When LOW, selects CLK. When HIGH, selects CLK. LVCMOS / LVTTL interface levels. 9, CLK,CLK Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. CLK Input Pullup Non-inverting differential clock input. 2 nclk Input Pullup/ Pulldown Inverting differential clock input. V /2 default when left fl oating. 3 V A Power Analog supply pin. 4 INV_CLK Input Pullup 5, 24, 3, 35, 39, 47, 5 6, 8, 2, 23 7, 22, 33, 37, 45, 49 9, 2 GNO Power Power supply ground. QC3, QC2, QC, QC Output V O Power Output supply pins. FSEL_C, FSEL_C Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Input Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. 25 Q Output Synchronization output for Bank A and Bank C. Refer to Figure, Timing iagrams. LVCMOS / LVTTL interface levels. 28 V Power Core supply pins. 29 QFB Output Feedback clock output. LVCMOS / LVTTL interface levels. 3 EXT_FB Input Pullup Extended feedback. LVCMOS / LVTTL interface levels. 32, 34, 36, 38 4, 4 42, 43 44, 46, 48, 5 QB3, QB2, QB, QB FSEL_B, FSEL_B FSEL_A, FSEL_A QA3, QA2, QA, QA Output Bank B clock outputs.7ω typical output impedance. LVCMOS / LVTTL interface levels. Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. Output 52 VCO_SEL Input Pullup Bank A clock outputs.7ω typical output impedance. LVCMOS / LVTTL interface levels. Selects VCO. When HIGH, selects VCO. When LOW, selects VCO 2. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values. 25 Integrated evice Technology, Inc 4

5 TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C IN Input Capacitance 4 pf R PULLUP / R PULLOWN Input Pullup/Pulldown Resistor 5 kw C P Power issipation Capacitance (per output) V, V A, V O = 3.465V 8 pf R OUT Output Impedance W TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs Inputs Outputs Inputs Outputs FSEL_A FSEL_A QA FSEL_B FSEL_B QB FSEL_C FSEL_C QC TABLE 3B. FEEBACK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs FSEL_FB2 FSEL_FB FSEL_FB QFB TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE Control Pin Logic Logic VCO_SEL VCO/2 VCO REF_SEL CLK or CLK CLK, nclk CLK_SEL CLK CLK PLL_SEL BYPASS PLL Enable PLL nmr/oe Master Reset/Output Hi Z Enable Outputs INV_CLK Non-Inverted QC2, QC3 Inverted QC2, QC3 25 Integrated evice Technology, Inc 5

6 fvco : MOE QA QC Q 2: MOE QA QC Q 3: MOE QC( 2) QA( 4) Q 3:2 MOE QC( 2) QA( 8) Q 4: MOE QC( 2) QA( 8) Q 4:3 MOE QA( 6) QC( 8) Q 6: MOE QA( 2) QC( 2) Q FIGURE. TIMING IAGRAMS 25 Integrated evice Technology, Inc 6

7 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V 4.6V Inputs, V I -.5V to V +.5 V Outputs, V O -.5V to V O +.5V Package Thermal Impedance, θ JA 42.3 C/W ( lfpm) Storage Temperature, T STG -65 C to 5 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the C Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY C CHARACTERISTICS, V = V A = V O = ±5%, TA = -4 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units V Core Supply Voltage V V A Analog Supply Voltage V V O Output Supply Voltage V I Power Supply Current All power pins 225 ma I A Analog Supply Current 2 ma NOTE: Special thermal handling may be required in some confi gurations. TABLE 4B. C CHARACTERISTICS, V = V A = V O = ±5%, TA = -4 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V V IL Input Low Voltage.8 V I IN Input Current ±2 µa V OH Output High Voltage I OH = -2mA 2.4 V V OL Output Low Voltage I OL = 2mA.5 V V PP Peak-to-Peak Input Voltage; NOTE, 2 CLK, nclk.3 V V CMR Common Mode Input Voltage; NOTE, 2 CLK, nclk V - 2V V -.6V V NOTE : Common mode voltage is defi ned as V IH. NOTE 2. For single ended applications, the maximum input voltage for CLK and nclk is V +.3V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V = V A = V O = ±5%, TA = -4 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units f IN CLK, CLK, Input Frequency CLK, nclk; NOTE 2 MHz _CLK 2 MHz NOTE : Input frequency depends on the feedback divide ratio to ensure clock * Feedback ivide is in the VCO range of 2MHz to 48MHz. 25 Integrated evice Technology, Inc 7

8 TABLE 6. AC CHARACTERISTICS, V = V A = V O = ±5%, TA = -4 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units fmax Output Frequency 2 25 MHz 4 2 MHz 6 8 MHz 8 6 MHz CLK ps Static Phase QFB 8 t(ø) Offset; CLK ps NOTE CLK, In Frequency = 5MHz ps nclk t sk(o) Output Skew; NOTE 2 55 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 4 ± ps f VCO PLL VCO Lock Range 2 48 MHz t LOCK PLL Lock Time; NOTE 3 ms t R / t F Output Rise/Fall Time; NOTE 3.8V to 2V.5.2 ns t PW Output Pulse Width t PERIO /2-75 t PERIO /2 ± 5 t PERIO / t PZL, t PZH Output Enable Time; NOTE 3 2 ns t PLZ, t PHZ Output isable TIme; NOTE ns NOTE : efi ned as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: efi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V O /2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defi ned in accordance with JEEC Standard 65. ps 25 Integrated evice Technology, Inc 8

9 PARAMETER MEASUREMENT INFORMATION OUTPUT LOA AC TEST CIRCUIT IFFERENTIAL INPUT LEVEL OUTPUT SKEW CYCLE-TO-CYCLE JITTER STATIC PHASE OFFSET (IFFERENTIAL) STATIC PHASE OFFSET (LVCMOS) OUTPUT RISE/FALL TIME t PW & t Period 25 Integrated evice Technology, Inc 9

10 APPLICATION INFORMATION USING THE OUTPUT FREEZE CIRCUITRY OVERVIEW To enable low power states within a system, each output of (Except QC and QFB) can be individually frozen (stopped in the logic state) using a simple serial interface to a 2 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the serial interface are FPGA s and ASICs. PROTOCOL The Serial interface consists of two pins, _ata (Freeze ata) and _CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 2 bit shift register. The sequence is started by supplying a logic start bit followed by 2NRZ freeze enable bits. The period of each _ATA bit equals the period of the _CLK signal. The _ATA serial transmission should be timed so the can sample each _ATA bit with the rising edge of the _CLK signal. To place an output in the freeze state, a logic must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 2 data bits are shifted into the shift register. When all 2 data bits are shifted in the register, the next rising edge of _CLK will enable or disable the outputs. If the bit that is following the 2th bit in the register is a logic, it is used for the start bit of the next cycle; otherwise, the device will wait and won t start the next cycle until it sees a logic bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state. 25 Integrated evice Technology, Inc

11 POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The providesseparate power supplies to isolate any high switching noise from the outputs to the internal PLL. V, V A, and V O should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a Ω resistor along with a μf and a.μf bypass capacitor should be connected to each V A pin. The Ω resistor can also be replaced by a ferrite bead. V V A.μF Ω.μF μf FIGURE 3. POWER SUPPLY FILTERING WIRING THE IFFERENTIAL INPUT TO ACCEPT SINGLE ENE LEVELS Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V /2 is generated by the bias resistors R, R2 and C. This bias circuit should be located as close as possible to the input pin. The ratio of R and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V =, V_REF should be.25v and R2/R =.69. FIGURE 4. SINGLE ENE SIGNAL RIVING IFFERENTIAL INPUT 25 Integrated evice Technology, Inc

12 IFFERENTIAL CLOCK INPUT INTERFACE The CLK /nclk accepts LVS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must mee t the VPP and VCMR input requirements. Figures 5A to 5 show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 5A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation..8v Zo = 5 Ohm Zo = 5 Ohm CLK CLK Zo = 5 Ohm Zo = 5 Ohm LVHSTL ICS HiPerClockS LVHSTL river R 5 R2 5 nclk HiPerClockS Input LVPECL R 5 R3 5 R2 5 nclk HiPerClockS Input FIGURE 5A. CLK/NCLK INPUT RIVEN BY LVHSTL RIVER FIGURE 5B. CLK/NCLK INPUT RIVEN BY LVPECL RIVER Zo = 5 Ohm R3 25 R4 25 CLK LVS_riv er Zo = 5 Ohm CLK LVPECL Zo = 5 Ohm nclk HiPerClockS Input Zo = 5 Ohm R nclk Receiver R 84 R2 84 FIGURE 5C. CLK/NCLK INPUT RIVEN BY LVPECL RIVER FIGURE 5. CLK/NCLK INPUT RIVEN BY LVS RIVER RECOMMENATIONS FOR UNUSE INPUT AN OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: LVCMOS OUTPUT: For applications not requiring the use of a clock input, it can be All unused LVCMOS output can be left fl oating. There should left fl oating. Though not required, but for additional protection, a be no trace attached. kω resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nclk can be left fl oating. Though not required, but for additional protection, a kω resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A kω resistor can be used. 25 Integrated evice Technology, Inc 2

13 RELIABILITY INFORMATION TABLE 7. θ JA VS. AIR FLOW TABLE θja by Velocity (Linear Feet per Minute) 2 5 Single-Layer PCB, JEEC Standard Test Boards 58. C/W 47. C/W 42. C/W Multi-Layer PCB, JEEC Standard Test Boards 42.3 C/W 36.4 C/W 34. C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for is: Integrated evice Technology, Inc 3

14 PACKAGE OUTLINE - Y SUFFIX FOR 52 LEA LQFP TABLE 8. PACKAGE IMENSIONS JEEC VARIATION ALL IMENSIONS IN MILLIMETERS BCC SYMBOL MINIMUM NOMINAL MAXIMUM N 52 A A A b c BASIC. BASIC E 2. BASIC E. BASIC e.65 BASIC L θ -- 7 ccc Reference ocument: JEEC Publication 95, MS Integrated evice Technology, Inc 4

15 TABLE 9. ORERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 87973YILF ICS87973YILF 52 Lead Lead-Free LQFP tray -4 C to 85 C 87973YILFT ICS87973YILF 52 Lead Lead-Free LQFP tape & reel -4 C to 85 C 25 Integrated evice Technology, Inc 5

16 REVISION HISTORY SHEET Rev Table Page escription of Change ate A T 4 Pin escription Table - added pins 2 and 2. 9/9/2 A 2 Block iagram - added missing dividers to the ata Generator. /8/2 B T4B 7 C Characteristics table - updated VCMR values from GN +.5V min., V max. to V - 2V min., V -.6V max. /23/2 T 4 Pin escription Table - corrected CLK Type to read Pullup from Pulldown. B T8 2 Revised Package rawing. Corrected Package imensions table to correspond /8/2 with the Package rawing. Added LVTTL to title. B 2//2 2 Corrected Package Outline to correspond with the Package imensions table. T2 5 Pin Characteristics - changed the C P limit from 25pF typical to 8pf max. T4A 7 Power Supply Table - changed the I limit from 25mA max. to 225mA max. C Application Information: 3/2/3 Added sections, Power Supply Filtering Techniques and Wiring the ifferential Level... 2 Added ifferential Clock Input Interface section. C 5/7/3 T4A 7 Power Supply Table - changed V A minimum from 3.35V to 2.935V. 6/27/3 T2 5 Pin Characteristics - changed C IN from 4pF max. to 4pF typical. Corrected Freeze ata labeling on Figure 2A. T T2 T T9 5 7 Pin Characteristics Table - added Pullup/Pulldown to pin 2, nclk. Pin Characteristics Table - added to R OUT 5Ω min. and 2Ω max. Features section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking and note. Updated datasheet s header/footer with IT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. T9 5 Ordering Information - removed leaded devices, quantity for tape & reel and LF suffi x note. Updated S header and footer. 7/9/3 5/9/6 8/5/ 2/7/5 25 Integrated evice Technology, Inc 6

17 Corporate Headquarters 624 Silver Creek Valley Road San Jose, CA 9538 USA Sales or Fax: Tech Support ISCLAIMER Integrated evice Technology, Inc. (IT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IT or any third parties. IT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IT product can be reasonably expected to signifi cantly affect the health or safety of users. Anyone using an IT product in such a manner does so at their own risk, absent an express, written agreement by IT. Integrated evice Technology, IT and the IT logo are trademarks or registered trademarks of IT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit Copyright 25 Integrated evice Technology, Inc. All rights reserved.