Keying of CompactPCI Boards and Backplanes

Transcription

1 Keying of CompactPCI Boards and Backplanes PICMG 2.10, Revision 1.0 October 1, 1999

2 Copyright 1999 PCI Industrial Computers Manufacturers Group (PICMG) The attention of adopters is directed to the possibility that compliance with or adoption of PICMG specifications may require use of an invention covered by patent rights. PICMG shall not be responsible for identifying patents for which a license may be required by any PICMG specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. It is beyond the scope of the this specification to ensure that all CompactPCI configurations will meet any applicable safety and telecom regulations and practices. Following the recommendations of this specification does not guarantee a safety regulatory compliant product and does not free manufacturers of this equipment from independently verifying that their equipment meets all applicable safety and telecom regulations and practices. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of CompactPCI equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG, CompactPCI, and the PICMG and CompactPCI logos are registered trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. ii

3 Contents TABLES... IV ILLUSTRATIONS...V 1 SCOPE APPLICABLE DOCUMENTS SPECIFICATION TERMINOLOGY BACKPLANE CONNECTOR KEYS DESCRIPTION OF KEYING MECHANISM PHILOSOPHY AND HISTORY OF ALLOCATION FRONT PANEL KEYS DESCRIPTION OF KEYING MECHANISM PHILOSOPHY AND HISTORY OF ALLOCATION HIERARCHICAL ALLOCATION OF COMPACTPCI FRONT PANEL KEYS KEY ASSIGNMENTS BACKPLANE CONNECTOR KEYS FRONT PANEL KEYS MINIMUM KEYING REQUIREMENTS Backplanes and Enclosures Boards APPLICABILITY TO APPROVED SPECIFICATIONS PICMG 2.0 CompactPCI Base SpecificationRevision 2.1 September 2, PICMG 2.2 VME64x Bus Pin Assignments on CompactPCI PICMG 2.5 CompactPCI Computer Telephony Specification ANTICIPATED IMPACT ON PROPOSED SPECIFICATIONS - ADVISORY PICMG 2.0 CompactPCI Base Specification, Draft PICMG 2.6 PCI-PCI Bridging for CompactPCI Backplanes PICMG 2.7 Dual CompactPCI Backplanes PICMG 2.8 Instrumentation Extensions to CompactPCI iii

4 Tables Table 5-1 Cavity D function Table 5-2 Cavity E Function Table 5-3 Cavity A Function Table 5-4 Cavity B Function Table 6-1 IEC Connector Key Utilization Table 6-2 IEEE keying assignments for 3U CompactPCI systems Table 6-3 IEEE keying assignments for 6U CompactPCI systems Table 6-4 IEEE key combinations on hybrid CompactPCI/VME64x systems Table 6-5 Keying Combinations for 6U boards as specified in PICMG Table 6-6 Additional Keying Combinations permitted in Computer Telephony Systems using features specified in PICMG Table 6-7 IEEE lower key combinations in 3U PXI systems Table 6-8 IEEE key combinations available for use in 6U PXI Systems iv

5 Illustrations Figure 4-1 Cavity number allocations in IEC connector keys Figure 4-2 Subset of IEC Connector Keys Figure 5-1IEEE Front Panel Keys v

6 vi

7 1. Scope 1 Scope Various PICMG Technical Subcommittees, among them the Telecommunications Interest Subcommittee (TISC) and the VME64x Subcommittee, have defined signal-topin assignments for the user-defined pins of the J4/P4 and the J5/P5 CompactPCI connectors. Specifications are also under development, which replicate the PCI bus on the J4/P4 and J5/P5 connectors. In addition, there is at least one specification under development, which might lead to future pin assignment conflicts on the J2/P2 connectors. These assignments for bussed signals will certainly overlap. The result will be risk of damage to equipment and in some cases hazard to persons operating the equipment. To safely support overlapping uses of CompactPCI s user-definable pins, use of the keying mechanisms defined in IEC for the J4/P4 connector and in IEEE for handle and cardguide hardware will be required. In the interest of providing a single reference document and to reduce the risk of duplicated use, assignment of these keys will be centrally administered by the PICMG Technical/Executive Committee. Page 7 of 7

8 1. Scope Page 8 of 8

9 2. Applicable Documents 2 Applicable Documents PICMG 2.0 CompactPCI (Base Specification) PICMG 2.2 VME64x Bus Pin Assignments on CompactPCI PICMG 2.5 CompactPCI Computer Telephony Specification PICMG 2.6 PCI-PCI Bridging for CompactPCI Backplanes PICMG 2.7 Dual CompactPCI Backplanes PICMG 2.8 CompactPCI Instrumentation Extensions VITA 1.1 VME64 Extensions IEC mm Hard Metric Connectors IEEE Std Additional Mechanical Specifications for Microcomputers Using the IEEE Equipment Practice IEEE Std Mechanical Rear Plug-in Units for Microcomputers Using the IEEE Equipment Practice Page 9 of 9

10 2. Applicable Documents Page 10 of 10

11 3. Specification Terminology 3 Specification Terminology This specification utilizes several reserved key words which are defined below: MAY: A key word indicating flexibility of choice with no implied preference. SHALL: A key word indicating a mandatory requirement. Designers SHALL implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification. SHOULD: A key word indicating flexibility of choice with a strongly preferred implementation. Page 11 of 11

12 3. Specification Terminology Page 12 of 12

13 4. Backplane Connector Keys 4 Backplane Connector Keys 4.1 Description of Keying Mechanism The Type A connector specified in IEC includes provisions for installation of a keying block having eight coding positions. When installed, this block is located in rows 12, 13, and 14 of the 25 row free and fixed connectors specified for J1/P1 and J4/P4. In any given keying block, four coding positions are filled with blocking pins and four are left open to receive pins from the mating keying block. This arrangement allows for 70 mutually exclusive mating pairs, all of which are summarized in Annex D of IEC Figure 4-1 shows the cavity numbers in the mating keying blocks. Male/Fixed Female/Free Figure 4-1 Cavity number allocations in IEC connector keys Page 13 of 13

14 4. Backplane Connector Keys Ten of these combinations have been tooled and are readily available from several major connector manufacturers. Figure 4-2 is a summary of these keys. Figure 4-2 Subset of IEC Connector Keys Page 14 of 14

15 4. Backplane Connector Keys 4.2 Philosophy and History of Allocation The connector keys are generally intended to prevent inadvertent installation of boards designed for one particular bus interconnect into backplane slots defined for another. Only J1/P1 and J4/P4 on the CompactPCI have these keys, and thus only these connectors are deemed to be protected by them. It is intended that a particular connector key will be uniquely associated with a particular use of the type A connector on which it is installed, regardless of the connector s position on the backplane. For example, these keying assignments will support the use of J4/P4 as a CompactPCI connector, or conversely, the use of J1/P1 as a VME64x connector. Ultimately, it is intended that seven of the 70 possible keying combinations will be identified as User Defined and the remainder, which are unassigned, as reserved for future assignment. Only the ten readily available keys summarized above are assigned in the first revision of this specification. Of the ten readily available keys summarized above, two will be identified as User Defined. One of the user-defined keys will be for slot specific IO, and the second will be for user defined bus structures. It is anticipated that the user-defined keys will only be used on J4/P4. The remaining unassigned, but readily available, keys will be identified as reserved for future assignment. The CompactPCI Base Specification has, in all revisions including the first, identified the Brilliant Blue, RAL # 5007, J1/P1 key to signify 5.0 Volt signaling and the Cadmium Yellow, RAL # 1021, J1/P1 key to signify 3.3 Volt signaling on the CompactPCI bus. The absence of a J1/P1 key signifies universal signaling according to all specifications through Revision 2.1. When the 64 bit extensions to PCI are implemented on J2/P2, the signaling levels are as indicated by the J1/P1 key. The VME64 Extensions, as standardized under the auspices of VSO and ANSI, have been mapped onto J4/P4 and J5/P5 and the Reseda Green, RAL# 6011, key has been identified to signify that usage of the two connectors together. The PICMG TISC has requested the Strawberry Red, RAL # 3018, key be used exclusively by the Computer Telephony (CT) industry for the purpose of preventing accidental insertion of any board that has J4 equipped, into a slot that has P4 wired per the TISC s CompactPCI Computer Telephony Specification for a CT subbus. When the J4/P4 zone is used for rear IO, rather than a bussed interconnect, the backplane shroud and mating rear transition module connector may be populated with connector keys. Because the Nut Brown key is the one used to designate rear IO, it is the only one appropriate for use in the rear shrouds and transition modules. Page 15 of 15

16 4. Backplane Connector Keys Page 16 of 16

17 5. Front Panel Keys 5 Front Panel Keys 5.1 Description of Keying Mechanism IEEE specifies a front panel keying arrangement for 3U and 6U Eurocard modules and enclosures. The enclosure keying block is integrated with the card guide, and provides three rectangular cavities. Each cavity can be fitted with an insert which fills half the cavity in any of four possible orientations. The mating key block on the module handle is fitted with pins of complementary orientation in each of the three positions. With three cavities and four positions in each, each mating block has 64 mutually exclusive combinations. On 3U CompactPCI modules and enclosures only one keying block, the lower block comprised of cavities D, E, and F, is installed so that only 64 combinations are available in 3U slots. On 6U CompactPCI modules and enclosures an upper keying block, comprised of cavities A, B, and C, is installed in addition to the lower block yielding 4096 combinations. Figure 5-1 summarizes the front panel keying arrangement. Page 17 of 17

18 5. Front Panel Keys Figure 5-1IEEE Front Panel Keys Page 18 of 18

19 5. Front Panel Keys 5.2 Philosophy and History of Allocation The IEEE front panel keying arrangement was originally formulated to provide system integrators and end users of VME and other mechanically compatible systems, with a mechanism to prevent mating of incompatible user defined signals. In CompactPCI systems, J3/P3, J4/P4 and J5/P5 pins were originally identified as being user defined. The pins of J2/P2 were optionally available for user defined signals in 32 bit CompactPCI systems. With the industry-wide acceptance of sub-bus definitions for J4/P4 and J5/P5, there comes the need to reserve front panel keys for each of these definitions and for user defined IO pins associated with the use of these sub-busses. While bussed utilization of J4/P4 can be identified using connector block keys, front panel keys are required to identify whether the J5/P5 block is being used in conjunction with J4/P4 or independently. When the J5/P5 block is used independently, front panel keys must be used to identify whether the J5/P5 utilization is bussed or unbussed. It is intended that the majority of the 4096 available keying combinations be preserved for their original intended use, the differentiation of slot specific user defined IO functions. Only those keying combinations needed to protect bussed interconnects on J2/P2, J3/P3 and/or J5/P5 will be reserved. The PICMG TISC has identified the need for four unique front panel keys, to be used exclusively by the Computer Telephony (CT) industry for the following purposes: 1. IEEE CT-TNV3 Interface Board Key - This key is for all CT Interface Boards qualified to directly terminate TNV3 circuits on J5/P5 pins per the TISC s Compact PCI Computer Telephony Specification for telecom IO. 2. IEEE CT-TNV2 Interface Board Key - This key is for all CT Interface Boards qualified to directly terminate TNV2 circuits on J5/P5 pins per the TISC s Compact PCI Computer Telephony Specification for telecom IO. 3. IEEE CT-TNV1 Interface Board Key - This key is for all CT Interface Boards qualified to directly terminate TNV1 circuits on J5/P5 pins per the TISC s Compact PCI Computer Telephony Specification for telecom IO. 4. IEEE CT-SELV Interface Board Key - This key is for all CT Interface Boards qualified to directly terminate SELV circuits on J5/P5 pins per the TISC s Compact PCI Computer Telephony Specification for telecom IO. In 3U backplanes one front panel keying combination must be allocated to signify the use of the J2/P2 block for extensions of the bus defined by the J1/P1 key. When the J2/P2 connector is so used, there are no pins available for user IO or sub-busses. Page 19 of 19

20 5. Front Panel Keys 5.3 Hierarchical Allocation of CompactPCI Front Panel Keys Connectors J1 and J4 are functionally identified by their IEC keys. Connectors J2, J3, and J5 are functionally identified by an arrangement of IEEE front panel keys. IEEE keys are hierarchically arranged, with cavity D on the lower keying block being the major functional designator, with cavity E next providing additional functional detail and cavity F providing slot specific IO differentiation. The keying cavities in the lower key block differentiate the utilization of J2 for 3U boards, and may also be used with upper key blocks of 6U boards to differentiate uses of J3 and J5. The key in cavity D determines whether J2 is bussed or unbussed. Cavity D Value Function 1 J2 Bussed 2 Reserved for future allocation 3 Unbussed 4 Unbussed Table 5-1 Cavity D function The key in cavity E differentiates the function of J2 when it is bussed. When J2 is unbussed it is used to differentiate the IO function. Cavity E value Functions (of J2 only when bussed) 1 Reserved for future PICMG 2.5 Computer Telephony Bus 2 PICMG bit extensions to PCI 3 PICMG 2.8 Instrumentation Extensions 4 Reserved for future allocation Table 5-2 Cavity E Function The key in cavity F is used to differentiate IO functions. When J2 is unbussed these keys may be configured by the user. When J2 is bussed these keys are used to differentiate IO functions of or some other attribute of the interconnect. In the case of the PICMG 2.5 Computer Telephony Bus, specific assignments have been made as summarized in Table 6-1, Table 6-3, Table 6-5, and Table 6-6. The lower block key assignments for 3U cards also apply to 6U, though with some modification. The PICMG 2.5 specification does not explicitly allow for a CT bus on J2 in 6U systems. In the interest of consistency and convenient use of 3U boards in 6U systems, the 256 keying combinations associated with telecommunications use in 6U Page 20 of 20

21 5. Front Panel Keys PCI 32 systems have been specially allocated assuming the future use of J2 as an as yet undefined auxiliary CT bus. In these systems, the primary CT bus is on J4. Cavity A on the upper block is the major designator for the functions of the J3 and J5 connector blocks, with additional information provided by cavity B and cavity C providing slot specific IO differentiation in conjunction with cavity F in the lower block. Page 21 of 21

22 5. Front Panel Keys Cavity A is used to denote whether J3 and/or J5 are bussed according to the following table: Cavity A value Function 1 J3 unbussed, available for IO or unpopulated, J5 utilization linked with J4 2 J3 bussed, J5 utilization linked with J4 3 J3 unbussed and available for IO or unpopulated, J5 utilization not linked with J4 4 J3 bussed, J5 utilization not linked with J4 Table 5-3 Cavity A Function For the combinations in which J3 is bussed (A = 2 or 4), the key in cavity B is used to differentiate its function according to the following table: Cavity B value Function (only when J3 bussed) 1 Reserved for future assignment 2 Reserved for future assignment 3 Reserved for future assignment 4 User defined bus on J3 Table 5-4 Cavity B Function For the combinations in which J3 is unbussed (A = 1 or 3), the cavity B key is used for IO differentiation. The cavity C key is used for IO or user defined bus differentiation for all combinations of A and B keys. An elaboration of this scheme for 3U and 6U cards is contained in the following section. When the front panel keying feature is used on rear transition modules, it is recommended that the same keying combinations be used in the rear as in front for each slot. Page 22 of 22

23 6. Key Assignments 6 Key Assignments 6.1 Backplane Connector Keys Table 6-1contains the connector key assignments for the ten readily available combinations. Any key combination, which is not specifically allocated, is reserved for future use. Color RAL # Code - Free Code - Fixed J1/P1 Use J4/P4 Use Pastel Orange User defined bus Steel Blue Slate Grey Cadmium Yellow CompactPCI 3.3V CompactPCI 3.3V Reseda Green VME64x Brilliant Blue CompactPCI 5.0V CompactPCI 5.0V Blue/Lilac Ocher Yellow Strawberry Red Telecom (PICMG Computer Telephony Specication 1.0 Nut Brown User I/O Table 6-1 IEC Connector Key Utilization Page 23 of 23

24 6. Key Assignments 6.2 Front Panel Keys Table 6-2 contains the allocation of front panel keys for 3U systems. D E F J2 Use Reserved for J2 CT Bus w/ SELV IO Reserved for J2 CT Bus w/ TNV1 IO Reserved for J2 CT Bus w/ TNV2 IO Reserved for J2 CT Bus w/ TNV3 IO PCI 64 Extensions per PICMG PXI per PICMG Bussed, reserved for future assignment Bussed, reserved for future assignment User IO User IO Table 6-2 IEEE keying assignments for 3U CompactPCI systems Table 6-3 contains the allocation of front panel keys for 6U systems. Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, Reserved User IO CT Bus SELV IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus SELV IO (Note 1) 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO VME64x (Note 2) 1 1,2,3,4 1,2,3, PCI 64 Ext User IO PCI64 (Note 3) 1 1,2,3,4 1,2,3, PXI (Note 4) User IO CT Bus (Note 1) SELV IO Page 24 of 24

25 6. Key Assignments Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3, PXI User IO VME64x (Note 2) 1 1,2,3,4 1,2,3, PXI User IO PCI64 (Note 3) 2 4 1,2,3, Reserved User Bus CT Bus SELV IO (Note 5) 2 4 1,2,3, Reserved User Bus CT Bus TNV1 IO 2 4 1,2,3, Reserved User Bus CT Bus TNV2 IO 2 4 1,2,3, Reserved User Bus CT Bus TNV3 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus SELV IO (Note 1) 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV1 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV2 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV3 IO 2 4 1,2,3, PCI 64 Ext User Bus VME64x (Note 2) 2 4 1,2,3, PCI 64 Ext User Bus PCI64 (Note 3) 2 4 1,2,3, PXI (Note 4) User Bus CT Bus SELV IO (Note 1) 2 4 1,2,3, PXI User Bus CT Bus TNV1 IO 2 4 1,2,3, PXI User Bus CT Bus TNV2 IO 2 4 1,2,3, PXI User Bus CT Bus TNV3 IO 2 4 1,2,3, PXI User Bus VME64x (Note 2) 2 4 1,2,3, PXI User Bus PCI64 (Note 3) 3 1,2,3,4 1,2,3, Reserved User IO J4 Key (Note 6) 3 1,2,3,4 1,2,3, PCI 64 Ext User IO J4 Key (Note 6) 3 1,2,3,4 1,2,3, PXI (Note 4) User IO J4 Key (Note 6) 4 4 1,2,3, Reserved User Bus J4 Key (Note 6) 4 4 1,2,3, PCI 64 Ext User Bus J4 Key (Note 6) 4 4 1,2,3, PXI (Note 4) User Bus J4 Key (Note 6) User IO User IO User IO User IO User IO User IO Page 25 of 25

26 6. Key Assignments Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 * * * 1 4 * Reserved Combinations * * * 2 * * Reserved combinations 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus SELV IO (Note 1) 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO VME64x (Note 2) 1 1,2,3,4 1,2,3,4 3, User IO User IO PCI64 (Note 3) 2 4 1,2,3,4 3, User IO User Bus CT Bus SELV IO (Note 1) 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV1 IO 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV2 IO 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV3 IO 2 4 1,2,3,4 3, User IO User Bus VME64x (Note 2) 2 4 1,2,3,4 3, User IO User Bus PCI64 (Note 3) 3 1,2,3,4 1,2,3,4 3, User IO User IO J4 Key (Note 6) 4 4 1,2,3,4 3, User IO User Bus J4 Key (Note 6) User IO User IO Note 1 For A = 1, J4 and J5 uses are linked. J4 is used as a CT Bus if Strawberry Red connector key is installed in J4. Note 2 For A=1, J4 and J5 uses are linked. J4 and J5 are used for VME64 Extensions per PICMG 2.2 if Reseda Green connector key is installed in J4. Note 3 For A=1, J4 and J5 uses are linked. J4 and J5 are used for PCI with 64 bit extensions per PICMG 2.0 if Cadmium Yellow or Brilliant Blue connector keys are installed in J4. Note 4 For D=1 and E=3, J2 carries the PCI 64 bit extensions as well as the PXI signals summarized in PICMG 2.8. PXI is interoperable with other bussed/linked uses of J4 and J5. Page 26 of 26

27 6. Key Assignments Note 5 For A=2, J4 and J5 uses are linked but J3 is bussed. Only the value B=4 has been assigned to denote a user defined bus on J3. Values of B = 1, 2, or 3 are reserved for future use. Note 6 J4 use determined by connector key, bussed or User IO if Nut Brown connector key is installed. IO functions on J5 are not related to the use of J4. Table 6-3 IEEE keying assignments for 6U CompactPCI systems. 6.3 Minimum Keying Requirements This section defines the minimum complement of keys which shall be installed by equipment suppliers consistent with safety and/or proper interoperation of CompactPCI boards and backplanes Backplanes and Enclosures For 3U and 6U backplane slots in which only J1 is installed, only the backplane connector key signifying the backplane signaling level shall be required. In this case, no front panel keys are needed to insure safety or proper operation of bussed or rear IO connections in the other connector zones. For 3U and 6U backplane slots in which only J1 and J2 are installed, the D, E, and F front panel keying cavities shall be populated appropriately to signify the use of the J2 connector according to the hierarchical allocation plan of this specification. The A, B, and C front panel keying cavities may be left unpopulated in an enclosure containing such a backplane. For 6U backplane slots in which 3 or more connectors are installed, the A, B, C, D, E, and F front panel keying cavities shall be populated appropriately to signify the use of all connectors according to the hierarchical allocation plan of this specification Boards For 3U and 6U boards on which only J1 is installed, a J1 backplane connector key shall be installed to signify the PCI signaling levels which can be tolerated. The exception, when no backplane connector key is necessary, is when the board is tolerant of both 5 volt and 3.3 volt signaling levels. Such boards may be considered universal because of their electrical compatibility with all CompactPCI backplane slots. For 3U and 6U boards on which J1 and J2 are installed, a J1 backplane connector key shall be installed to signify the PCI signaling levels which can be tolerated. The exception, when no backplane connector key is necessary, is when the board is universal (tolerant of both 5 volt and 3.3 volt signaling levels). The D, E, and F front Page 27 of 27

28 6. Key Assignments panel keying cavities shall be populated appropriately to signify the use of the J2 connector according to the hierarchical allocation plan of this specification. For 6U boards in which 3 or more connectors are installed, the J1 and J4 (if populated) backplane connector keys shall be installed according the use of the connector. An exception, when no J1 backplane connector key is necessary, is when the board is universal (tolerant of both 5 volt and 3.3 volt signaling levels). The J4 backplane connector key, when populated, shall be installed with a key signifying which bussed interconnect is in use, or if the connector is allocated for user IO as indicated by Nut Brown key. The A, B, C, D, E, and F front panel keying cavities shall be populated appropriately to signify the use of all connectors according to the hierarchical allocation plan of this specification. 6.4 Applicability to Approved Specifications PICMG 2.0 CompactPCI Base SpecificationRevision 2.1 September 2, 1997 The CompactPCI Base Specification identifies the Brilliant Blue, RAL # 5007, J1/P1 key to signify 5.0 Volt signaling and the Cadmium Yellow, RAL # 1021, J1/P1 key to signify 3.3 Volt signaling on the CompactPCI bus. The absence of a J1/P1 key on a CompactPCI board signifies universal signaling, that is, the ability to operate with either signaling level. Only a board can be considered universal. Backplanes shall always be keyed for one of the two signaling levels, consistent with the VI/O level distributed on the backplane. When the 64 bit extensions to PCI are implemented on J2/P2, the signaling levels are as indicated by the J1/P1 key. There are no mandated uses of the IEEE keys in Revision 2.1 of the CompactPCI Base Specification. Page 28 of 28

29 6. Key Assignments PICMG 2.2 VME64x Bus Pin Assignments on CompactPCI CompactPCI boards and slots which connect the VME64 Extensions on J4/P4 and J5/P5 will have the J1/P1 key consistent with the CompactPCI signaling level, and a Reseda Green, RAL# 6011, key in J4/P4. The IEEE keys will be assigned from the categories shown in Table 6-4 below: Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, PCI 64 Ext User IO VME64x (Note 2)* 1 1,2,3,4 1,2,3, PXI User IO VME64x (Note 2)* 2 4 1,2,3, PCI 64 Ext User Bus VME64x (Note 2)* 2 4 1,2,3, PXI User Bus VME64x (Note 2)* 1 1,2,3,4 1,2,3,4 3, User IO User IO VME64x (Note 2)* 2 4 1,2,3,4 3, User IO User Bus VME64x (Note 2)* *Refers the notes accompanying Table 6-3 IEEE keying assignments for 6U CompactPCI systems. Table 6-4 IEEE key combinations on hybrid CompactPCI/VME64x systems PICMG 2.5 CompactPCI Computer Telephony Specification CompactPCI boards and slots of 6U form factor which connect the CT sub-bus on J4/P4 will have the J1/P1 key consistent with the CompactPCI signaling level, and a Strawberry Red, RAL#3018, key in J4/P4. Page 29 of 29

30 6. Key Assignments The IEEE keying keying combinations specified in PICMG 2.5 are summarized in Table 6-5 below: Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, Reserved User IO CT Bus SELV IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, Reserved User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus SELV IO (Note 1)* 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, PCI 64 Ext User IO CT Bus TNV3 IO *Refers the notes accompanying Table 6-3 IEEE keying assignments for 6U CompactPCI systems. Table 6-5 Keying Combinations for 6U boards as specified in PICMG 2.5 Page 30 of 30

31 6. Key Assignments According to the hierarchical assignment rules set forth above, the following keying combinations are also allowed in Computer Telephony systems using features specified in PICMG 2.5: Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, PXI (Note 4) User IO CT Bus SELV IO (Note 1)* 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV3 IO 2 4 1,2,3, Reserved User Bus CT Bus SELV IO (Note 5) 2 4 1,2,3, Reserved User Bus CT Bus TNV1 IO 2 4 1,2,3, Reserved User Bus CT Bus TNV2 IO 2 4 1,2,3, Reserved User Bus CT Bus TNV3 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus SELV IO (Note 1)* 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV1 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV2 IO 2 4 1,2,3, PCI 64 Ext User Bus CT Bus TNV3 IO 2 4 1,2,3, PXI (Note 4) User Bus CT Bus SELV IO (Note 1)* 2 4 1,2,3, PXI User Bus CT Bus TNV1 IO 2 4 1,2,3, PXI User Bus CT Bus TNV2 IO 2 4 1,2,3, PXI User Bus CT Bus TNV3 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus SELV IO (Note 1)* 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3,4 3, User IO User IO CT Bus TNV3 IO 2 4 1,2,3,4 3, User IO User Bus CT Bus SELV IO (Note 1)* 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV1 IO 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV2 IO 2 4 1,2,3,4 3, User IO User Bus CT Bus TNV3 IO *Refers the notes accompanying Table 6-3 IEEE keying assignments for 6U CompactPCI systems. Table 6-6 Additional Keying Combinations permitted in Computer Telephony Systems using features specified in PICMG 2.5 Page 31 of 31

32 6. Key Assignments 6.5 Anticipated Impact on Proposed Specifications - Advisory PICMG 2.0 CompactPCI Base Specification, Draft 3.0 It is anticipated that the next major revision of the base specification will mandate the use of IEEE keys consistent with the assignments given above. In backplanes which have J4 installed, installation of a IEC key will be required. The Nut Brown, RAL# 8011, key signifying User I/O should be mandated as the default when there is no bussed interconnect on J4/P4. The default for IEEE keys will depend on the width of the PCI backplane. For 64 bit PCI backplanes, combinations in which F=1, E=2, and D=1 should be mandated for the lower keying block in 3U and 6U systems. In 6U systems, the defaults for the upper keys will depend on the configuration of J4/P4. It should be mandatory for all IEEE keying cavities to be populated. It should be recommended practice to install a P1 key on all CompactPCI boards. Universal boards should be shipped with a 5 volt key installed, and a spare 3.3 volt key, with a recommendation to the user or system integrator to install the key with matches the backplane PICMG 2.6 PCI-PCI Bridging for CompactPCI Backplanes CompactPCI boards and slots of 6U form factor which connect the PCI Bus on J4/P4 and J5/P5 as well as on J1/P1 and J2/P2 for the purpose of bridging PCI bus segments will have keys consistent with the CompactPCI signaling levels in J1/P1 and in J4/P4. The signaling levels need not be the same on both PCI segments, however PICMG 2.7 Dual CompactPCI Backplanes CompactPCI boards and slots of 6U form factor which connect the PCI Bus on J4/P4 and J5/P5 as well as on J1/P1 and J2/P2 for the purpose of generating two independent PCI bus segments will have keys consistent with the CompactPCI signaling level in J1/P1 and in J4/P4. The signaling levels need not be the same on both PCI segments, however PICMG 2.8 Instrumentation Extensions to CompactPCI Backplanes and options which implement the Instrumentation Extensions to CompactPCI should use J1/P1 connector keys consistent with the signaling level. In order to deal with possible future conflicts between 64 bit PCI and the Instrumentation Extensions on J2/P2, the IEEE keys should be selected from the groups summarized in the following tables: Page 32 of 32

33 6. Key Assignments D E F J2 Use PXI per PICMG 2.8 Table 6-7 IEEE lower key combinations in 3U PXI systems CompactPCI System and Peripheral Boards which do not connect to PXI pins may be keyed using the forgoing combinations. Page 33 of 33

34 6. Key Assignments Because the Instrumentation Extensions reserve the J3/P3, J4/P4 or J5/P5 for future use, these zones will not normally be populated in 6U implementations. When J4/P4 is present in a 6U PXI system, it should be fitted with a key which describes it use, and with front panel keys assigned in accordance with the rules defined in previous sections. Front panel keying combinations which would be permissible in 6U PXI systems are listed in Table 6-8: Keying Cavity and Value Connector and Use A B C D E F J2 J3 J4 J5 1 1,2,3,4 1,2,3, PXI (Note 4) User IO CT Bus SELV IO (Note 1)* 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV1 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV2 IO 1 1,2,3,4 1,2,3, PXI User IO CT Bus TNV3 IO 1 1,2,3,4 1,2,3, PXI User IO VME64x (Note 2)* 1 1,2,3,4 1,2,3, PXI User IO PCI64 (Note 3)* 2 4 1,2,3, PXI (Note 4) User Bus CT Bus SELV IO (Note 1)* 2 4 1,2,3, PXI User Bus CT Bus TNV1 IO 2 4 1,2,3, PXI User Bus CT Bus TNV2 IO 2 4 1,2,3, PXI User Bus CT Bus TNV3 IO 2 4 1,2,3, PXI User Bus VME64x (Note 2)* 2 4 1,2,3, PXI User Bus PCI64 (Note 3)* 3 1,2,3,4 1,2,3, PXI (Note 4) User IO J4 Key (Note 6)* 4 4 1,2,3, PXI (Note 4) User Bus J4 Key (Note 6)* User IO User IO *Refers the notes accompanying Table 6-3 IEEE keying assignments for 6U CompactPCI systems. Table 6-8 IEEE key combinations available for use in 6U PXI Systems Page 34 of 34