CS152 Computer Architecture and Engineering. Lecture 15 Virtual Memory Dave Patterson. John Lazzaro. www-inst.eecs.berkeley.

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1 CS152 Computer Architecture and Engineering Lecture 15 Virtual Memory Dave Patterson ( John Lazzaro ( www-inst.eecs.berkeley.edu/~cs152/ 1

2 Last Time: How to Design a Cache Most design errors come from incorrect specification of state machine behavior! Common bugs: stalls, block replacement, write buffer To CPU Control State Machine Control Control To Lower Level Memory To CPU Addr Din Dout Blocks Tags Addr Din Dout To Lower Level Memory 2

3 Today s Lecture - Virtual Memory DRAM technology Virtual address spaces Page table layout TLB design options 3

4 DRAM Technology 4

5 Why DRAM over SRAM? Density! SRAM Cell: Large bit bit 6 transistors nfet and pfet 3 interface wires Vdd and Gnd 1 0 word DRAM Cell: Small row select transistor + capacitor nfet only 2 interface wires no Vdd Density advantage: 3X to 10X, depends on metric bit 5

6 DRAM: Reading, Writing, Refresh Writing DRAM: Drive data on bit line Select row 1 1 row select 1 Capacitor holds state for 60 ms -- then must do refresh bit 1 To learn more... DRAM Circuit Design: A Tutorial Brent Keeth, R. Jacob Baker ISBN: November 2000, Wiley-IEEE Press Reading DRAM Select row Sense bit line (~1 million electrons) Write value back Refresh: a dummy read 1 bit 1 row select 1 1 6

7 Synchronous DRAM (SDRAM) Interface A clocked bus protocol (ex: 100 MHz) Note! This example is best-case! For a random access, DRAM takes many more than 2 cycles! T0 T1 T2 T3 CLK COMMAND READ NOP NOP tlz t OH DQ DOUT t AC Cache controller puts commands on bus CAS Latency = 2 (CAS = Column Address Strobe) From Micron 128 Mb SDRAM data sheet (on resources web page) Data comes out several cycles later. 7

8 Administrivia - Lab 3, HW 3, Lab 4 Lab 3 final demo on 10/22 (Friday) Lab 4 to be posted on 10/22 (Friday) (if all goes well). Lab 3 report due: Monday 10/25 11:59 PM Homework 3 due 10/26 (Tuesday), 283 Soda, in CS 152 box at 5 PM 8

9 Virtual Addressing 9

10 The Limits of Physical Addressing Physical addresses of memory locations A0-A31 CPU Where we are in CS A0-A31 Memory D0-D31 Data D0-D31 All programs share one address space: The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource 10

11 Solution: Add a Layer of Indirection Virtual Addresses Physical Addresses A0-A31 Virtual Physical A0-A31 CPU Address Translation Memory D0-D31 Data D0-D31 User programs run in an standardized virtual address space Address Translation hardware managed by the operating system (OS) maps virtual address to physical memory Hardware supports modern OS features: Protection, Translation, Sharing 11

12 MIPS R4000: Address Space Model Process A 0 Address Error 2 GB ASID = Address Space Identifier 2 31 Process B ASID = 12 Process A and B have ASID = 13 independent address spaces All address spaces translated to standard map May only be accessed by kernel/supervisor When Process A writes its address 9, it writes to a different physical memory location than Process B s address 9 Address Error 2 GB To let Process A and B share memory, OS maps parts of ASID 12 and ASID 13 to the same 0 physical memory locations. Still works (slowly!) if a process accesses more virtual memory than the machine has physical memory 12

13 MIPS R4000: Who s Running on the CPU? System Control Registers 47 0 EntryHi EntryHi 10* TLB EntryLo0 EntryLo0 2* 2* EntryLo1 3* ( Safe entries) (See Random Register, contents of TLB Wired) LLAddr 17* TagLo 28* Index Index 0* Random Random 1* Page Mask Page Mask 5* Wired Wired 6* PRId 15* Config 16* TagHi 29* Used with memory management system. *Register number Context 4* Count 9* Status 12* EPC 14* WatchHi 19* ECC 26* BadVAddr 8* Compare 11* Cause 13* WatchLo 18* XContext 20* CacheErr 27* ErrorEPC 30* Used with exception processing. See Chapter 5 for details. Status (12): Indicates user, supervisor, or kernel mode EntryLo0 (2): 8-bit ASID field codes virtual address space ID. User cannot write supervisor/kernel bits. Supervisor cannot write kernel bit. User cannot change address translation configuration 13

14 MIPS Address Translation: How does it work? Virtual Addresses Physical Addresses A0-A31 CPU D0-D31 Data Virtual Physical Translation Look-Aside Buffer (TLB) A0-A31 Memory D0-D31 Translation Look-Aside Buffer (TLB) A small fully-associative cache of mappings from virtual to physical addresses TLB also contains ASID and kernel/supervisor bits for virtual address Fast common case: Virtual address is in TLB, process has permission to read/write it. What is the table of mappings that it caches? 14

15 Page tables encode virtual address spaces Page Table (One per ASID) Physical Memory Space frame frame A virtual address space is divided into blocks of memory called pages virtual address OS manages the page table for each ASID frame frame A machine usually supports pages of a few sizes (MIPS R4000): A page table is indexed by a virtual address Page Size 4 Kbytes 16 Kbytes 64 Kbytes 256 Kbytes 1 Mbyte A valid page table entry codes physical memory frame address for the page 4 Mbytes 16 Mbytes 15

16 The TLB caches page table entries TLB caches page table entries. virtual address page off e Page Table TLB frame page Virtual Address V page no. Page Table Base for ASIDReg index into page table physical address page off Page Table V Access Rights 10 offset PA table located in physical memory MIPS handles TLB misses in software (random replacement). Other machines use hardware. Physical and virtual pages must be the same size! P page no. Physical frame address offset 10 Physical Address V=0 pages either reside on disk or have not yet been allocated. OS handles V=0 Page fault 16

17 Page tables may not fit in memory! A table for 4KB pages for a 32-bit address space has 1M entries Each process needs its own address space! Two-level Page Tables 1K PTEs 4KB 32 bit virtual address P1 index P2 index Page Offset 4 bytes Top-level table wired in main memory Subset of 1024 second-level tables in main memory; rest are on disk or unallocated s space? 4 bytes 17

18 VM and Disk: Page replacement policy Head pointer Place pages on free list if used bit is still clear. Schedule pages with dirty bit set to be written to disk. Set of all pages in Memory Dirty bit: page written. Used bit: set to 1 on any reference Tail pointer: Clear the used bit in the page table Architect s role: support setting dirty and used bits dirty used Page Table... Freelist Free Pages 18

19 TLB Design Concepts 19

20 MIPS R4000 TLB: A closer look... Virtual Addresses Physical Addresses A0-A31 CPU D0-D31 Checked against CPO ASID 39 ASID 8 Data Virtual Physical Translation Look-Aside Buffer (TLB) Virtual Address with 1M (2 20 ) 4-Kbyte pages bits = 1M pages VPN Offset A0-A31 Memory System D0-D31 Physical space larger than virtual space! Bits 31, 30 and 29 of the virtual address select user, supervisor, or kernel address spaces. TLB Virtual-to-physical translation in TLB 36-bit Physical Address Offset passed unchanged to physical memory 35 0 PFN Offset 20

21 Can TLB and caching be overlapped? Virtual Page Number Page Offset Index Byte Select Virtual Translation Look-Aside Buffer (TLB) Physical Cache Tags Valid Cache Data Cache Block Cache Tag = Cache Block This works, but... Hit Q. What is the downside? A. Inflexibility. VPN size locked to cache tag size. Data out 21

22 Can we cache virtual addresses? Virtual Addresses Physical Addresses A0-A31 CPU D0-D31 Virtual Cache D0-D31 Virtual Physical Translation Look-Aside Buffer (TLB) A0-A31 Main Memory D0-D31 Only use TLB on a cache miss! Downside: a subtle, fatal problem. What is it? A. Synonym problem. If two address spaces share a physical frame, data may be in cache twice. Maintaining consistency is a nightmare. 22

23 Conclusions Synchronous DRAM: flexible bus protocol for array access VM: Uniform memory models, protection, sharing. A TLB acts as a fast cache for recent address translations. Operating systems manage the page table and (often) the TLB 23

CS 152 Computer Architecture and Engineering

CS 152 Computer Architecture and Engineering Lecture 12 -- Virtual Memory 2014-2-27 John Lazzaro (not a prof - John is always OK) TA: Eric Love www-inst.eecs.berkeley.edu/~cs152/ Play: CS 152 L12: Virtual