CS 152 Computer Architecture and Engineering

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 13 Memory and Interfaces John Lazzaro ( TAs: Ted Hong and David Marquardt www-inst.eecs.berkeley.edu/~cs152/

2 Last Time: 1-T DRAM cells Bit Line Word Line Vdd Word Line Vdd Capacitor Bit Line Bit Line n+ n+ p- oxide oxide Word Line and Vdd run on z-axis Why Vcap values start out at ground. Vcap Vdd Diode leakage current.

3 Today: Memory Technology Wrap-Up Static Memory Circuits: For SRAM memory cells and for flip-flops. Memory Arrays: Row decoders, column sense amps, array sizing. DRAM Interfaces: How the SDRAM chips on the Calinx board work.

4 Inverters

5 Inverters: Circuits and Layout Vdd symbol Vin Vout Vin Vout

6 Inverter: Die Cross Section Vout Vin oxide n+ n+ p- Vin oxide p+ p+ n+ n-well Vin Vout

7 Inverters: n-fet Transistor Equation If Vgs > Vt and Vds > Vgs - Vt : Ids = (k/2) (W/L) [Vgs -Vt]^2 Vin V d Vout V g I ds V s Otherwise, if Vgs > Vt : Ids = k (W/L) [Vgs -Vt] [Vds] Otherwise: Ids 0, but really = Io [exp((κvg - Vs)/Vo)] [1 - exp(-vds/vo)] Note: Vt is transistor threshold, was formerly Vth. Also, Vt is actually Vt(Vs) sqrt(vs).

8 Inverters: p-fet Transistor Equation V s If Vsg > Vt and Vsd > Vsg - Vt : I sd Isd = (k/2) (W/L) [Vsg -Vt]^2 Vin V g V d Vout Otherwise, if Vsg > Vt : Otherwise: Isd 0, but again, in reality there is a leakage current. Isd = k (W/L) [Vsg -Vt] [Vsd] Note: Vt for p-fet and n-fet are different. Also true for k (fab constant). kp < kn, due to electrons being faster than holes.

9 Inverters with Vin = Gnd, Vout = Vdd Is Vsd > Vsg - Vt once Vout is Vdd? Is Vsg > Vt? I sd V s Isd = k (W/L) [Vsg -Vt] [Vsd] Vin V d V d I ds Vout This goes as close to 0 as it can while still supplying the leakage current. V s Ids 0, but really a small leakage current

10 Inverters with Vin = Vdd, Vout = Gnd Isd 0, but really a small leakage current Vin V s I sd V d V d Vout This goes as close to 0 as it can while still supplying the leakage current. I ds V s Is Vds > Vgs - Vt once Vout is Gnd? Is Vgs > Vt? Ids = k (W/L) [Vgs -Vt] [Vds]

11 Calculating the inverter threshold (Vth) Vth Tie output to input. Vth I sd V s Assume voltage is somewhere near the middle Vin V d V d Vout For nfet, is Vds > Vgs - Vt? For pfet, is Vsd > Vsg - Vt? I ds No, by definition! Use: V s Ids = kn (W/L) [Vth -Vtn] [Vth] Isd = kp (W/L) [Vdd-Vth -Vtp] [Vdd - Vth] To compute the exact voltage in the middle.

12 Question: What happens when... V s V s I sd I sd Vin V d V d Vout Vin V d V d Vout I ds I ds V s V s Stays at Vth until a tiny amount of Vin noise appears. Then output goes to Vdd or Gnd until Vin noise flips it back the other way. Lesson: at Vth, small dvin make big dvout

13 Static Memory Circuits Dynamic Memory: Circuit remembers for a fraction of a second. Static Memory: Circuit remembers as long as the power is on. Non-volatile Memory: Circuit remembers for many years, even if power is off.

14 Recall DRAM cell: 1 T + 1 C Word Line Row Column Bit Line Column Row Word Line Vdd Bit Line

15 Idea: Store each bit with its complement x x! Row Why? Gnd Vdd Vdd Gnd We can use the redundant representation to compensate for noise and leakage.

16 Case #1: x = Gnd, x! = Vdd... x x! Row I sd Gnd Vdd I ds

17 Case #2: x = Vdd, x! = Gnd... x x! Row I sd Vdd Gnd I ds

18 Combine both cases to complete circuit Gnd Vdd Vth Vth Vdd Gnd Crosscoupled inverters noise noise x x!

19 SRAM Challenge #1: It s so big! SRAM area is 6X-10X DRAM area, same generation... Cell has both transistor types Vdd AND Gnd Capacitors are usually parasitic capacitance of wires and transistors. More contacts, more devices, two bit lines...

20 Challenge #2: Writing is a fight When word line goes high, bitlines fight with cell inverters to flip the bit -- must win quickly! Solution: tune W/L of cell & driver transistors Initial state Vdd Initial state Gnd Bitline drives Gnd Bitline drives Vdd

21 Challenge #3: Preserving state on read When word line goes high on read, cell inverters must drive large bitline capacitance quickly, to preserve state on its small cell capacitances Cell state Vdd Cell state Gnd Bitline a big capacitor Bitline a big capacitor

22 SRAM vs DRAM, pros and cons DRAM has a 6-10X density Big win for DRAM advantage at the same technology generation. SRAM advantages SRAM has deterministic latency: its cells do not need to be refreshed. SRAM is much faster: transistors drive bitlines on reads. SRAM easy to design in logic fabrication process (and premium logic processes have SRAM add-ons)

23 Admin: First Xilinx Checkoff in Friday Homework 1: is also due Friday! Midterm 1: Thurs 3/17, 6PM to 9PM

24 Memory Arrays Calinx DRAM: 133 Mhz, 128 Mb SYNCHRONOUS DRAM 128Mb: x4, x8, x16 SDRAM MT48LC32M4A2 8 Meg x 4 x 4 banks MT48LC16M8A2 4 Meg x 8 x 4 banks MT48LC8M16A2 2 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: Data sheet on resources page. Will need to understand for final project!

25 Bit Line Column Word Line Row People buy DRAM for the bits. Edge circuits are overhead So, we amortize the edge circuits over big arrays

26 A bank of 32 Mb (128Mb chip -> 4 banks) 1 12-bit row address input o f d e c o d e r 4096 rows Each column 4 bits deep 2048 columns 33,554,432 usable bits (tester found good bits in bigger array) 8196 bits delivered by sense amps Select requested bits, send off the chip

27 Recall DRAM Challenge #3b: Sensing How do we reliably sense a 60mV signal? Compare the word line against the voltage on [...] a dummy world line. sense amp Word line to sense + Dummy word line.? - Cells hold no charge. Dummy word line

28 Corresponds to row read into sense amps 12-bit row address input 1 o f d e c o d e r Slow! This 7.5ns period DRAM (133 MHz) can do row reads at only 75 ns ( 13 MHz). Plus, need to add selection time. DRAM has high latency to first bit out. A fact of life rows 2048 columns 33,554,432 usable bits (tester found good bits in bigger array) 8196 bits delivered by sense amps Select requested bits, send off the chip Each column 4 bits deep

29 An ill-timed refresh may add to latency Bit Line Word Line Parasitic currents leak away charge. Solution: Refresh, by reading cells at regular intervals (tens of milliseconds) + Vdd n+ n+ p- oxide oxide Diode leakage...

30 Latency is not the same as bandwidth! Thus, push to faster DRAM interfaces 12-bit row address input 1 o f d e c o d e r What if we want all of the 8196 bits? In row access time (75 ns) we can do 10 transfers at 133 MHz. 8-bit chip bus -> 10 x 8 = 80 bits << 8196 Now the row access time looks fast! 4096 rows 2048 columns 33,554,432 usable bits (tester found good bits in bigger array) 8196 bits delivered by sense amps Select requested bits, send off the chip Each column 4 bits deep

31 Sadly, it s rarely this good bit row address input 1 o f d e c o d e r What if we want all of the 8196 bits? The we for a CPU would be the program running on the CPU. Recall Amdalh s law: If 20% of the memory accesses need a new row access... not good rows 2048 columns 33,554,432 usable bits (tester found good bits in bigger array) 8196 bits delivered by sense amps Select requested bits, send off the chip Each column 4 bits deep

32 DRAM latency/bandwidth chip features Columns: Design the right interface for CPUs to request the subset of a column of data it wishes: 8196 bits delivered by sense amps Select requested bits, send off the chip Interleaving: Design the right interface to the 4 memory banks on the chip, so several row requests run in parallel. Bank 1 Bank 2 Bank 3 Bank 4

33 Off-chip interface for the Micron part... A clocked bus protocol (133 MHz) Note! This example is best-case! For a random access, DRAM takes many more than 2 cycles! T0 T1 T2 T3 CLK COMMAND READ NOP NOP tlz t OH DQ DOUT t AC DRAM is controlled via commands (READ, WRITE, REFRESH,...) CAS Latency = 2 (CAS = Column Address Strobe) Synchronous data output with variable latency From Micron 128 Mb SDRAM data sheet (on resources web page)

34 Example: Access all 4 banks in parallel T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DQ DOUT n DOUT a DOUT x DOUT m CAS Latency = 3 NOTE: Each READ command may be to any bank. DQM is LOW. Figure 8 Random READ Accesses DON T CARE

35 Lectures: Coming up next... Essential tools for the final project. Last 3 new-material lectures before midterm.