Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp

Transcription

1 . BRIEF REPORT. SCIENCE CHINA Information Sciences February 2014, Vol : :6 doi: /s Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp ZHANG Peng 1, WANG Yuan 2, ZHANG Xing 2, MA XiaoHua 1 &HAOYue 1 1 Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi an , China; 2 Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing , China Received October 9, 2013; accepted November 4, 2013; published online November 29, 2013 Abstract Due to latch-up issue, the main problem of silicon-controlled rectifier (SCR) for power supply clamps in on-chip ESD protection is its inherent low holding voltage, especially in high-voltage applications. In this paper, we proposed a MOS-inside SCR () showing nearly no snapback character and good ESD robustness, which is qualified for on-chip power clamp ESD protection. The stacked device achieves a series of triggering and holding voltage by altering the stacking number, which can also be used for the high voltage ESD power supply clamp applications. Keywords high voltage electrostatic discharge (ESD), SCR, latch-up immunity, holding voltage, power supply clamp, Citation Zhang P, Wang Y, Zhang X, et al. Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci China Inf Sci, 2014, 57: (6), doi: /s Introduction Transient-induced latch-up in integrate circuit power supply is a major concern in designing the electrostatic discharge (ESD) protection solutions [1]. For high voltage (HV) application, the supply voltage is in the range of tens of volts [2]. Its latch-up risk becomes more serious because of harsh operating environment and noise generated from switching [3]. Silicon-controlled rectifier (SCR) processes excellent failure current and relatively low on-resistance compared to any other device, such as diode or MOSFET [4], which makes it very robust for ESD power supply clamp. However, the low holding voltage (V h ) makes the SCR susceptible to latch-up danger during normal circuit operations in a noisy environment [5]. Extensive studies have focused on this subject. The major solution is increasing the V h larger than the power supply voltage to eliminate the latch-up risk of the circuit [6 10]. Moreover, how to greatly improve the V h in ESD applications of the power ICs becomes especially difficult as its power supply is in high voltage range [11]. Severral SCR structures aiming to increase the V h in HV application have been proposed [12 15], showing that by increasing the device dimension or using stacking mode or other methods, the latch-up immunity along with excellent ESD robustness in HV technology can beachievedbyscrs.butnoneofthesescrscan Corresponding author ( pengzhang@xidian.edu.cn) c Science China Press and Springer-Verlag Berlin Heidelberg 2013 info.scichina.com link.springer.com

2 Zhang P, et al. Sci China Inf Sci February 2014 Vol :2 VDD VSS VDD VSS Lnw SB N+ P+ N+ N+ P+ P+ N+ N+ P+ Rnw Rpw Rnw N-well P-well N-well P-well P-substrate P-substrate Figure 1 (Color online) Cross-sections of the and the. Rnw Rnw NMOS NMOS Figure 2 Schematics of the and the. solve the digital and the HV power supply clamp applications together as their high triggering voltage (V t1 ) is hard to prevent the gate breakdown at low voltage in the digital ICs. In this work, a novel MOS-inside SCR () realized in bulk CMOS technology and SOI BCD technology for both digital power clamp application and HV power clamp application is presented. The structure [16] derived from the classic low-voltage triggering SCR () [17] shows lower V t1 with nearly no-snapback characteristics, which indicates good latch-up immunity. Moreover, the device realized in stacking mode (one device s cathode connect to another s anode) shows very high triggering voltage and good ESD performance. The stacked can achieve V h above 40 V after experiment, which can be flexibly applied for different HV power supply requirement. 2 Structure of for ESD power supply clamp Figure 1 shows cross-section of the novel in CMOS process along with a normal. The novel device is formed by a lateral SCR device (composed by two cross-coupled parasitic BJTs: the vertical p-n-p and the lateral n-p-n ) with a short-channel NMOS merged together to lower the V t1 of lateral SCR. The gate of NMOS is connected to VSS to ensure itself in off state during the normaloperation conditions. A silicide-block (SB) layer is added between the N+ implant in the anode and the gate in order to provide a ballasting resistance and protect the gate oxide from early breakdown [18]. The schematics of both and devices are shown in Figure 2. Unlike the structure, the anode electrode is directly connected to the central N+ implant which crosses the N-well/P-substrate junction. And the P+ implant in anode is far away from the p-n junction. While in the the anode electrode is connected to the N+ implant in the N-well and the current have to cross the N-well to reach the central N+ implant. These changes result in different I-V characteristics under the ESD stress, which will be discussed later.

3 Zhang P, et al. Sci China Inf Sci February 2014 Vol :3 Current (A) Figure 3 (Color online) TLP testing results of the proposed and original. 10 Current (A) HH Lnw=2.5 µm HH Lnw=3.5 µm HH Lnw=4.5 µm Figure 4 (Color online) TLP testing results of the proposed and, altering the n-well length (L nw) LDMOS-SCR triggering behavior 3.1 I-V curve under TLP testing results Figure 3 presents the TLP testing results of the comparing with the realized in 0.13 µm CMOS process, and the data in 0.18 µm SOI BCD process is present in Figure 4. The gate width of each device is 40 µm in CMOS technology and 40 µm in SOI technology. The in both processes shows lower V t1 and higher V h compared to the. The lower V t1 of the is because the anode electrode is directly connected to the central N+ implant crossing the N-well/P-well junction, while the anode electrode of is connected to the N+ implant in the N-well and the current have to cross the N-well to reach the central N+ implant. Thus, the V t1 of the will be lower than the due to the smaller parasitic resistance along the N-well path. On the other hand, the base width of BJT (distance between the P+ implant in N-well and the P-N junction) in the is larger than the due to longer n-well length L nw, which means the current gain of is reduced. So the V h in is larger to maintain the current generated by the avalanche breakdown. The I-V curves of altering the n-well length L nw is also shown in Figure 4. As the L nw enlarges, the resistance of N-well increases and the V t1 becomes higher. Meanwhile, the base width of BJT also becomes larger and current gain of is reduced as we mentioned before. Therefore, it needs extra voltage to achieve the current required by the snapback. So the holding voltage of is increased. By this method, V h can be adjusted to above the power supply and keeping the V t1 relatively low at the same time to meet the ESD design window of the power clamp. 3.2 Distribution of current density using device simulation In this part, ISE-TCAD tool is used to investigate the microscopic physical mechanism which is responsible for the ESD behaviour. In order to simulate the actual environment, the human body ESD stress model (HBM), which is the most commonly used ESD testing model, is used for the transient sweep simulation. In Figure 5, the distribution of current density of both SCRs obtained by Dessis simulation tool can also explain the inherent mechanism of the lower V t1 in the. The devices are demonstrated in both triggering point and high current point (the anode-cathode current of each device is 1.25 A after snapback). At the triggering point, the NMOS of the turns on first and most of the current is discharged through the whole area like a normal SCR, while most of the current is around the NMOS as the anode can directly discharge current through the NMOS to the P-well. Thus the V t1 of the is the same with the NMOS, which is lower than V t1 of the inherent SCR. At the high current point, both SCRs discharge current through the whole area. For the, it means the inherent SCR is triggered on to ensure good ESD performance.

4 Zhang P, et al. Sci China Inf Sci February 2014 Vol :4 Triggering High current Abs (Total current density) Triggering High current Abs (Total current density) Figure 5 (Color online) Total current density of and at two points: triggering point and high current point. HV VDD PLDMOS NLDMOS I/O Pad Power-rail clamp Lnw SB P+ N+ N+ P+ Rpw Rnw N-well P-well Trench Buried oxide Trench VSS Figure 6 ESD power supply clamp using the stacked s. P-substrate Figure 7 (Color online) device structure in SOI BCD technology. 4 Stacking mode for HV ESD power supply clamp After realizing the, we assume that the device in stacking mode should achieve both high V t1 and V h for the HV power clamp applications as its nearly no-snapback advantage is also very suitable for the HV ESD design window. Figure 6 shows the stacked mode in application of HV power supply clamp. It should be noted that the substrate of each device is separated to achieve a multiple of triggering voltage. Figure 7 shows the realized in 0.18 µm SOI BCD technology for 40 V power supply clamp applications. The substrate of each cell is separated by the trench and buried oxide (BOX) isolation in SOI technology. The device has a 2 µm thick substrate above the BOX, so there is no difference with the bulk structure shown in Figure 1 except for the BOX. Figure 8 shows the TLP testing results with the stacking number altering from single to 6. And the L nw width is changed from 2.5 µm to4.5µm to observe the influence to the snapback characteristics. The V t1 and V h increase as the stacked number enlarges. Also the device on-resistance (namely reciprocal of the I-V curve slope) is increased due to the series connection of the devices. Larger L nw increases the parasitic R nw and also raises the V t1 and V h. As the breakdown voltage of LDMOS applied for HV I/O in our BCD process is 60 V, the five-stacked with 4.5 µm L nw with 54 V V t1 and 40 V V h is very suitable for the HV power supply applications. And the experiment data also showed that the V t1 and the V h can be adjusted by selecting a proper stacking number and changing the L nw width to meet different HV ESD protection requirement.

5 Zhang P, et al. Sci China Inf Sci February 2014 Vol : cell 2 cell stacking cell stacking L nw =2.5 µm 4 cell stacking 5 cell stacking 6 cell stacking L nw =3.5 µm L nw =4.5 µm Figure (Color online) TLP testing results of stacked with different n-well length (L nw). 5 Conclusion The structure with nearly no snapback and good ESD robustness has been realized in both CMOS and SOI BCD technology. The anode electrode is directly connected to the central N+ implant crossing the N-well/P-well junction and thus possesses low triggering voltage compared to the. By increasing the L nw, the holding voltage can be adjusted to above the power supply and keeping its snapback voltage within a small range to achieve latch-up-free ESD applications. In SOI BCD technology, the device in stacking mode can be adjusted to meet different high-voltage power supply requirement by selecting proper stacking unit number and/or the dimension of the unit cell. Acknowledgements This work was supported by National Basic Research Program of China (Grant No. 2011CBA00606) and Young Scientists Fund of the National Natural Science Foundation of China (Grant No ). References 1 Weiss G H, Young D E. Transient-induced latchup testing of CMOS integrated circuits. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Phoenix, Hsu S F, Ker M D. Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs. IEEE Trans Electron Dev, 2007, 54: Chen W Y, Ker M D, Jou Y N, et al. Source-side engineering to increase holding voltage of LDMOS in a -m 16-V BCD technology to avoid latch-up failure. In: Proceedings of 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, Suzhou,

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