Low-C ESD Protection Design with Dual Resistor-Triggered SCRs in CMOS Technology

Transcription

1 Low-C ESD Protection Design with Dual Resistor-Triggered SCRs in CMOS Technology Chun-Yu Lin, Senior Member, IEEE, and Chun-Yu Chen Abstract The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this work. The proposed design includes a P-type RTSCR between I/O and VDD, an N-type RTSCR between I/O and VSS, and a power clamp circuit between VDD and V SS to achieve whole-chip E SD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-c ESD protection in CMOS technology. Index Terms Electrostatic discharge (ESD), low capacitance, silicon-controlled rectifier (SCR). F I. INTRODUCTION OR the demand of faster data transmission, the transceivers operated in millimeter-wave and microwave frequencies are the good candidate [1]. CMOS technology is a promising way to implement the millimeter-wave and microwave integrated circuits with the advantages of high integration capability and low cost for mass production [], [3]. However, the MOSFET is inherently susceptible to the electrostatic discharge (ESD) events; furthermore, the input/output (I/O) pads of the integrated circuits are usually connected to the gate terminal or silicided drain/source terminal of the MOSFET, which makes the integrated circuits very sensitive to ESD [4], [5]. Once the integrated circuits are damaged by ESD, they can not be recovered and the functionality will be lost. The ESD damage has become one of the most important reliability issues for the integrated circuits [6], [7]. Therefore, the ESD protection circuits must be equipped on the chip. To achieve effective ESD protection, the clamping voltage of ESD protection circuit during ESD stresses should be sufficiently low to prevent the internal circuits from damage [8], [9]. In addition, the clamping voltage of ESD protection circuit should be higher than the power-supply voltage (V DD) to prevent the ESD protection circuit from being mis-triggered under normal circuit operating conditions. As the CMOS technology advanced, the gate oxide becomes thinner, and the This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Contracts of MOST E CC and MOST E , and in part by Amazing Microelectronic Corp., Taiwan. (Corresponding author: Chun-Yu Lin.) The authors are with the Department of Electrical Engineering, National Taiwan Normal University, Taipei 106, Taiwan ( cy.lin@ieee.org). gate-oxide breakdown voltage is decreased to <5V in nanoscale CMOS technologies [10], [11]. As a result, the ESD protection design to provide efficient ESD protection without degrading the normal circuit operating will be very important in nanoscale CMOS technologies. The integrated circuits operated in millimeter-wave and microwave frequencies are very sensitive to the parasitic capacitance. Conventional ESD protection device, such as the gate-grounded NMOS, with large dimension to provide efficient ESD protection has the large parasitic capacitance [1]. To mitigate the performance degradation caused by ESD protection device, several low-c ESD protection design have been developed. The ESD protection design with reduced parasitic capacitance can be easily combined or co-designed with the high-frequency circuits [13]. In this paper, the conventional low-c ESD protection designs in CMOS technology will be reviewed, and then a proposed ESD protection design with resistor-triggered silicon-controlled rectifiers (SCRs) to achieve even lower parasitic capacitance will be introduced. II. CONVENTIONAL LOW-C ESD PROTECTION DESIGN A. Dual Diodes Diodes have been used as the ESD protection devices [14], [15]. The conventional ESD protection design with dual diodes is shown in Fig. 1, where the P-type diode (D P) provides the ESD current path from I/O to V DD, and the N-type diode (D N ) provides the ESD current path from V SS to I/O [16], [17]. It should be noted that additional power clamp circuit is needed between V DD and V SS to achieve whole-chip ESD protection [18], [19]. The ESD protection diodes are typically realized with STI-bounded diodes, due to their lower parasitic capacitance among the diodes [0]. Figures 1 and 1(c) show the device cross-sectional views of P-type and N-type STI-bounded diodes, respectively. The P-type STI-bounded diode consists of P+/N-well, and the N-type STI-bounded diode consists of P-well/N+. For the consideration of low noise for high-frequency applications, the deep N-well layer is used in the N-type diode to isolate the P-well from the common P-substrate. During normal circuit operating conditions, both D P and D N are reverse biased and kept off. However, the junction capacitances of diodes cause high-frequency performance degradation. The parasitic capacitance of ESD protection is the concern for the high-frequency applications.

2 B. Dual Stacked Diodes The ESD protection devices in stacked configuration to reduce the parasitic capacitance has ever been presented [1]. The ESD protection design with dual stacked diodes is shown in Fig. []. The device cross-sectional views of P-type stacked diodes (D P1 and D P ) and N-type stacked diodes (D N1 and D N) are shown in Figs. and (c), respectively. With the stacked diodes, the junction capacitances are connected in series, and the overall parasitic capacitance becomes smaller. (c) Fig. 1. Schematic circuit of ESD protection design with dual diodes. Device cross-sectional views of D P and (c) D N. Although stacked diodes can reduce the parasitic capacitance, this design is adverse to ESD protection because the overall clamping voltage of the stacked diodes during ESD stresses are increased as well. C. Dual Stacked Diodes with Embedded SCR The SCR has been reported to be useful for ESD protection [3], [4]. To reduce the clamping voltage during ESD stresses, the stacked diodes with embedded SCR has ever been presented [5]-[7]. The SCR device consists of P-N-P-N four layers, and it is useful for ESD protection with high ESD robustness and small layout area. The equivalent circuit of SCR consists of a PNP BJT and an NPN BJT. As ESD zapping, the positive-feedback regenerative mechanism of the PNP and the NPN results in the SCR device highly conductive to make SCR very robust against ESD stresses. The ESD protection design with dual stacked diodes and embedded SCR is shown in Fig. 3, where the P-type and N-type diodes (D P1 and D N1, or D P and D N ) are put together in layout. The device cross-sectional views of stacked D P and D N and stacked D P1 and D N1 are shown in Figs. 3 and 3(c), respectively. The embedded SCR can be established through the P+, N-well, P-well, and N+. During ESD stresses, the stacked diodes will be forward biased to discharge the initial ESD current, and then the embedded SCR will be turned on to discharge the primary ESD current. The stacked diodes also act like the trigger circuit of the embedded SCR to make it fast turned on. (c) Fig.. Schematic circuit of ESD protection design with dual stacked diodes. Device cross-sectional views of stacked D P1 and D P, and (c) stacked D N1 and D N. (c) Fig. 3. Schematic circuit of ESD protection design with dual stacked diodes and embedded SCR. Device cross-sectional views of stacked D P and D N, and (c) stacked D P1 and D N1.

3 (c) Fig. 4. Schematic circuit of ESD protection design with dual RTSCR. Device cross-sectional views of RTSCR P and (c) RTSCR N. Fig. 5. Simplified model of RTSCR P and RTSCR N. TABLE I COMPARISON AMONG PARASITIC CAPACITANCE OF ESD PROTECTION DEVICES Devices Parasitic Capacitance Capacitance Reduction D P C 0% D P1 +D P 0.67C 33% D P+D N 0.75C 5% RTSCR P (R TP >>0) 0.73C 7% D N C 0% D N1 +D N 0.6C 40% D P1+D N1 0.75C 5% RTSCR N (R TN >>0) 0.55C 45% *Assuming each junction capacitance is equal to C. III. PROPOSED LOW-C ESD PROTECTION DESIGN WITH DUAL RTSCRS By using the small resistor as the trigger element, the resistor-triggered SCR (RTSCR) has been present for high-speed applications [8]. In this work, the low-c ESD protection design with dual RTSCRs is proposed. The schematic circuit of ESD protection design with dual RTSCRs is shown in Fig. 4, where the small resistor is inserted between the P-type and N-type diodes (D P1 and D N1, or D P and D N ). The P-type RTSCR (RTSCR P ) provides the ESD current path from I/O to V DD, and the N-type RTSCR (RTSCR N) provides the ESD current path from V SS to I/O, which is different from the typical design of local SCR protection from I/O to V SS [8]-[31]. During normal circuit operating conditions, the I/O potential is always lower than the V DD potential, and the V SS potential is always lower than the I/O potential, so the SCR paths cannot keep turning on. Therefore, the RTSCR devices can be safely used without latchup danger. The power clamp circuit, as used in the conventional ESD protection design, is also needed between V DD and V SS to achieve whole-chip ESD protection. The device cross-sectional views of P-type and N-type RTSCRs are shown in Figs. 4 and 4(c), respectively. The anode of the P-type RTSCR is arranged in the center, and the cathode is arranged to the outside, which can minimize the overall parasitic capacitance seen at the I/O. Similarly, the cathode of the N-type RTSCR is arranged in the center, and the anode is arranged to the outside. During ESD stresses from I/O to V DD or from V SS to I/O, the initial ESD current will be discharged through the P+/N-well diode, the small resistor (R TP or R TN), and the P-well/N+ diode. In this moment, the current drawn from the N-well and injected into the P-well can trigger on the SCR to discharge the primary ESD current. The small resistor can limit the large ESD current from flowing through the diode path, and the large ESD current can be discharged through the robust SCR path. Furthermore, the small resistor can also help to reduce the overall parasitic capacitance seen at the I/O. Considering the simplified model of RTSCR P and RTSCR N by using junction capacitances, as shown in Fig. 5, the parasitic capacitance seen at the I/O can be calculated. Assuming each

4 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI /TDMR , IEEE (c) (d) (e) (f) (g) (h) Fig. 6. Layout top views of DP, stacked DP1 and DP, (c) stacked DP and DN with embedded SCR, (d) P-type RTSCR with 150 RTP (RTSCRP_150 ), (e) DN, (f) stacked DN1 and DN, (g) stacked DP1 and DN1 with embedded SCR, and (h) N-type RTSCR with 150 RTN (RTSCRN_150 ). junction capacitance is equal to C to simply the calculation, Eqs. (1) and () express the parasitic capacitances of the RTSCRP and RTSCRN, respectively CRTSCRP CRTSCRN Im YRTSCRP Im YRTSCRN 3 C R TP C RTP 3 4 C (1) C RTN C C RTN () which is obtained from the imaginary part of the admittance of each RTSCR. According to this calculation result, the capacitance reduction of RTSCRP and RTSCRN can be up to 7% and 45%, as compared with the dual diodes. The capacitance reduction among the ESD devices are compared in Table I. It should be noted this calculation result is based on the assumption of the equal junction capacitance. The actual capacitance reduction of RTSCR may be further improved. IV. IMPLEMENTATION OF TEST DEVICES A 0.18-μm CMOS process is used in this work to implement the conventional and proposed ESD protection designs in silicon. Figures 6~6(d) show the layout top views of the test devices between I/O and VDD, and Figs. 6(e)~6(h) show the layout top views of the test devices between VSS and I/O. The width of each test device is selected to be 0μm. The top metal (M6 in the given CMOS process) is used for connecting from the test devices to the I/O pads, while the lower metals (M and M3) is used for connecting to VDD or VSS. For the test devices of RTSCRs, the uses of 5 and 150 polysilicon resistors are demonstrated in this work. Figures 6(d) and 6(h) show the layout top views of RTSCRP and RTSCRN with 150 resistors. If the polysilicon resistor cannot sustain the stressing current, other types of resistors in the given CMOS process can be used instead. Besides, the resistance value can be further optimized for specified applications. All the test devices are arranged in ground-signal-ground (G-S-G) pads, which is a common pad

5 structure for RF measurement to set a reference ground for the high-frequency signals [3], [33]. A. HBM ESD Robustness V. EXPERIMENTAL RESULTS The HBM ESD robustness of each device is tested. The failure criterion is defined as the I-V curve seen between test pads shifting over 30% from its original curve after ESD stresses at every ESD test level. The measurement results show that the test devices can pass 3.5kV ~ 4.5kV HBM ESD tests, in which all the SCR-based devices have 4kV HBM ESD robustness at least. All these test results are summarized in Table II. B. TLP I-V Characteristics The transmission-line-pulse (TLP) system is used to simulate the HBM ESD stresses, and the I-V characteristics of the test devices can be obtained. The TLP-measured I-V characteristics of test devices between I/O and V DD are shown in Fig. 7. The triggering behaviors of test devices are shown in Fig. 7. The clamping voltage during ESD stress can be observed in the TLP-measured I-V characteristics, which should be less than the failure voltage of internal circuit. The clamping voltage as 1.3A TLP zapping (V clamp@1.3a), which is equivalent to ~kv HBM stress [34], of D P, stacked D P1 and D P (D P1+D P), stacked D P and D N with embedded SCR (D P +D N ), P-type RTSCR with 5 R TP (RTSCR P_5 ), and P-type RTSCR with 150 R TP (RTSCR P_150 ) are 4.4V, 6.9V, 5.6V, 5.4V, 5.6V, respectively. The V clamp@1.3a of D N, stacked D N1 and D N (D N1 +D N ), stacked D P1 and D N1 with embedded SCR (D P1 +D N1 ), N-type RTSCR with 5 R TN (RTSCR N_5 ), and N-type RTSCR with 150 R TN (RTSCR N_150 ) are 5.8V, 7.3V, 6.7V, 6.7V, 6.7V, respectively, as shown in Fig. 8. All these experimental results are listed in Table II. According to the TLP-measured I-V characteristics, the clamping voltages of test devices are sufficiently low for ESD protection in nanoscale CMOS process [35]. C. Very-Fast TLP I-V Characteristics Another very-fast TLP system is used to simulate the charged-device-model (CDM) ESD stresses [36]. Figures 9 and 10 show the very-fast-tlp-measured I-V characteristics of test devices between I/O and V DD and between V DD and I/O, respectively. The measurement results show that the RTSCR devices can turn on during such fast ESD events. Fig. 7. TLP-measured I-V characteristics of test devices between I/O and V DD, and zoomed in picture around triggering. Fig. 8. TLP-measured I-V characteristics of test devices between V SS and I/O, and zoomed in picture around triggering.

6 TABLE II MEASUREMENT RESULTS OF TEST DEVICES Devices Width ( m) HBM Robustness (kv) TLP V clamp@1.3a (V) C 0GHz (ff) FOM (V -1 pf -1 ) D P D P1+D P D P+D N RTSCR P_ RTSCR P_ D N D N1 +D N D P1 +D N RTSCR N_ RTSCR N_ Fig. 9. Very-fast-TLP-measured I-V characteristics of test devices between I/O and V DD, and zoomed in picture around triggering. Fig. 10. Very-fast-TLP-measured I-V characteristics of test devices between V SS and I/O, and zoomed in picture around triggering.

7 D. Parasitic Capacitance The parasitic capacitance of each test device is measured using an on-wafer S-parameter measurement system. The parasitic effects of the G-S-G pads have been removed using a standard open/short de-embedding procedure. Figures 11 and 1 show the extracted parasitic capacitances seen at the I/O of each test device. The parasitic capacitances of test devices at 0GHz (C 0GHz ) are listed in Table II. The P-type RTSCR devices have up to 48% capacitance reduction as compared to the D P, and the N-type RTSCR devices have up to 53% capacitance reduction as compared to the D N. 3.5, 4.5, 5.7, and 5.7 V -1 pf -1, respectively, and those of D N, D N1 +D N, D P1 +D N1, RTSCR N_5, and RTSCR N_150 are 3.4, 3.6, 4.1, 5., and 6. V -1 pf -1, respectively. The proposed ESD protection design with dual RTSCRs can perform the better ESD clamping ability and the lower parasitic capacitance. VII. CONCLUSION The low-c ESD protection design with dual RTSCRs have been developed in nanoscale CMOS process for high-frequency applications. The target of this work is to achieve the low clamping voltage during ESD current discharging conditions, and low parasitic capacitance under normal circuit operating conditions; therefore, the FOM of 1/(V clamp@1.3a C 0GHz ) is wished to be as high as possible. According to the experimental results of test chip, both P-type RTSCRs with 5 and 150 R TP perform the FOM of 5.7 V -1 pf -1, and the N-type RTSCRs with 5 and 150 R TN perform the FOM of 5. and 6. V -1 pf -1. The RTSCRs show the better FOM among the test devices. Measurement results verify the high-frequency performances and confirm the ESD protection ability of P-type and N-type RTSCRs. Therefore, the proposed ESD protection design with dual RTSCRs can be a good solution for high-frequency applications. Fig. 11. Measured parasitic capacitances of test devices between I/O and V DD. ACKNOWLEDGMENTS The authors would like to thank National Chip Implementation Center (CIC), Taiwan, for the support of chip fabrication, and Hanwa Electronic Ind. Co., Ltd., Japan, for setting up the ESD tester. The authors would also like to thank Prof. Ming-Dou Ker and his research group in National Chiao Tung University, Taiwan, for their great help during measurement. REFERENCES Fig. 1. Measured parasitic capacitances of test devices between V SS and I/O. VI. COMPARISON For the high-frequency applications, the ESD protection devices are wished to have low parasitic capacitance under normal circuit operating conditions, and good voltage clamping ability during ESD current discharging conditions. The figure of merit (FOM) in this work is defined as FOM 1 (3) V C clamp@1.3a 0GHz where V clamp@1.3a is the clamping voltage as 1.3A TLP zapping, and C 0GHz is the parasitic capacitance at 0GHz. The FOM of D P, D P1+D P, D P+D N, RTSCR P_5, and RTSCR P_150 are 3.8, [1] S. Rangan, T. Rappaport, and E. Erkip, Millimeter-wave cellular wireless networks: potentials and challenges, Proceedings of the IEEE, vol. 10, no. 3, pp , Mar [] D. Fritsche, G. Tretter, C. Carta, and F. Ellinger, Millimeter-wave low-noise amplifier design in 8-nm low-power digital CMOS, IEEE Trans. Microwave Theory and Techniques, vol. 63, no. 6, pp , Jun [3] A. Abidi, CMOS microwave and millimeter-wave ICs: The historical background, in Proc. IEEE Int. Radio-Frequency Integration Technology Symp., 014. [4] H. Gossner, Design for ESD protection at its limits, in VLSI Technology Symp. Dig. Tech. Papers, 013 [5] J. Li, R. Mishra, M. Shrivastava, Y. Yang, R. Gauthier, and C. Russ Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies, in Proc. Electrical Overstress/Electrostatic Discharge Symp., 011. [6] S. Sangameswaran, J. Coster, D. Linten, M. Scholz, S. Thijs, L. Haspeslagh, A. Witvrouw, C. Hoof, G. Groeseneken, and I. Wolf, ESD reliability issues in microelectromechanical systems (MEMS): A case study on micromirrors, in Proc. Electrical Overstress/Electrostatic Discharge Symp., 008. [7] V. Shukla and E. Rosenbaum, Charged device model reliability of three-dimensional integrated circuits, IEEE Trans. Device and Materials Reliability, vol. 15, no. 4, pp , Dec [8] F. Roger, W. Reinprecht, and R. Minixhofer Process variation aware

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Dutton, RF ESD protection strategies: Codesign vs. low-c protection," Microelectronics Reliability, vol. 47, no. 7, pp , Jul [3] C. Nguyen, Radio-Frequency Integrated-Circuit Engineering. John Wiley & Sons, 015. [33] S. Voldman, ESD: RF Technology and Circuits. John Wiley & Sons, 006. [34] J. Barth, K. Verhaege, L. Henry, and J. Richner, TLP calibration, correlation, standards, and new techniques, IEEE Trans Electronics Packaging Manufacturing, vol. 4, no., pp , Apr [35] C. Duvvury, Paradigm shift in ESD qualification, in Proc. IEEE Int. Reliability Physics Symp., 008. [36] Y. Zhou, J. Hajjar, D. Ellis, A. Olney, and J. Liou, A new method to evaluate effectiveness of CDM ESD protection, in Proc. Electrical Overstress/Electrostatic Discharge Symp., 010. Chun-Yu Lin (SM 17) received the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Taiwan, in 009. He is currently the Associated Professor with the Department of Electrical Engineering, National Taiwan Normal University, Taiwan, and also the Secretary-General of Taiwan ESD Association. His current research interests include ESD protection designs and biomimetic circuit designs. Chun-Yu Chen received the B.S. degree from the Department of Electrical Engineering, National Taiwan Normal University, Taiwan, in 017. His current research interests include ESD protection designs.