Characteristics analysis and optimization design of a new ESD power clamp circuit

Transcription

1 007 Microelectronics Reliability Microelectronics Reliability 50 (2010) Characteristics analysis and optimization design of a new ESD power clamp circuit Hongxia Liu *, Baojun Tang, Yue Hao Key Lab of Ministry of Wide Band-Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi an , China article info abstract Article history: Received 28 October 2009 Received in revised form 10 April 2010 As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmission structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/L ratio, the clamp can safely protect the gate of ESD power clamp devices from thermoelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The proposed structure has the advantages of low power and low cost, and can be used to the system-level ESD protection. Ó 2010 Elsevier Ltd. All rights reserved. 1. Introduction 2. Design of new ESD power clamp circuit In recent years, scaling down of the feature size of CMOS technology has caused a lot of reliability issues. Electrostatic Discharge (ESD) is one of the major reliability threat in the semiconductor industry for decades. It was reported that nearly 70% of failures in Integrated Circuits (ICs) technology is caused by ESD and Electrical Over Stress (EOS) [1]. So the design of ESD protection circuit in ICs is very important. As a part of protection circuit, the ESD power clamp circuit has been widely used in order to effectively protect the internal circuit from thermoelectric breakdown [2]. The emergence of more power lines in System on Chip (SOC) makes the design of ESD power clamp circuit become more challenging. Some researches on the new ESD protection device have been proposed, while the new structures of ESD protection circuit have seldom been reported. Some of the key advantages of power clamps based on NMOS transistor are no added process steps, relaxed layout constraints and easy SPICE simulation. All these advantages can shorten the development process and reduce the manufacturing cost. In this paper, a new transient ESD power clamp circuit of RC triggering is proposed, which adopts rising-edge triggering TSPCL D flip-flop [3] to turn on and time delay. Simulations results show that this clamp is immune to false triggering and power supply noise. The proposed new circuit can improve ESD protection ability effectively and reduce manufacturing cost greatly. * Corresponding author. Tel.: ; fax: address: hxliu@mail.xidian.edu.cn (H. Liu) ESD power clamp circuit of RC triggering At present, several different structures of ESD clamp circuit have been proposed [4 7]. This paper focuses on MOSFET ESD clamp circuit of RC triggering, its structure and node voltage are shown in Fig. 1a and b respectively. When ESD event occurs, the potential of node A becomes 1. Because of the delay of inverters, the potential of node B turns to 1, the clamp NMOS transistor keeps on for about 60 ns, ESD current in power line can be sufficiently discharged. Beside the NMOS transistor of big size, the clamp devices can be replaced by Substrate Triggering Field Oxide Device (STFOD) and Silicon Controlled Rectifier (SCR) Design of new ESD power clamp circuit Ref. [8] presented the first RC triggering active clamp circuit in 1993, some different types of clamp circuits are reported in the following years. Fig. 2 shows the structure of general clamp, it consists of three sections: detector element, delay element and clamp device. The detector element is used to detect the ESD event and keep the clamp device on with delay element. The detector is usually implemented with a simple RC network. The rise time of ESD event is between 100 ps and 100 ns, while the rise time of normal power supply is in millisecond range. Therefore, it is easy to distinguish the ESD event from normal power supply when the typical value of RC time constant is in microsecond range. However, for some special applications, such as hot-plug operations or switching networks controlling the sleep power mode in lowpower high-performance microprocessors, the fast rise time is in /$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi: /j.microrel

2 1088 H. Liu et al. / Microelectronics Reliability 50 (2010) (a) Structure of clamp circuit (b) Voltage of nodes A and B Fig. 1. Generic ESD power clamp circuit of RC triggering. Fig. 2. Structure of general clamp. microsecond range or even hundreds of nanoseconds [9,10]. Thus, the generic ESD power clamp circuit might be triggered under normal operations because of false triggering. In this paper, a high performance TSPCL D-type flip-flop is proposed as the delay element. Fig. 3 shows the structure of TSPCL D flip-flop. Compared with the level triggered clamp circuit, the new clamp circuit with rising-edge triggered D-type flip-flop becomes more effective to avoid false triggering. When a fast rising edge of potential ramp occurs at node CLK, the voltage of node Qb is always the inverse of node D. Fig. 4 shows the block diagram of the new clamp circuit. The input voltage of node D is always kept at 1. When an ESD event comes, the rising edge is detected by RC network at the CLK input, the output voltage of Qb becomes 0, the voltage of node Q becomes 1 because of the inverter and the clamp device M0 turns on. The clamp circuit keeps M0 conductive during the whole ESD event Optimization of new ESD clamp circuit The major limitation of this new clamp is that this clamp will keep on after ESD event, and transistor M0 cannot be turned Fig. 3. Structure of TSPCL D-type flip-flop. Fig. 4. Block diagram of the new clamp circuit. off. In order to solve this problem, the TSPCL D-type flip-flop should be modified based on its application. By adding a leakage transistor, the new clamp circuit can be turned off. The leakage transistor Mr acts as a pseudo-nmos transistor to pull up the voltage of node Qb. In order to charge the node Qb very slowly, Mr should be designed in a very small size. The W/L ratio of transistor M9 should be designed at least ten times bigger than Mr. When an ESD event comes, the voltage of both nodes Y and CLK is 1, M8 and M9 turn on, and transistor M10 turns off. Because the transistor M9 has much more pull down capability than Mr, the voltage of node Qb is changed to 0, and M0 turns on. After the ESD event, the voltage of node CLK is changed to 0, M8 turns on, M9 and M10 turn off. Hence, the voltage of Qb keeps at 0. However, the voltage of node Qb will be pulled up to 1 ultimately because of continued conduction of Mr, thus M0 turns off. It can be seen that the W/L ratio of transistors M9 and Mr is the key factor in implementing the turn off mechanism of new clamp. The bigger the W/L ratio of transistors M9 and Mr is, the longer conduction time the clamp device will take. In order to get the appropriate time to discharge the ESD current, designer can change the W/L ratio of transistors M9 and Mr, which can provide redundancy for circuit design. The schematic of new clamp can be further simplified. Input of the flip-flop is always 1, M1 turns on, and M3 is not activated. Hence, the transistors M1, M3 and M2 can be simply eliminated. Meanwhile, the potential of node X is always 0, M6 turns on, and M5 is not activated. Hence, the transistors M6, M5 and M4 can also be simply eliminated without affecting the circuit operation under both ESD and normal power-up conditions. It should be considered that before a power-up event comes, voltage of V DD is 0, M7 is in on-state. Voltage of node Y is

3 H. Liu et al. / Microelectronics Reliability 50 (2010) , and M10 is in on-state too. When a power-up event happens, M7 is turned off due to the charging of C1, and then M7 is turned on with the discharging of C1. Therefore, node Y is charged to 1 only after M7 being turned on, and M10 is delayed to turn off. While the voltage of Qb has already been charged to 1, the gate voltage of M0 is 0. Otherwise, M0 will be turned on when the circuit is powered up, and the circuit cannot work. Meanwhile, we noticed that Mr is such a narrow channel transistor, it cannot pull up the voltage of Qb immediately and effectively when the circuit is powered up. Fig. 5 shows the optimization structure of the new clamp circuit. The optimization structure needs few transistors and can reduce the manufacturing cost. Comparison of the structure of TSPCL D-type flip-flop in Fig. 3 and whole clamp circuit in Fig. 4, the optimization clamp circuit in Fig. 5 shows that it has the same performance to act as the ESD protection circuit under the normal operating conditions. It should be noted that we use a single transistor M1 in Fig. 5 to instead the inverter in Fig. 4. A single transistor M1 can make the gate voltage of clamp device M0 be lower than V DD, transistor M0 can be protectively effectively. Therefore a dynamic, inverse and delay NMOS transistor M1 is used to instead the inverter. The clamp circuit has the advantage of dynamic transmission structure. 3. Characteristic analysis and parameters optimization of new power ESD clamp circuit Base on SMIC 1.8 V VLP lm CMOS process, the new clamp circuit is stimulated and verified. In order to prevent false triggering, the RC time constant is set to 45 ns. R1 = 30 kx, C1 = 1.5 pf. The performance of new clamp circuit is simulated under different process corners using HSPICE Voltage characteristic By applying a ramp voltage from 0 to 5 V with the rise time of 10 ns as the ESD event, one can see the voltage of CLK and Q Fig. 5. Optimization structure of the new clamp circuit. under the SS process corner, which is shown in Fig. 6. The gate voltage of clamp device is kept at 1.2 V for about 60 ns. It s enough for clamp device to discharge ESD current. Three factors affecting the hold time of gate voltage are RC time constant, voltage amplitude of ESD pulse, and structure of delay element. The bigger the RC time constant is, the longer the hold time will be. Comparison of Figs. 1 and 6 show that the RC time constant of general clamp is two times larger than that of new clamp when the hold time of gate voltage is the same. So the new clamp takes up less area. We suppose that the transistors M9 and Mr will charge or discharge for the total capacitance of node Qb independently, the voltage V M9 shows the impact of M9 on the voltage of node Qb. Similarly, the voltage V Mr shows the impact of Mr on the voltage of node Qb. Therefore, the ratio A = V M9 /V Mr represents impact of M9 and Mr on the voltage of node Qb, it also determines the hold time of gate voltage, which is shown in A ¼ V M9 =V Mr ¼ Q M9 = Q Mr ¼ I M9T ¼ð W Þ l n C ox L M9 ðv 2 GS V T Þ 2 =ð W Þ L Mr ¼ l n l p ðð W L Þ M9 =ðw L Þ Mr Þ 9 ¼ I M9 =I Mr >= ðv 2 GS V T Þ 2 >; = I MrT l p C ox where, the ratio l n /l p is a constant, the value of A is determined by (W/L) M9 /(W/L) Mr. The control factor of gate voltage hold time is defined as R =(W/L) M9 /(W/L) Mr. Table 1 shows the relationship between R and hold time of gate voltage under ESD condition. Value of R changes from 1 to 33, the step is 4. By changing the control factor R, one can get the different hold time under the same ESD condition. From Fig. 6, one can see that the gate voltage is the same for different hold time R = 14 and R = 22. Fig. 7 shows the hold time of gate voltage increases with increasing R. When R is less than 10, the hold time is so short that clamp cannot discharge the ESD current completely. When R is larger than 20, the hold time change slightly. However, it will take up much more area and increase cost. When the value of R is between 10 and 20, the hold time changes greatly. R can change the hold time of gate voltage effectively. The optimized parameter R is set between 10 and 20. In some applications such as hot-plug operations proposed above, the new clamp circuit is simulated under very fast power supply conditions with the rise time of 1 ls. Fig. 8 shows the voltage of node Q for a 1 ls power supply event. It can be seen that the gate voltage of M0 rises to 0.13 V and goes back to zero immediately. Compared with the threshold voltage of 0.40 V, the M0 cannot be turned on. So the new clamp circuit can avoid false triggering for a very fast power supply. In order to explain the excellent immunity to false triggering, the rise times of power supply are reduced to 160 ns, 80 ns, 40 ns, respectively. Fig. 9 shows the voltage of node Q under different rise time. The result shows that the clamp does not trigger if the rise time is higher than 160 ns. Hence, the new ESD clamp circuit can avoid false triggering more effectively. Therefore, this new clamp can be widely used in high-speed integrated circuits. ð1þ Fig. 6. Voltage amplitude of nodes CLK and Q under ESD condition.

4 1090 H. Liu et al. / Microelectronics Reliability 50 (2010) Table 1 Relationship between R and hold time of gate voltage under ESD condition. R Hold time 4 ns 7 ns 55 ns 61 ns 65 ns 67 ns 69 ns 70 ns 71 ns Hold time (ns) Noise characteristic Fig. 7. Relationship between R and hold time of gate voltage under ESD condition. Under normal operating condition, the power noise occurs because of high switching rates, which can trigger the clamp circuit. So we simulate the noise characteristics of clamp circuit under the worst operating condition by adding a pseudorandom pulse. The added noise has a rate of 250 MHz and amplitude of 600 mvp-p. Here 200 ps edges have been used for each of the bit transition times [5,11]. From Fig. 10, it can be seen that the peak current of clamp is approximately 140 la, which is smaller than that in Refs. [5,11]. Hence, the new clamp is immune to power noise. R 3.3. ESD response characteristic In order to evaluate the effectiveness of this clamp under ESD conditions, its response to a 2-kV-HBM stress is simulated in circuit level. The 2-kV-HBM stress is applied to the V DD line of the proposed clamp in the device simulator. The HBM test is the main ESD test method which is widely used in industry, and it is defined in the MIL-STD-883 standard. In this standard, the HBM waveform has a rise time of less than 10 ns and a delay time of ns. For a 2-kV-ESD stress, the peak current is 1.33A ± 10%. The transient current waveform used in our simulations is shown in Fig. 11a. Fig. 11b shows the ESD response. From Fig. 11b, it can be seen that the maximal voltages of nodes V DD and Q are 7.07 V and 6.22 V respectively and the clamp keeps on for about 2 ls, which is enough to discharge the ESD energy completely. Since the gate-oxide breakdown voltage of transistors in a 0.18 lm CMOS technology under 100 ns voltage pulse is around 10 V [12]. This new clamp can protect the core circuit against a 2-kV-ESD stress Leakage current characteristic As we know, the ESD clamp circuit should not work under normal operating condition. Therefore, the value of sub-threshold leakage current is an important parameter for power consumption estimation. When the circuit does not work, the clamp NMOS transistor works in the sub-threshold region, the leakage current can be expressed as following: I D ¼ Wl n L kt q 2 e 0 e s q 2qN A V s 1=2 n 2 i e qvs kt N A 1 e qv DS kt ð2þ Fig. 8. Voltage of Q for a rapid power supply of 1 ls. Fig. 9. Voltage of node Q under different rise times.

5 H. Liu et al. / Microelectronics Reliability 50 (2010) (a) Voltage of node Q (b) Leakage current Fig. 10. Variation of voltage of node Q and leakage current with power noise. (a) 2-kV HBM ESD current waveform (b) ESD response Fig kV-HBM ESD current waveform and ESD response. One can see that the leakage current and is proportional to the W/L ratio. The small W/L ratio is better for low power. While the circuit works normally, the clamp NMOS transistor works in the saturation region, the leakage current can also be expressed as following: I Dsat ¼ l n WC OX ðv GS V T Þ 2 2L So the larger the W/L ratio is, the bigger the leakage current will be, and the better the NMOS transistor discharge ability will be. Therefore, one should balance these two factors and choose the proper W/ L ratio for the clamp NMOS transistor. Under SS process corner, a varying power voltage from 0 V to 3.3 V is applied for DC analysis. Fig. 12 shows variety of the leakage current with voltage under normal operating conditions. It can be seen that the corresponding leakage current increases from 0 to 183 pa. The leakage current is 65 pa when the operating voltage ð3þ is 1.8 V, which is much lower than the leakage current 1 na under 1.8 V process. Compared with other turn off mechanism [13], this new turn off mechanism can more effectively reduce the gate voltage of clamp device to very low, so the surface potential V s in clamp device is very low, and the leakage current will be small. So, the power consumption of new clamp is very small System-level ESD test In recent years, the system-level ESD test has become more important. It has been reported that ESD protection circuits may fail under system-level test, even it has passed the component-level test of human-body model of ±2 kv, machine model of ±200 V, and charged-device model of ±1 kv [14 16]. When the chip is applied with system-level test, the power line provides a very high

6 1092 H. Liu et al. / Microelectronics Reliability 50 (2010) Fig. 12. Variety of the leakage current with voltage under normal operating conditions. underdamped sinusoidal voltage. As a result, the leakage current of clamp circuit may increase significantly. The clamp circuit may not turn off and cause latch-up failure. Hence, it becomes necessary that the circuit should implement system-level ESD test. Simulation of system-level test is done by applying an underdamped sinusoidal voltage to V DD as follows [17]: Vðt A Þ¼V 0 þ V a expð ðt t d ÞD a Þsinð2pf ðt t d ÞÞ In order to simulate the clamp under system-level test, the parameters of the equation are set as: V 0 = V DD = 1.8 V, V a = 14.6, Vt d = 50 ns, D a = s 1, f = 20 MHz. The voltage is applied to the V DD line of the new clamp circuit. Fig. 13 shows the voltage of node Q during system-level ESD test. It can be seen that the maximum voltage is 1.93 V at 406 ns, but it reduces immediately. After several microseconds, the voltage of node Q and V DD remain at 0 V and 1.8 V respectively. Therefore, the new clamp circuit passes the system-level test as well Layout of new clamp circuit ð4þ For the same hold time of gate voltage, the less area of clamp circuit takes up, the lower manufacturing cost will be. The general clamp has the disadvantages that it takes up much layout area and need more cost. Furthermore the area of resistance and capacitance is nearly 2/3 that of whole clamp circuit. Comparison of Figs. 1 and 6 show that the RC time constant of general clamp circuit is two times larger than that of the new clamp circuit when the hold time of gate voltage is the same. Hence, the new clamp circuit takes up less area. Fig. 14 shows the layout of the generic clamp circuit and the proposed clamp. Compared with the area of general clamp circuit, the new clamp circuit can save layout area as much as 24.8%. 4. Conclusion It is well known that there are some disadvantages for the generic power clamp circuit, such as the easy false triggering, large layout area, and high power consumption. In this paper, an optimization ESD power clamp circuit is proposed and its electrical characteristics are analyzed systematically. It can increase the turn on time significantly. Meanwhile, the layout area of new clamp circuit can save as much as 24.8%, so the fabrication cost can be decreased greatly. In addition, there are no new structure device and special circuit in the presented clamp circuit, so this new structure can be widely used in different process including nanometer-level feature size, such as 65 nm. Simulation results show that this clamp is immune to false triggering and power supply noise. Finally, the HBM measurement results show that the new clamp circuit can endure 2-kV-ESD stress. Fig. 13. Voltage of node Q and V DD during system-level ESD test. Fig. 14. Layout of the generic clamp circuit and the new clamp circuit.

7 H. Liu et al. / Microelectronics Reliability 50 (2010) Acknowledgments This work was supported in part by the Project of National Natural Science Foundation of China (Grant No , ), in part by the Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China Program (Grant No ). References [1] Huang Jin Biao, Wang Ge Wen. ESD protection design for advanced CMOS. In: SPIE proceedings series, Nanjing; p [2] Ker Ming Dou. Whole-chip ESD protection design with efficient V DD to V SS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans Electron Dev 1999;46(1): [3] Elgamel Mohamed, Darwish Tarek. Noise tolerant low power dynamic TSPCL D flip-flops. In: Proceedings of the IEEE computer society annual symposium on VLSI; p [4] Poon Steven S, Maloney Timothy J. New considerations for MOSFET power clamps. Microelectron Reliab 2003;43(7): [5] Smith Jeremy C, Boselli Gianluca. A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. Microelectron Reliab 2005;45(2): [6] Semenov Oleg, Sarbishaei Hossein, Sachdev Manoj. A transient power supply ESD clamp with CMOS thyristor delay element. In: Proceeding of in the EOS/ ESD symposium, Anaheim; p [7] Chen Shih Hung, Ker Ming Dou. Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13 lm CMOS technology. In: Proceedings of IEEE international conference on electronics, circuits and systems, ICECS, St. Julian s; p [8] Merrill R, Issaq E. ESD design methodology. In: Proceeding of the EOS/ESD symposium; p [9] Stockinger Michael, Miller James W, Khazhinsky Michael G, Torres Cynthia A, Weldon James C, Preble Bryan D, et al. Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies. In: EOS/ESD symposium; p [10] Rabaey Jan, Chandrakasan Aanantha. Digital integrated circuits: a design perspective. 2nd ed. Beijing: Publishing House of Electronics Industry; p [11] Sarbishaei H, Semenov O, Sachdev M. A new flip-flop based transient power supply clamp for ESD protection. IEEE Trans Dev Mater Reliab 2008;8(2): [12] Mergens M, Armer J, Jozwiak P, Keppens B, De Ranter F, Verhaege K, et al. Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90 nm technologies. CICC 2004:251. [13] Li J, Rosenbaum E, Gauthier R. A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection. In: EOS/ESD symposium; p [14] Ker Ming Dou, Yen Cheng Cheng. Investigation and design of on-chip powerrail ESD clamp circuits without suffering latchup-like failure during systemlevel ESD test. IEEE J Solid-State Circ 2008;43(11): [15] Yen Cheng Cheng, Ker Ming Dou. The effect of IEC-like fast transients on RCtriggered ESD power clamps. IEEE Trans Electron Dev 2009;56(6): [16] Ker Ming Dou, Sung Yu Yu. Hardware/firmware co-design in a 8-bits microcontroller to solve the system-level ESD issue on keyboard. Microelectron Reliab 2001;41(3): [17] Ker Ming Dou, Hsu Sheng Fu. Physical mechanism and device simulation on transient induced latchup in CMOS ICs under system-level ESD test. IEEE Trans Electron Dev 2005;52(8):