Transient Latch-up in Large NFET Switch Arrays. Nathaniel Peachey, RFMD, Inc. Rick Phelps, IBM, Inc.

Transcription

1 Transient Latch-up in Large NFET Switch Arrays Nathaniel Peachey, RFMD, Inc. Rick Phelps, IBM, Inc.

2 Biography Nathaniel (Nate) Peachey received his Ph.D. in Physical Chemistry in 1994 from the University of Nebraska Lincoln and then was awarded a Director s Funded Postdoctoral Fellowship at the Los Alamos National Laboratory. In 1996 he joined Atmel Corporation in Colorado Springs. Over the next several years Dr. Peachey held various positions at Atmel including process engineer, technology development engineer, device engineer, and circuit design engineer. In 2005 Dr. Peachey accepted the position of engineering manager for the ESD design group at RF Micro Devices. In this capacity he was responsible for the development of ESD protection for all of the technologies that RFMD designed in including both silicon and GaAs. Dr. Peachey has authored and coauthored over 20 technical journal submissions. He has also submitted 6 patents that have either been granted or are pending. In 2009 Dr. Peachey was elected to the Board of Directors for the ESD Association. Currently he is serving as the Standards Chair for the Association.

3 Abstract Power management circuits often employ large switching arrays to provide a stable voltage output. The switching arrays for a typical dc-dc converter consist of PMOS and NMOS arrays that are located at the output of the device. Rapid switching of this output driver can result in significant voltage transients on both VBAT and GND. These switching transients, if not properly managed, can also result in detrimental displacement currents in the substrate that can be large enough to trigger snapback during operation. Prototype products were designed and tested in hardware. Initial results showed that the parts could not be operated at the nominal supply voltage without damaging the parts. Failure analysis showed damage on the large NMOS transistor in the switching array. This was due to snapback voltage lowering such that the NMOS transistor entered snapback and then failed. The initial analysis suggested that the large displacement currents from the switching of the PMOS arrays provided the substrate current that triggered snapback. To address this, triple wells (isolated PWELL) were implemented. Testing of the revised designs indicated that, particularly for larger designs, the triple well implementation did not completely solve the problem. Additional review of the device physics of the snapback process indicated that the switch transient could couple into the substrate through the NMOS drain in such a manner to initiate snapback. Addressing this required decreasing the substrate ties in the isolated PWELL. This presentation also touches on the testing and characterization of these products. Questions are raised about characterization of this problem such that there is no danger in implementing these designs in final products.

4 Problem Defined DC-DC-Converter Schematic VBAT Feedback and Control Driver Circuit MP0 MN0 LX External Filter VOUT L C Circuit on Chip GND

5 Problem Defined DC-DC-Converter Operation DC-DC converter intended to supply a stable voltage. Must be loaded with external filter before operating. Switching array transistors are up to 100+ mm total width. Efficiency of operation is improved by rapid switching of the transistor arrays. Switching of these transistor arrays is known to produce transients. Transients are increased by increased switching speeds.

6 Problem Defined NFET arrays failed when parts were initially tested. Failures observed even at supply voltages that were below nominal voltage for the part. VBAT MP0 MN0 GND Transients immediately suspected as the source of the failures.

7 Investigation Voltage transients measured on the LX node show 1.6V over shoot at 5V VBAT Negative going transients are as low as -2V when the PFET switches off. When the PFET switches off, the NFET will turn on. NFET switching on (V gs >0) will also lower the snapback voltage.

8 Investigation Measurements of the NFET under substrate biased conditions changes snapback voltage. If a substrate voltage of 1V is applied the snapback voltage reduces to around 6.5V. If the transients observed on LX node couple into substrate, NFET snapback voltage could be reduced.

9 Snapback Physics NMOS Snapback Physics Source N+ S/D P-sub Gate Poly Gate R sub Parasitic Bipolar Device Drain N+ S/D

10 Snapback Physics Triggering the Parasitic Bipolar Device V sx = [(M 1)(I DS + I C ) I B ]R sub where: V sx is substrate voltage M is the avalanche multiplication factor I DS is the drain to source current I C is the collector current I B is the base current R sub is the substrate resistance Simplistically, snapback in silicon occurs when the V sx becomes 0.7V higher than the source voltage.

11 Snapback Physics Triggering the Parasitic Bipolar Device From the previous equation there are 3 ways to trigger snapback: 1. Increase I DS done by raising gate voltage and turning on transistor. (gate-aided breakdown). 2. Add substrate current (-I B ). (Substrate triggering mechanism.) 3. Transient voltage at the drain. I C = C CB (dv CB /dt) where: C CB is collector/base (drain to substrate) capacitance V CB is the collector to base voltage

12 Failure Mechanism Analysis Triggering the NFET Array PMOS Array P+ P+ NWELL NMOS Array N+ N+ Switching transients generated in PMOS array become displacement currents in substrate. If the displacement currents are large enough due to the size of the PMOS array, these can provide a current to the NMOS array. This displacement current is generated at the same time that the NMOS gate goes high (combining mechanisms #1 and #2 listed above).

13 TCAD Simulations Simulated Structures PMOS NMOS Guard Rings Standard structure showing guard rings and PMOS and NMOS devices. Isolated PWELL structure showing triple well surrounding NMOS. Isolated PWELL tied to quiet ground.

14 Voltage TCAD Simulations PWELL swings up over 1V during switching Any transient over 0.7V can lower snapback voltage DNWL DNWL Std Std LX Node P-WELL Node Isolated PWELL (DNWL) shows no transients at all

15 Implementing Isolated PWELL PMOS Array P+ P+ NWELL NMOS Array N+ N+ The simplest method to isolate NMOS place in a triple well. This was done with mixed results: For smaller products, the failure voltage level raised to well above required limits. For larger arrays, while the failure voltage was raised, it remained lower than was acceptable. Further analysis was needed.

16 Additional Failure Mechanism Switching Transients at the Drain Switching transients generated at drain CLK CLK LX Filter These transient, if large enough, can provide enough C CB (dv CB /dt) current to trigger the parasitic bipolar device. The addition of DNW will not help avoid this type of triggering. Addressing this problem required reducing the spacing between substrate ties.

17 Discussion of Results The two different snapback triggering mechanisms. Smaller arrays displacement current explained failure mechanism. Larger arrays both mechanisms contribute to failures. Actions: 1. All NMOS arrays must be placed in isolated PWELL. 2. For larger products, spacing between substrate ties must also be reduced.

18 Test Considerations 1. Latch-up testing difficult to perform. Any switching of part during test set-up will damage it. 2. V MAX for parts set lower than 1.5 times the supply voltage. 3. Snapback mechanism a form of transient latch-up. The following questions remain: a. Should there be a test to characterize this vulnerability? b. Is there any increased vulnerability to early failure due to transients pushing NFET close to snapback?

19 Conclusions Power management products are becoming increasingly common for handheld consumer products. These present unique problems in managing the snapback and subsequent failure of the large NMOS array. Two different mechanisms have been identified that are responsible for the failures observed in these products. Characterization and reliability checking for these products remains a concern.

20 References Blerina Aliaj, Vladislav Vashchenko, Philippe Lindorfer, Andrew Tcherniaev, Maxim Ershov, Juin j. Liou, Peter Hopper, Study of Power Arrays in ESD Operation Regimes, EOS/ESD Symposium 2010, pp C. Gezgin, Predicting Load Transients Response to Output Voltage in DC-DC Converters, 19 th Annual IEEE Applied Power Electronic Conference and Exposition, 2004, pp D. Chen, L. He, X. Yan, A Current-Mode DC-DC Buck Converter with High Stability Independent of Load and Supply Voltage, IEEE International Symposium on Industrial Electronics, 2006, pp J. R. M. Luchies, C. G. C. M. de Kort, J. F. Verweij, Fast turn-on on an NMOS ESD protection transistor: measurements and simulations, Journal of Electrostatics, Vol. 36 (1995), pp

21 Acknowledgments The authors would like to thank Robert Gauthier at IBM for information on the NMOS transistor and Mike Kay at RFMD for the oscilloscope screen images of the DC-DC converter output signals.